JPH0134489B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a protection circuit in a frame synchronization circuit of a PCM communication device.

Background Art In the field of PCM communication, frames are often repeatedly sent synchronously. Therefore, when the synchronization pulse arrangement is sequential, the frame synchronization pulses detected from this synchronization pattern are monitored, and when the synchronization breaks down, a hunting control signal is generated and the frame phase is shifted to obtain correct synchronization. . However, in order to prevent hunting from starting due to a simple transmission line code error, it is determined that synchronization is lost only when the detected synchronization pulses are out of sync for a certain period of time, and a hunting control signal is generated. A synchronization protection circuit is provided that monitors the synchronization state for a certain period of time even after the transmission starts, and prevents erroneous synchronization judgments due to transmission line code errors. FIG. 1 shows a digital competition counter type circuit. two counters
CT ₁ and CT ₂ are preset counters that count out and are reset when they reach set count values N ₁ and N ₂ . Counter CT ₁ receives the synchronous coincidence pulse,
In addition, counter CT ₂ counts synchronization mismatch pulses, so if a concentrated error occurs due to synchronization loss, one of the competing counters CT ₁ and CT ₂ will
CT ₂ first reaches the count number N ₂ and sets the flip-flop FF. Then, since the AND circuit is opened, a hunting pulse is generated every time a mismatch pulse (in the following, synchronization at the beginning of a word is omitted) is generated to perform synchronization pull-in. During the hunting period when the hunting control signal (output of the flip-flop FF) is logic "1", this circuit uses a counter via the OR circuit every time a mismatch pulse occurs.
Since CT ₁ and CT ₂ are reset, the counters CT ₁ and
There is no accumulated count value remaining in CT ₂ . However, when the synchronization state is reached and the number of coincident pulses increases intensively, the counter _CT1 reaches a count value of _N1 , and the flip-flop FF is reset.
In this case, the hunting control signal becomes logic "0" and closes the AND circuit, so no hunting pulse is generated. By the way, in such a synchronized state, counter CT ₂ accumulates the count when a mismatch pulse comes, but if there is a temporary burst error, the counter will continue to accumulate even when the burst error disappears and the steady state is reached. Since the count number remains in CT ₂ , even if a small number of mismatched pulses that do not cause synchronization loss occur afterwards, the set count value N ₂ will be reached.
Start hunting. Therefore, there is a disadvantage that synchronization is broken. This situation will be discussed in more detail in the description of the circuit according to the invention.

DISCLOSURE OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned drawbacks and to improve the conventional contention method so as to avoid entering a hunting state when bit errors occur densely due to temporary burst errors. The purpose of the present invention is to provide a synchronization protection circuit with improved synchronization protection.

In order to achieve the above object, the present invention provides a signal that resets a counting counter in a conventional digital competition type circuit every time a coincidence pulse is detected during a synchronized and non-hunting period. The present invention is characterized in that it is provided with a counter reset control circuit that generates a counter reset.

Since the present invention has the above configuration, when there is a loss of synchronization, normal hunting is performed to pull in the synchronization, and even when there is a bit error such as a burst error in a synchronized state, the synchronization is prevented. There is no. In other words, if one matching pulse occurs, the mismatching number counter is reset and the count becomes zero, so even if there is a small number of mismatching pulses after that, the hunting control signal will not be set to logic "1", which occurs in conventional circuits. This can prevent loss of synchronization.

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described with reference to the drawings. FIG. 2 is a diagram showing a circuit block of the embodiment, and FIG. 3 is a time chart showing its operation. In FIG. 2, a data signal and a bit clock enter a synchronization detection circuit 1 from an input terminal, and a detected synchronization signal is extracted from a synchronization pattern within each frame. The detected synchronization signal is guided to a coincidence detection circuit 2 and a mismatch detection circuit 3, and if it matches or does not match the normal synchronization signal output from the frame counter 12, a coincidence pulse is sent from the corresponding detection circuits 2 and 3, respectively. , a mismatch pulse is output. The match pulse and the mismatch pulse are counted by a match counter 4 and a mismatch counter 5, respectively, and when they reach preset count values N ₁ and N ₂ , the flip-flop 6 is reset and set. When the output Q of the flip-flop 6 is set, the AND circuit 7 outputs a hunting pulse every time a mismatch pulse is output from the mismatch detection circuit 3, blocks the bit pulse passing through the clock gate 11, and changes the phase by one bit. Trying to adjust the shift synchronization. The synchronization signal is a pulse train passed through the clock gate 11 and sent to the frame counter 1.
Generated by counting by 2. Further, the counters 4 and 5 are reset via the OR circuit 8 for each counter output and for each hunting pulse. The explanation so far is the same as the conventional protection circuit, but in the present invention, a counter reset control circuit 10 is provided, and this circuit receives the coincidence pulse from the coincidence detection circuit 2 and the output of the flip-flop 6. A signal obtained by inverting the hunting control signal by an inverter 9 is added. The counter reset control circuit 10 outputs an output pulse when both of the above two signals are logic "1", resets the counters 4 and 5 via the OR circuit 8, and also resets the frame counter 12. Therefore, the circuit 10 may be constructed using a well-known AND gate.

The operation of this circuit will be explained below with reference to FIG. Set count value N ₁ of two counters 4 and 5,
N ₂ is determined depending on the appearance of mismatched pulses, but
Transmission systems with low jitter, for example for broadcasting satellites.
For PCM reception, N ₂ is set larger than N ₁ . This is because even if a mismatch pulse happens to come in, the hunting state is not immediately entered in the case of normal synchronization. In FIG. 3, N ₁ =5 and N ₂ =6. Figure 3A shows the original synchronization signal that should originally be sent. 3A to 3F show the state of each part of a conventional protection circuit, and FIGS. 3G to 3C show the protection circuit of the present invention. 3A and 3C show the occurrence of mismatched pulses and match pulses. Since the synchronization is initially out of order, the probability of appearance of a mismatched pulse is greater than the probability of appearance of a match pulse. Therefore, the mismatch counter 5 that counts the number of mismatch pulses reaches the set count value N ₂ at time t ₁ before the match counter 4 does.
Then, the flip-flop 6 is set and both counters 4 and 5 are reset. As shown in FIG. 3F, flip-flop 6 sets the hunting control signal to logic "1" and the circuit enters the hunting state. Each time a mismatch pulse occurs, both counters 4 and 5 are reset, so that no count value remains as shown in FIGS. 3E and 3E. If the hunting state continues, synchronization will be achieved at time _t2 , but the count number of match counter 4 will reach the set count value _N1.
The process waits until time _t3 , at which time the hunting control signal is set to logic "0". In this way, conventional circuits provide effective synchronization protection in the case of normal synchronization loss. However, in a synchronous state, if the data signal has dense bit errors such as burst errors,
That is, an inconvenient situation occurs as shown by C in FIG. 3A. For example, after time _t3 , the synchronization state is maintained and the hunting control signal is at logic "0", so the two counters 4 and 5 are reset when the match number counter 4 reaches the set count value _N1 . The mismatch number counter 5 has left a count up to that point. By the way, from time t ₄ to time t ₅ , the dense mismatch pulses shown in C appear,
If the match number counter 4 does not reach the set count value N ₁ yet, the count number of the mismatch number counter 5 reaches the set count value N ₂ as shown in FIG.
It's getting closer to. Therefore, even if a small number of mismatched pulses occur thereafter, a reset operation is initiated. In Figure 3, as shown in A and B, after time t ₅ , there are 4 coincidence pulses.
Then, when one non-coincidence pulse is input, the coincidence number counter 5 reaches the set count value _N2 and is reset, and the flip-flop 6 is set to set the hunting control signal to logic "1". Even if there is a bit error such as a burst error, if the synchronization is not lost in the first place, once a hunting state occurs with a small number of matching pulses as described above, if one more matching pulse arrives, the synchronization will be lost. It will shift due to hunting. It takes time to recover from this "out of synchronization" caused by the circuit itself. All of the coincidence pulses A surrounded by the dotted line in Figure 3A were originally coincidence pulses, except for one, but the synchronization signal output from the frame counter 12 is out of sync due to the "synchronization loss" of the circuit itself. Therefore, it was detected as an apparently mismatched pulse. In the circuit according to the present invention, when the hunting control signal is at logic "0", that is, when in the synchronous state, the dense bit errors shown at C from time _t4 as shown in FIG. C of A
), the hunting control signal is inverted by the inverter 9 and enters the counter reset control circuit 10 as logic "1", so the reset signal shown in FIG. is generated and sent to the counter 4 through the OR circuit 8.
Reset 5. Therefore, the count accumulated in the mismatch counter 5 shown in FIG.
Thereafter, even if a small number of mismatch pulses occur at time _t6 , the set value _N2 is not reached and the hunting control signal is not set to logic "1". Therefore, there is no "out-of-synchronization" caused by the circuit itself. As shown in Figure 3, C and S, even after time t ₆ , the same mismatch and coincidence pulses are still occurring. Here, the third
The coincidence pulse indicated by B in the figure is the original coincidence pulse. In other words, according to the circuit of the present invention, even if a bit error signal like that shown in FIG. “Kuzushi”
does not occur.

Note that the frame counter 12 counts only the number of bits of the frame and outputs a synchronization signal, but the second
The circuit shown in the figure is wired so that it is reset by a reset signal from the counter reset control circuit 10. However, this is to ensure operation, and it goes without saying that even when no reset signal is generated, if the count reaches the set value, it will be reset and counting will start again.

As explained above, according to the present invention, it is possible to operate as a conventional competitive synchronization protection circuit when there is a synchronization shift, and to perform synchronization protection even when there are dense code errors during a synchronization state. can.

[Brief explanation of drawings]

Figure 1 is a circuit block diagram showing a conventional competition type synchronization protection circuit, Figure 2 is a circuit block diagram of an embodiment of the present invention, and Figure 3 explains the operation of the circuits in Figures 1 and 2. This is a time chart for 1...Synchronization detection circuit, 2...(Synchronization) coincidence detection circuit, 3...(Synchronization) mismatch detection circuit, 4...(Synchronization)
Match number counter, 5... (synchronization) mismatch number counter, 6... flip-flop, 7... AND circuit, 8
...OR circuit, 9...Inverter, 10...Counter reset control circuit, 11...Clock gate, 12...
frame counter.

Claims (1)

[Claims] 1. In a conflict counter type PCM frame synchronization protection circuit that performs hunting by counting synchronization mismatch pulses and synchronization match pulses, each time a synchronization match pulse is detected during a period in which hunting is not performed, the synchronization mismatch pulse counting counter is activated. and a counter reset control circuit for generating a signal for resetting a synchronization pulse counting counter.