JPS59223037A - Synchronization protecting circuit - Google Patents

Abstract

PURPOSE:To cause no hunting state even if a bit error is massed and generated, by providing a controlling circuit for generating a signal for resetting a counter whenever a coincidence pulse is detected in a period in which synchronization is taken and no hunting is executed. CONSTITUTION:Set count values N1, N2 of two counters 4, 5 are determined by an appearance state of a dissidence pulse. In case a hunting control signal is logic ''0'', namely, in a synchronized state, even if a mass-like bit error exists, a hunting control signal is inverted by an invertor 9 and inputted as logic ''1'' to a counter reset controlling circuit 10, therefore, whenever a coincidence pulse arrives, a reset signal is generated, and the counters 4, 5 are reset through an OR circuit 8. Accordingly, a count number accumulated in the dissidence number counter 5 is also reset immediately when only one coincidence pulse comes, therefore, even if a few dissidence pulses come thereafter, they do not reach the set value N2, and the hunting control signal does not become logic ''1''. Accordingly, ''step-out'' caused by the circuit itself does not occur either.

Description

TECHNICAL FIELD The present invention relates to a protection circuit in a frame synchronization circuit of a PCM communication device.

BACKGROUND ART In the field of PCM communication, frames are often sent periodically and repeatedly. Therefore, when the synchronization pulse arrangement is sequential, the frame synchronization pulses detected from this synchronization pattern are monitored, and when synchronization breaks down, a nonting control signal is generated and the frame phase is shifted to ensure correct synchronization. It has gained. However, in order to prevent hunting from starting due to a simple transmission line code error, it is determined that synchronization has been lost and a hunting control signal is generated only when the detected synchronization pulses are out of sync for a certain period of time, and a synchronization state is entered by hunting control. A synchronization protection circuit is provided that monitors the synchronization state for a certain period of time even when the transmission line code is incorrect, and prevents incorrect synchronization judgment due to an incorrect transmission line code.

FIG. 1 shows a digital competition counter type circuit. The two counters CT, , Cr2 are preset counters that count out and are reset when they reach the set count value N, , N2. Since the counter CTl counts the synchronization coincidence pulses and the counter CT2 counts the synchronization mismatch pulses, if a concentrated error occurs due to synchronization loss, the counters CT1. Of Cr2, the counter CT2 counts first, and when the number reaches N2, the flip-flop FF is set. Then, since the AND circuit is opened, the mismatch pulse (the synchronization at the beginning of the word will be omitted below) generates the hunting pulse and performs synchronization pull-in. (output of
Since the counters cT, , Cr2 are reset via the R circuit, the counters CT, Cr2 are reset.

No accumulated count value remains in Cr2. However, when the synchronization state is reached and the number of matching pulses increases intensively, the non-counter CT reaches a count value of N, and the flip-flop FF is reset. In this case, the non-taking control signal is logical ((since it becomes OII and closes the AND circuit), no sitting pulse is generated. By the way, in such a synchronized state, when a mismatch pulse comes, the counter CT2 accumulates the count number. However, if there is a temporary burst error, the count number remains in the counter CT2 even when the no-strike error disappears and the steady state is reached, so a small number of mismatched pulses that do not lose synchronization will occur afterwards. Even when the count reaches the set count value N2, counting starts.This results in the disadvantage of breaking the synchronization.This situation will be described in more detail in the description of the circuit according to the present invention.

DISCLOSURE OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks, and to solve the problem in cases where bit errors occur densely due to temporary burst errors, etc.
An object of the present invention is to provide a synchronization protection circuit which improves the conventional competition method and prevents a hunting state from entering.

In order to achieve the above object, the present invention resets a counting counter every time a coincidence pulse is detected during a synchronized period in which no matching is performed in a conventional digital contention type circuit. The present invention is characterized in that it is provided with a counter reset control circuit that generates a signal.

Since the present invention has the above-mentioned configuration, when there is a loss of synchronization, normal ... If there are matches/(Rus h''--), the mismatch counter will be reset and the Jt count will be zero, so even if there is a small number of mismatch pulses, the non-matching control signal will not be There is no need to set the logic level to 1'', and the loss of synchronization that occurs in conventional circuits can be prevented.

Best mode for carrying out the invention Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing the circuit block diagram of the embodiment, and FIG. 3 is a time chart showing its operation. As shown in FIG. 2, a data signal and a bit clock enter the synchronization detection circuit 1 from the input terminal, and a detected synchronization signal is extracted from the synchronization pattern within each frame. The detected synchronization signal is guided to the coincidence detection circuit 2 and the mismatch detection circuit 3, and if it matches or does not match the normal synchronization signal output from the frame counter 2, the above-mentioned detection is performed according to t. A coincidence pulse and a mismatch pulse are output from circuits 2 and 3. Concordance pulse, mismatch/<Russe, respectively” as match number counter 4. When the discrepancy counter 5 reaches a preset constant count value N, . . . N2, the flip-flop occurs.

6), set. When the output Q of the flipflop 6 is set, the AND circuit 7 also outputs a notating pulse every time the mismatch detecting circuit 3 outputs a mismatch nockle h''.
It attempts to block the bit noise passing through 1 and shift the phase by 1 bit to achieve synchronization. The synchronization signal is generated by counting the pulse train passing through the clock gate 11 with a frame counter 2. Further, the counter 4.5 is reset via the OR circuit 8 every time the counter outputs. The explanation so far is the same as that of the conventional protection circuit, but in the present invention, when the counter reset control circuit 10 is hit (this time; the match from the match detection circuit 2), it is destroyed. , and a signal obtained by inverting the converting control signal, which is the output of the flip-flop 6, by an inverter 9. Count Chriseno! - The control circuit 10 outputs an output pulse when both of the above two words are logic "1", and sends a reset signal to the counters 4 and 5 via the OR circuit 8, and also resets the frame counter 12. Therefore, the circuit]0 may be configured with a well-known AND gate.

The operation of this circuit will be explained below with reference to FIG. The set values N1 and N2 of the two counters 4 and 5 are determined depending on the occurrence of mismatched pulses, but in a transmission system with low jitter, for example, I) CM reception for broadcasting satellites, N,
is larger than N. Even if a mismatched pulse happens to occur, after that (d normal period) 1. This is because in the case of Jl, the hunting state is not immediately entered. In FIG. 3, N is set to 5°N2-6. FIG. 3 (7) shows the original synchronization signal that should originally be sent. Figure 3 B) to C1)
) shows the status of each part of a conventional protection circuit.
Figure 3 (=V) to (a) show the protection circuit of the present invention. Because of the deviation, the probability of appearance of a mismatched pulse is greater than the probability of appearance of a matched pulse. Therefore, the mismatch number counter 5, which counts the number of mismatch pulses, precedes the match number counter 4 and reaches the set count value N2 at time 8, setting the flip-flop 6 and resetting both counters 4 and 5. As shown in FIG.
II, the circuit enters the...
When a non-coincidence pulse occurs, both counters 4 and 5 are reset each time they occur, so no count value remains as shown in Figure 3 (E). If the non-taking state continues, synchronization may be achieved at time 2, but the count number of the coincidence counter 1 reaches the set count value N1, and the number of matches reaches the set count value N1, and the non-taking control signal is not activated at this time. Logic + I o rr. In this way, conventional circuits provide effective synchronization protection in the case of normal synchronization loss. However, in a synchronous state, when the data signal has dense bit errors such as Nost errors, ie, as shown by C in FIG. 3(a), an inconvenient situation occurs. For example, after time t1, the synchronization state is maintained and the hunting control signal is at logic "O", so the two counters 4 and 5 are reset when the match number counter 4 reaches the set count value N. The mismatch number counter 5 remains counting up to It. by the way,
If the dense mismatch pulses shown in C come from time t4 to time t1, and the match number counter 4 still does not reach the set count value N1, the count number of the mismatch number counter 5 will change as shown in Figure 3). is the setting noun count value N2
((It's getting closer.

Therefore, even if a small number of V mismatch pulses occur thereafter, the reset operation is started. In Fig. 3, as shown in (A), after time 1, when there are 4 matching pulses and 1 non-matching pulse, the non-matching number counter 5 reaches the set count value N2, is reset, and the no. Set the block flop 6 to 71 and set the control signal to logic ++1. Once a hunting state occurs due to a mismatch pulse, if another mismatch pulse comes, the synchronization will be lost due to this hunting.It takes time to recover from the "loss of synchronization" caused by this circuit itself. Except for one of the mismatched pulses A surrounded by the dotted line in Figure 3 (A), they were originally "coincidence pulses" but were output from the frame counter 2 due to the "synchronization" of the circuit itself. This is because the synchronization signal shifted, so it was detected as a match pulse.In the circuit according to the present invention, when the hunting control signal is logic 110 II, that is, when in the synchronization state, the As shown in Figure 3 (C), the dense bit errors shown in C from time t4 (Figure 3 (2)
)), the hunting control signal is inverted by the inverter 9 and enters the counter reset control circuit 10 as a logic "Y", so every time a coincidence pulse arrives, the signal shown in FIG. A reset signal is generated to set the counters 4 and 5 via the OR circuit 8.

Therefore, the accumulated count of the mismatch counter 5 shown in FIG. 3) is reset immediately after one match pulse is received. Even if a small number of mismatch pulses occur at this point, the set value N2 is not reached and the hunting control signal is not closed to logic ++1++. Therefore, the circuit itself ((there is no "out-of-synchronization" caused by 5 K t, as shown in Figure 3 (g), 1' as before)
Occurrence of inconsistent pulses and coincident pulses is observed. This is also the coincidence pulse shown by B in Figure 3). In other words, according to the circuit of the invention, "Fig. 3 (
Even if a focus error signal as shown in C in (a) occurs during the synchronization state, the hunting state will not be entered, and no "out of synchronization" caused by the circuit itself will occur.

Note that the frame counter 2 counts the number of bits of a frame and outputs a synchronizing signal, but in the circuit shown in FIG. 2, it is wired so as to be reset by a reset signal from the counter reset control circuit 10.

However, this is to ensure operation, and it goes without saying that even when a reset signal is not generated, if the count reaches the set value, it will be reset and start counting again.

As explained above, according to the present invention, it operates as a conventional competitive synchronization protection circuit when there is a loss of synchronization, and it is also possible to perform synchronization protection even if there are dense code errors during the synchronization state. can.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing a conventional competition type synchronization protection circuit, and FIG. 2 is a circuit block diagram of an embodiment of the present invention.
FIG. 3 is a time chart for explaining the operation of the circuits shown in FIGS. 1 and 2. FIG. 1...Synchronization detection circuit, 2...(Synchronization) coincidence detection circuit, 3...(Synchronization) mismatch detection circuit, 4...(Synchronization) coincidence number counter, 5...(Synchronization) mismatch number Counter, 6...Flip-flop, 7...AND circuit, 8...OR circuit, 9...Inverter\10...Counter reset control circuit, [l...Rirl
Cockgate, ]2...Frame counter. Patent applicant ShinNippon Electric Co., Ltd.

Claims (1)

[Scope of Claim] In a PC and M frame synchronization protection circuit of a contention counter type that performs hunting by counting synchronization mismatch pulses and synchronization match pulses. A synchronization protection circuit comprising a counter reset control circuit that generates a signal for resetting the counting counter every time a synchronization coincidence pulse is detected during a period in which hunting is not performed.