JPS6148252A - Pcm synchronizing system - Google Patents

Abstract

PURPOSE:To attain forward/backward protecting function by reviving a time window when the number of times of coincidence exceeds consecutively a prescribed number of times so as to bring the state to the steady-state in the system performing two state operations as steady-state and hunting state. CONSTITUTION:So long as a detection synchronizing signal 2a is a window at the steady-state, a synchronizing signal 15a is outputted to attain forward protection. When a dissident counter 6 overflows, the state moves to the hunting state. When a detected synchronizing signals 2a exists in the hunting state, a synchronizing signal 15a is outputted. When no detection synchronizing signal 2a exists, a pseudo synchronizing signal 15a appears a normal position of N-clock by the preceding synchronizing signal 15a. When this state is consecutive, repeated by N2 times and the coincident counter 7 overflows, the Q output of the flip-flop 13 goes to logical ''1'', the window is formed again so as to attain backward protection.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame synchronization system for PCM transmission system. Here, the PCM transmission system is intended for reception signals generally transmitted in the PCM system, including satellite communications, digital audio, and the like.

[Conventional technology]

Recently, the OPCM method has come to be used not only in communication systems but also in a wide range of general equipment.While high quality is expected from the OPCM method, code errors always exist, so it is required to have the ability to correct errors. Ru. If the synchronization signal is not correctly reproduced from the received data, the error correction ability will be significantly reduced. In interleaved received data, the effect extends to all data that is interleaved.

In the PCM system, since frames are sent repeatedly periodically, this periodicity is used to constantly monitor the synchronization state and when a synchronization error is detected, the frame phase rasrus (hunting) of the frame counter is detected. In this case, a synchronization protection circuit is provided to prevent a hunting state from occurring due to a temporary transmission line code error.

As the above-mentioned synchronization system, a digital contention counter method is known.

This method compares the detected synchronization signal detected from the synchronization pattern of the data signal with the synchronization signal of a frame counter that inputs a pit clock and rotates at the frame period, detects the number of matches and mismatches, and detects the number of matches and mismatches. When the number exceeds a certain number, the controller enters a hunting state and generates a hunting pulse every time a mismatch pulse occurs, shifts the phase of the frame counter, and generates a synchronization signal.

[Problem that the invention seeks to solve]

The conflict counter method statistically determines synchronization based on the number of matches and mismatches. Therefore, this method does not work effectively in cases where the detection synchronization signal is missing or appears at another remote location, which has a decisive effect on the code error correction ability. On the other hand, it has the disadvantage that it tends to enter a hunting state due to start-up errors such as jitter.

The object of the invention is to eliminate the above-mentioned drawbacks and, in the above-mentioned case, to
It is an object of the present invention to provide a PCM synchronization system that correctly reproduces synchronization signals and has appropriate forward and backward protection functions.

[Failure to solve the problem]

The PCM synchronization system according to the present invention leads a detected synchronization signal to the clear terminal of a frame counter through a time window, and uses one output of a pulse generation circuit that generates various timing pulses by tecoding the output of the frame counter as a synchronization signal. It has an output configuration and operates in two states: a steady state and a hunting state.

For the pulse generation circuit, N is the number of frame clocks.

Where A is an arbitrary number of clocks, the number of clocks A and W of the frame counter is (N-A) to (N+A).

Corresponding to N and N+A, the signal (A) is a synchronization signal that sends out to the outside, and the signal (B) is a time window signal.

The signal (N) is a coincidence detection signal with the detected synchronization signal.

The signal (N+A) is clocked into the frame counter by the number of clocks A
Output as a load signal to be loaded into.

In a steady state, if the detected synchronization signal is within the time window, the frame counter is reset and the pulse generation circuit outputs the signal (A), and if it is not within the time window, it also outputs the signal (N+A). loads the frame counter and outputs the signal (A).

If the detection synchronization signal does not continue a certain number of times within a time window, the time window disappears and a hunting state is entered. In the hunting state, the detection synchronization signal always resets the frame counter and outputs a signal (N ) and the detected synchronization signal, a signal (A) is output in the case of a match, and a signal (N+A) is output in the case of a match.
) loads the frame counter and outputs the signal (A), and means for restoring the time window and transitioning to a steady state when the number of matches continues to exceed a certain number of times by the match/mismatch detection means. have.

〔Example〕

FIG. 1 is a circuit block diagram of an embodiment of the present invention, and FIG. 2 is a flowchart showing the operation of the circuit.

The data human input signal is converted into a parallel signal by a serial/parallel conversion circuit 1, and a detected synchronization signal 2a is input from a synchronization detection circuit 2 to the PCM system of the present invention. The detection synchronization signal 2a is input to the clear terminal of the frame counter 4 via a window set in the intra-window coincidence detection circuit 3. Frame counter 4 counts pit clocks extracted from the received signal. Here, the window is a time window through which a signal passes within a certain time period, and is a pulse generation circuit 5 which will be described later.
It is generated by the signal (W) of The pulse generating circuit 5 decodes the output of the frame counter 4 and generates various timing pulses. The number of clocks is A corresponding to the number of clocks of the frame counter 4.

When W=(N-A) to (N+A), N, N+A, signal (A) 51, signal (W) 54, signal (N) 5
A 5° signal (N+A) 56 is output. Number of clocks A
He will explain the signals corresponding to +l and N/2.

Signal (A) 51 is passed through OR circuit 15 to synchronization signal 15
It is output to the outside as a.

This circuit has two different operating states, tentatively called a steady state and a hunting state, and the transition between these states is detected by the mismatch counter 6, match/mismatch detection means 11. AND circuit 12
・14. This is done by a flip-flop 13.

Hereinafter, the operation of the circuit will be explained step by step with reference to the flowchart shown in FIG. All signals are treated as negative signals.

Steady state: The left side of FIG. 2 is the steady state.

It is detected whether the detected synchronization signal 2a is within the window W=(NA) to (N+A) set in the intra-window coincidence detection circuit 3 (Pl). Here, N is the normal number of frame clocks, an arbitrary number of clocks that is extremely smaller than AFiN. Q of the flip-flop 13 changes only when there is a change in the outputs of the mismatch counter 6 and the match counter 7, but now, due to the output of the match counter 7 when transitioning from the hunting state to the steady state, s = "o" Q=
It is in the state of "1". Therefore, AND circuit 14 is open and signal (W) 54 forms a window. If the detected synchronization signal 2a is within the window, the signal 3
The frame counter 4 is reset as a (Pa).

At this time, the signal 3a is input to the mismatch counter 6 as a load pulse via the AND circuit 12, and Nl is set (
P2).

Since frame counter 4 has been reset, signal (A)
s1. Signals (W) 54, . . . and timing pulses are generated. Signal (A) 51 is synchronization signal 15
The signal (W) 54 forms a window again, and it is detected whether the next detection synchronization signal 2a is within the window (Pl).

When Ps - P4 is cycled, since A is usually much smaller than N, the synchronization signal 15a is the same as the previous synchronization signal 1.
It is output at approximately N intervals for 5aVc.

Next, when the detected synchronization signal 2a is not within the window (Pl), the signal 3a is not output, so the frame counter 4
is not reset and the signal (N+A
) 56 occurs, and the discrepancy counter 6 is counted up (
Ps) and load frame counter 4 (
Pa). At this time, the frame counter 4 is loaded with A, so it outputs the signal (A) 51, and the synchronization signal 15a is sent out to the outside (P7). If this state continues until the mismatch counter 6 overflows the set number Nl (P
a) Regardless of the detected synchronization signal 2a, the frame counter 4 outputs the signal (A) 51 as the synchronization signal 15a at a period of N. However, if it falls within the window even once, the mismatch counter 6 is set to NI again at P2.

In a steady state, even if the detected synchronization signal 2a fluctuates somewhat due to jitter or the like, as long as it is within the window, the synchronization signal 15 is output at approximately N cycles, and even if it deviates from the window, it continues for a predetermined number of N cycles. The synchronization signal 15 is output at a period of N unless it is separated. The loop from P5 to Ps corresponds to so-called forward protection. When the mismatch counter 6 overflows, a hunting state occurs.

Hunting state: Output 6a of discrepancy counter 6 is AND
N2 is set in the load signal pulse and the point coincidence counter 7 via the circuit 10 (P9). When this happens, the flip-flop 13 becomes Q="O", so the AND circuit 14 blocks the signal (W) 54. Therefore, a window is no longer formed, and no matter where the detected synchronization signal 2a appears, it passes through the window coincidence detection circuit 3 and resets the frame counter 4 (Pu).
The signal (A) 51 is the synchronization signal 15a due to the count A of
(Plg). In other words, it follows and outputs the detection synchronization signal 2a with a delay of A count. At this time, the output of the mismatch detection circuit 8 is input to the match counter 7 as a load pulse, and N2 is set (PH). When the detection synchronization signal 2a is lost, the frame counter 4 continues counting without being reset and the signal (N+A)
Output 56 and load frame counter 4 (PI
3). At that time, A is set and at the same time signal (A) 51
is output as the synchronization signal 15a.

In other words, in the hunting state, if there is a detected synchronizing signal 2a, the synchronizing signal 15a is output following it, and even if there is no detected synchronizing signal 2a, it is at the normal position of N clocks from the previous synchronizing signal 15a. A synchronization signal 15a appears.

Next, when the synchronization of the detection synchronization signal 2a is recovered and appears normally (Pro), the coincidence counter 7 counts up (Plg) by the output of the coincidence detection circuit 9, and the frame counter 4 is reset (PI3). %signal(
A) 51 appears as synchronization signal 1.5a. This state continues and repeats pta~P19°PIG N2 times.
If the coincidence force hanger overflows (PI9), the signal 7a causes the flip-flop 13 to become Q="l", a window is formed again, and a transition is made to a steady state. At this time, the mismatch counter 6 is loaded by the signal 7a, and N1 is set (P+s). The transition to steady state must be continued N2 times, and even once it is not normal and the signal (N) 5
If it does not match 5 (plo), the match counter 7 is set to the original value, so this is backward protection.

Even in the hunting state, the detection synchronization signal 2a is detected by the window (
Even if there are no people within N-A) to (N+A), there is little deviation from that. Therefore, it is almost sufficient to take measures against the case where the detected synchronization signal 2a is missing. However, although there is a small probability, after the synchronization output 15a is sent out as the signal (A) 51 due to erroneous detection of the detected synchronization signal, the detected synchronization signal 2a may arrive nearby. At this time, it is necessary to prevent the synchronization signal 15a from being output to the outside. This prohibition period is shown as a counter (A+
1) Let it be ~B, and here ~ let it be B-Ban. As a result, the first
In the figure, the frame counter 4 is A+1. l'J/2
When the clock hits, the timing pulse generation circuit 5 generates the signal (A+1) 52. A signal (N/2) 53 is generated, and this signal is applied to the s and it terminals of the flip-flop 16, and its output becomes 1'' between the clocks (A+1) and (N/2), and during this period, it is a synchronous signal. 15a is prevented from being sent out to the outside. Here, N/2 is a value appropriately determined from empirical rules.

〔Effect of the invention〕

In the synchronization system of the present invention, by setting a window in a steady state, it is strong against start-stop errors such as jitter that occur in places other than the synchronization signal, and in a hunting state, when the detected synchronization signal is lost due to a synchronization signal code error, A pseudo synchronization signal is sent to the regular position from the previous synchronization signal, and the detected synchronization signal is sent to another position (in the actual example, A-N/
2) when it appears, I try to ignore it. The transition between the steady state and the hunting state has functions of forward protection and rear protection, respectively.

[Brief explanation of drawings]

The drawings show an embodiment of the present invention, with FIG. 1 being a circuit block diagram and FIG. 2 being a flow chart for explaining the operation of the system. 2... Synchronization detection circuit, 3... In-window coincidence detection circuit, 4... Frame counter, 5...
・Pulse generation circuit, 6...discrepancy counter,
7... Match counter, 8... Mismatch detection circuit,
9... Match detection circuit, 10,12.14...
・ANI) circuit, 11... Match/mismatch detection means, 13° 16... Flip-flop, 15.
...OR circuit, 51 to 56...timing pulse: signal (A) to signal (N+A).

Claims (2)

[Claims] (1) In a PCM transmission system, a detected synchronization signal is guided through a time window to the clear terminal of a frame counter, and one output of a pulse generation circuit that decodes the output of the frame counter and generates various timing pulses is used as a synchronization signal. It has a configuration that outputs as
A PCM synchronized system that performs a state operation, wherein the pulse generation circuit has a clock number A of the frame counter, W=(N-A) to (N+A), where N is the number of frame clocks and A is an arbitrary number of clocks. ),
Corresponding to N and N+A, the signal (A) is a synchronization signal that sends out to the outside, the signal (W) is a time window signal, and the signal (N) is
is the coincidence detection signal with the detection synchronization signal, signal (N+A)
shall be outputted as a load signal to load the frame counter to the number of clocks A, and in a steady state, if the detected synchronization signal is within the time window, the frame counter is reset and the pulse generation circuit outputs the signal ( A), and even if it is not within the time window, the frame counter is loaded with the signal (N+A) and the signal (A) is output, and the detected synchronization signal continues to be constant within the time window. If there is no count, the time window disappears and a transition is made to a hunting state. In the hunting state, the detection synchronization signal always resets the frame counter and the signal (
If there is a match, the signal (A) is outputted, and if there is a mismatch, the signal (N+A) loads the frame counter and the signal (A) is outputted by means for detecting coincidence/mismatch between the frame counter (N) and the detected synchronization signal. A PC characterized in that it has means for restoring the time window and transitioning to a steady state when the number of matches continues to exceed a certain number of times by the match/mismatch detecting means.
M synchronization system. (2) In the hunting state, the detection synchronization signal is the number of clocks of the frame counter (A+1) to B(
2. The PCM synchronization system according to claim 1, further comprising means for preventing the signal (A) from being sent to the outside when B is within an arbitrarily set number equal to or less than NA.