JPH0345036A - Word synchronizing circuit - Google Patents

Abstract

PURPOSE:To avoid a burst error by storing a comparison signal outputted from a phase comparison means and sending a comparison signal to a reset control means when a deviation of each phase is consecutive for a prescribed number of times. CONSTITUTION:The phase of an edge pulse and that of a reset pulse are compared by a phase comparison means 115, the comparison signal is stored in a protection means 117 and when the phase shift is consecutive for a prescribed number of times, the signal is sent to a reset control means 116. An edge pulse is inputted to a count mean 113 as a reset signal in response to the comparison signal sent from the protection means 117 and the count means 113 is reset. Then the count means 113 is reset at a prescribed period corresponding to the word length and outputs a reset pulse. Thus, the protection means is active effectively to a digital error of a header signal to avoid the reset of the counter means and the induction of the burst error attended with the production of the digital error is prevented.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a word synchronization circuit that synchronizes data in units of words by transmitting and receiving header signals together with data. In order to avoid this problem, the header signal indicating the beginning of the input data is input, and the edge detection means outputs an edge pulse corresponding to the edge, and the demultiplexing means outputs a count value used for demultiplexing the input data input to the demultiplexing means. and outputs a reset pulse in response to a reset operation of a predetermined period corresponding to the word length,
Furthermore, there is a counting means capable of performing a reset operation in response to the input of a reset signal, a phase comparison means that compares each phase of the edge pulse and the reset pulse, and outputs a comparison signal indicating a shift in each phase; , and a reset control means that uses an edge pulse as a reset signal for the counting means, the word synchronization circuit holds the comparison signal output from the phase comparison means, and outputs the comparison signal when each phase shift continues a predetermined number of times. The present invention is characterized in that it includes a protection means that sends a signal to the reset control means.

[Industrial application field]

The present invention relates to a word synchronization circuit that synchronizes data in units of words by transmitting and receiving a header signal along with data.

[Prior Art] A conventional word synchronization circuit used in a communication device that transmits and receives signals by word synchronization compares the rise timing of a header signal received with data and the reset timing of an internal counter, and detects when a discrepancy occurs. Sometimes, word synchronization is achieved by forcibly resetting the internal counter at the rising edge of the header signal.

FIG. 4 is a diagram showing a state when the header signal is normally received.

The internal counter outputs counter values φl, φ2, . . . and a reset pulse at a predetermined period. In other words, as long as the rising edge of the header signal and the phase of the reset pulse match, the counter outputs (φ1, φ2, . . .
) and the serial data (A, B,...) are matched,
Normal reception occurs.

[Problem to be solved by the invention]

By the way, in conventional word synchronization circuits, word synchronization is performed according to the rising edge of the header signal, so if a digital error occurs in the header signal, the rising edge of this digital error is mistakenly recognized as the rising edge of the header signal. .

FIG. 5 is a diagram showing a state when a digital error occurs in the header signal.

For example, if a digital error occurs when data is "P", the internal counter is forcibly reset in response to the digital error, so the counter output becomes φ1. That is, data "P" was determined to be the beginning of a word (data "A"), and could no longer correspond to the following data, resulting in a burst error.

Note that at the next rise of the header signal, the internal counter is reset again, so normal reception operation is restored.

SUMMARY OF THE INVENTION The present invention has been made to solve these problems, and it is an object of the present invention to provide a word synchronization circuit that can avoid burst errors caused by erroneous synchronization in response to digital errors in header signals.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

In the figure, edge detection means 111 receives a header signal indicating the beginning of input data, and outputs an edge pulse corresponding to the edge.

The counting means 113 outputs a count value used for demultiplexing the input data input to the demultiplexing means 112, outputs a reset pulse in response to a reset operation of a predetermined period corresponding to the word length, and further outputs a reset signal. A reset operation is possible according to the input.

The phase comparison means 115 compares each phase of the edge pulse and the reset pulse, and outputs a comparison signal indicating a shift in each phase.

The reset control means 116 uses the edge pulse as a reset signal for the counting means 113 in response to this comparison signal.

The protection means 117 holds the comparison signal output from the phase comparison means 115, and sends the comparison signal to the reset control means 116 when each phase shift continues a predetermined number of times.

[Operation] The phases of the edge pulse and the reset pulse are compared in the phase comparing means 115, and a comparison signal indicating the result is output. The comparison signal is held in the protection means 117, and reset control means 11 when the phase shift continues a predetermined number of times.
6 is sent out.

In response to the comparison signal sent from the protection means 117, an edge pulse is input as a reset signal to the counting means 113, and the counting means 113 is reset. Thereafter, the counting means 113 performs a reset operation at a predetermined cycle corresponding to the word length and outputs a reset pulse.

That is, when the phase shift is not continuous by the protection means 117, it is considered that a digital error has occurred, and the reset control means 116 does not reset the counting means 113.
When the phase shift continues, it is regarded as a change in the phase of the header signal and the counting means 113 is reset, so that false synchronization due to digital errors can be avoided.

〔Example〕

FIG. 2 is a block diagram showing the configuration of an embodiment of the word synchronization circuit of the present invention.

In FIG. 2, an edge pulse (a) output from an edge detection circuit 211 that detects a rising edge of a header signal with a duty ratio of 50% is output from an exclusive OR circuit 21.
5 and one input terminal of each of the OR circuit 223 and the OR circuit 225 via the NOT circuit 221.

The clock that serves as the operating reference for the receiving device is the counter 213.
and the other input terminal of the OR circuit 223.

A counter output (e) output from the counter 213 that runs freely in response to an input clock is input to a multiplexing/demultiplexing circuit 239 that separates and outputs serial data.

Further, a reset pulse (W) output in response to the reset operation is input to the other input terminal of the exclusive OR circuit 215.

The output of the exclusive OR circuit 215 is input to the input terminal of a D-type flip-flop circuit (hereinafter referred to as "DFF") 227 via the NOT circuit 217. and each clock input terminal CLK of the DFF229.DF
The Q output of F227 is input to the input terminal of DFF 229 and one input terminal of NAND circuit 231.

The d output of the DFF 227 is input to one input terminal of the NAND circuit 233. The Q output of the DFF 229 is input to the other input terminal of the NAND circuit 231. D
The d output of the FF 229 is input to the other input terminal of the NAND circuit 233.

The output of the NAND circuit 231 is output from the NAND circuit 235.
The output of the NAND circuit 233 is input to one input terminal of the NAND circuit 237. The output of the NAND circuit 235 is input to the other input terminal of the NAND circuit 237 and the other input terminal of the OR circuit 225 as a reset inhibit signal (C).

The output of the NAND circuit 237 is output from the NAND circuit 235.
is input to the other input terminal.

Reset signal (d) output from the OR circuit 225
is inverted and input to the clear terminal CLR of the counter 213.

Note that the exclusive OR circuit 215 outputs the edge pulse (a)
The AND circuit 223 is configured to detect coincidence or mismatch of each phase of the edge pulse (a) and reset pulse), and supply a clock corresponding to the edge pulse (a) to each DFF 227 and 229. In addition, DFF227.229, NAND circuit 231.233.235.237, DFF227.2
Each of the 29 Q outputs (d output) is logic “0” (logic “
1), the reset inhibit signal (C
) from logic "1" to logic "0".

Here, the correspondence between FIG. 1 and FIG. 2 will be shown.

The edge detection means 111 corresponds to the edge detection circuit 211.

Counting means 113 corresponds to counter 213.

The phase comparison means 115 corresponds to the exclusive OR circuit 215 and the NOT circuit 217.

The reset control means 116 corresponds to the NOT circuit 221 and the OR circuit 225.

The protection means 117 corresponds to the DFF 227, the DFF 229, the NAND circuit 231, the NAND circuit 233, the NAND circuit 235, and the NAND circuit 237.

The operation of the circuit according to the embodiment of the present invention will be described below with reference to the timing diagrams shown in FIGS. 2 and 3.

In a normal state when a header signal without digital errors is being received (Fig. 3 ■), the counter 213, which runs freely according to the clock, outputs a normal counter output (e) to the demultiplexing circuit 239, and The reset is repeated at a predetermined period corresponding to the word length of the received serial data,
A reset pulse synchronized with the edge pulse (a) is output.

Therefore, the output of the exclusive OR circuit 215 is logic "0".
" is repeated, and each Q output of DFF227.229 becomes logic "1", so the reset inhibit signal (
C) continues to be in the logic “1” state, and the edge pulse (a
) is inhibited, and the counter 213 repeats the normal counting operation.

When a 1-bit digital error occurs in the header signal (Fig. 3 ■), the edge detection circuit 211 determines the digital error as a rising edge of the header signal and outputs an edge pulse (a). (b)
is not output, the exclusive OR circuit 215 detects a phase mismatch (outputs logic "1" as in the conventional case).

However, each Q output of DFF227.229 is logic "0"
, "1", so the reset inhibit signal (C)
is fixed at logic "1". That is, the cent signal (d) corresponding to the digital error is inhibited, and the counter 213 continues its normal counting operation and outputs a reset pulse 0)) at a predetermined period. Therefore, a match is made with the edge pulse (a) corresponding to the next header signal, and the counter 213 further repeats the normal counting operation.

In this way, for a 1-bit digital error,
The protection means of the DFF 227 to the NAND circuit 237 work effectively, and the counter 213 continues its normal counting operation without being reset for each digital error, making it possible to avoid burst errors in received data.

Furthermore, when a discrepancy occurs between the header signal and the counter output (e) (Fig. 3 ■), the counter operates in the same way as when a digital error occurs for the first header signal whose phase has changed. 213 is not reset and the reset pulse (b) is output at a predetermined period. However, since the phase of edge pulse (a) and reset pulse (b) is not lost even for the next header signal, DFF227.229
The respective Q outputs of both become logic "0". That is, each d output is both logical r1. J, the output of the NAND circuit 233 becomes logic "0", and the reset inhibit signal (C) becomes logic "0".

In this way, edge pulse (a) and reset pulse (a)
When the phase shift of the edge pulse (a) is continuously detected, the inhibition of the reset signal (d) corresponding to the edge pulse (a) is released, and the counter 213 is reset at that timing.

Thereafter, the phases of the reset pulse (b) and edge pulse (a) are reversed, and normal operation is performed.

[Effects of the Invention] According to the present invention, the protection means effectively works against digital errors on the header signal, and the resetting of the counting means can be avoided, thereby preventing burst errors from occurring due to the occurrence of digital errors. be able to.

4. Explanation of the drawings Figure 1 is a block diagram of the principle of the present invention, Figure 2 is a block diagram showing the configuration of an embodiment, Figure 3 is a timing diagram explaining the operation of the embodiment, and Figure 4 is a conventional normal diagram. FIG. 5 is an explanatory diagram of word synchronization when a conventional digital error occurs.

In the figure, 111 is an edge detection means, 113 is a counting means, 115 is a phase comparison means, 116 is a reset control means, 117 is a protection means, 213 is a counter, 215 is an exclusive OR circuit, 217.221 is a NOT circuit, 223.225 is an OR circuit, 227.229 is a D-type flip-flop circuit (DFF)
, 231.233.235.237 are NAND circuits, and 239 is a demultiplexing circuit.

Principle block diagram of the present invention No. figure clock Middle) Reset pulse ~) Reset pulse (b) Reset pulse Timing diagram explaining the operation of the embodiment figure

Claims (1)

[Claims] (1) A header signal indicating the beginning of input data is input,
An edge detection means (111) that outputs an edge pulse corresponding to the edge, and a count value for demultiplexing the input data input to the demultiplexing means (112), and a predetermined period corresponding to the word length. a counting means (113) capable of outputting a reset pulse in response to a reset operation of the reset signal and further performing a reset operation in response to input of a reset signal; a phase comparison means (115) that outputs a comparison signal indicating , and a reset control means (115) that uses the edge pulse as a reset signal for the counting means (113) in accordance with the comparison signal.
A word synchronization circuit comprising: holding a comparison signal output from the phase comparison means (115), and transmitting the comparison signal to the reset control means (116) when each phase shift continues a predetermined number of times; A word synchronization circuit characterized in that it comprises a protection means (117) for transmitting a signal to a user.