JPS61148939A - Frame synchronization system - Google Patents

Abstract

PURPOSE:To attain high stable frame synchronization by transmitting alternately two kinds of frame synchronizing data with different bit patterns at each frame and taking it as the frame synchronization state when one received frame is synchronized. CONSTITUTION:Reception data fed to an input terminal IN is inputted to a bit synchronizing circuit 1, where a bit clock pulse BTCK is recovered. Two kinks of frame synchronizing data AS, BS having different patterns are arranged alternately at each frame in the reception data, and the synchronizing data AS, BS are detected in synchronization with the BTCK by frame synchronizing pattern detection circuits 2, 3 for words A, B. The pulse BTCK is counted by a bit counter 4, from which frame pulses AFSYNC and BFSYNC whose phases are shifted by 180 deg. at two frame interval are generated and the phase is discriminated with the output of the circuits 2, 3 by phase coincidence discrimination circuits 5, 6 respectively, and when any frame is synchronized, the counter 4 is not initialized and a frame synchronizing signal is outputted from a gate 10.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a frame synchronization method in digital data transmission such as PCM data transmission.

(Background of the Invention) In digital data transmission, when a burst error occurs, there is a risk of losing frame synchronization. In particular, when a long burst error occurs, frame synchronization becomes unstable. 0 (Object of the Invention) The present invention has been made in view of the above, and provides a frame synchronization method that makes it easy to achieve frame synchronization when errors are likely to occur frequently, such as when burst errors are likely to occur, and solves the above problems. The purpose is to

(Structure of the Invention) The present invention alternately uses frame synchronization data consisting of two different patterns every 17 frames as frame synchronization data, determines the pattern of the received friend frame synchronization data, and determines the frame synchronization phase. The present invention is characterized in that it is determined that the frame is in a synchronized state when at least one of the frames is synchronized.

(Example of the invention) The present invention will be explained below with reference to Examples.

FIG. 1 is a diagram showing a frame structure according to the present invention, and FIG. 2 is a block diagram showing an example of a frame synchronization circuit that receives received data according to the frame structure of the present invention.

One frame is composed of frame synchronization data, data words, code error correction words, and code error detection words. The bit pattern of the frame synchronization data consists of two types of bit patterns, which are alternately different every frame, and whose bit lengths are set to be the same bit length. In FIG. 1, A5 indicates first frame synchronization data, Bs indicates second frame synchronization data,
Their bit patterns are different. The data word, code error correction word and code ab detection word are collectively Nl, N2 . ...is shown. Hereinafter, the frame containing the first frame synchronization data λB is the A word frame, and the frame containing the second 7-frame synchronization data Bs is the B word frame.
It is written as word frame.

The received data supplied to the input terminal IN is supplied to the bit synchronization circuit 1, and the bit synchronization circuit 1 reproduces the bit clock pulse B T CK of the received data.

The received data supplied to the input terminal INK is supplied to the A word frame synchronization pattern detection circuit 2 and the B word frame synchronization pattern detection circuit 3, and the bits of the frame synchronization data As in the received data are detected in synchronization with the bit block pulse BTCK. Pattern detection is performed,
Similarly, the bit pattern of the frame synchronization data BS in the received data is detected.

The A word frame synchronization pattern detection circuit 2 and the B word frame synchronization pattern detection circuit 3 are composed of, for example, a serial/parallel shift register that converts received data into parallel data in synchronization with the bit clock pulse BTCK;
The output of the shift register is frame synchronization data As(Bs
), the frame synchronization data As ( Bs), the A-word synchronous data detection signal pulse AFW and the B-word synchronous data detection signal pulse BFW are output separately.

On the other hand, the bit clock pulse BTCK is supplied to the bit counter 4 for counting, and the bit clock pulse BTCK is generated from the bit counter 4 at intervals of 2 frames as shown in FIG. A word frame pulse AF8YNC and B word frame pulse BF8Y
NC is generated.

Therefore, the A word frame pulse AF8YNC is synchronized with the A word frame, and the B word frame pulse BF8Y
Each NC is generated in synchronization with the B word frame.

Output AFW of A word frame synchronization pattern detection circuit 2
and the output AF8YNC of the bit counter 4 are supplied to a phase coincidence determination circuit 5 to detect coincidence of both phases. Similarly, the output B of the B word frame synchronization pattern detection circuit 3
FW and the output BF8YNC of the bit counter 4 are supplied to a phase coincidence determination circuit 6, where m- of both phases is detected. Here, the phase-number construction circuits 5 and 6 use a predetermined algorithm,
For example, if the phase mismatch occurs, the output AF8YNC (BFSYNC
) occurs over several pulses, it is determined that the phases do not match.

The phase match output AWD (high potential output) of the phase match determination circuit 50 and the phase match output BWD (high potential output) of the phase match determination circuit 60 are supplied to the NOR gate 7, and the NOR gate 7 determines whether the phases match with either one. It is detected that the determination has been made. Therefore, the output WD of the NOR gate 7 becomes a high potential only when the output AWD=BWD=low potential and phase matching is not detected in the circuits 5 and 6. On the other hand, the output AFW of the A word 7 frame synchronization pattern detection circuit 2 and the output BFW of the B word 7 frame synchronization pattern detection circuit 3 are supplied to the OR gate 8, and the output WF of the OR gate 8 and the output of the NOR gate 7 WD is supplied to a Nant gate 9, and the output of the OR gate 8 opens the gate of the Nant gate 9, and the output of the Nant gate 9, which is an inversion of the output WD of the NOR gate 7, initializes the bit counter 4.

Bit counter 4 output AFSYNC(!-BFSYN
C is supplied to the OR gate 10 to obtain a claim synchronization signal from the OR gate 10.

Therefore, in one embodiment of the present invention configured as described above, frame synchronization data As and Bs in received data are
When either one of the frames is synchronized, the bit counter 4 is not initialized, and when both are out of frame synchronization, the bit counter 4 is initialized and the frame is synchronized. Also,
Furthermore, frame synchronization data As is included in the received data.

Even if there is a bit pattern that is the same as the frame synchronization data As and a bit pattern that has a predetermined correlation with it other than the Bs part, there is also a bit pattern that is the same as the frame synchronization data BS and a bit that has a predetermined correlation with it. Even if a pattern exists,
The bit synchronization data As is determined by the phase coincidence determination circuit 5.6.
, the output of the A word frame synchronization pattern detection circuit 2 and the output of the B word frame synchronization pattern detection circuit 3 based on bit patterns in parts other than the BS are rejected by the phase coincidence determination circuits 5 and 6, resulting in frame synchronization malfunction. Never. In addition, the phase matching determination circuit 5
and 6 is the output AFSYNC2B of bit counter 4
Since the output AWD and BWD are generated according to a predetermined algorithm, such as not outputting the output AWD and BWD even if a phase mismatch is detected until FsYNc is counted to a predetermined value, the number of times a phase mismatch is detected is reduced. become.

(Effects of the Invention) As explained above, according to the present invention, frame synchronization data with different patterns are arranged for each frame.
A system that is robust against long burst errors, where the interval between two word frame synchronization patterns is effectively two frames apart.
Furthermore, if at least one of the bit patterns of the two types of frame synchronization data satisfies frame synchronization, it is determined that the frame synchronization state is established, so that a highly stable frame synchronization operation is performed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a frame structure according to the present invention. FIG. 2 is a block diagram showing an example of a frame synchronization circuit that receives received data according to the frame structure of the present invention. FIG. 3 is a waveform diagram showing the output of the bit counter in one embodiment of the present invention. 1...Bit synchronization circuit, 2 and 3...A and B
Word frame synchronization pattern detection circuit, 4...bit counter, 5 and 6...phase coincidence determination circuit.

Claims (1)

[Claims] For each frame, frame synchronization data consisting of two different bit patterns are alternately used as frame synchronization data, and the pattern of the received frame synchronization data is determined,
A frame synchronization method characterized in that the frame synchronization phase is determined and a frame synchronization state is determined when at least one of the frames is synchronized.