JPS61172437A - Code error detection circuit - Google Patents

Abstract

PURPOSE:To detect a code error by extracting a DC component of an output of a flip-flop inverted by '0' of an mBIP code and detecting its level change. CONSTITUTION:An mBIP code signal (a) is fed from an input terminal 6 to a NAND circuit 9, where it is inverted and its output signal (b) is fed to an AND circuit 1 together with a clock signal (c). An output signal (d) of the AND circuit 1 is fed to a clock terminal C of a flip-flop 2, where the signal is inverted and the flip-flop 2 is inverted by a '0' level of the received mBIP code signal (a) and levels at output terminals Q, Q' are restored to the initial state at a location of a parity bit. Thus, in extracting the DC component of the flip-flop 2 by low pass filters 3, 4, since the DC component level is changed at transmission error, the change is detected by a comparator 5.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to a digital high-speed transmission system in which mB bits in which one parity bit is added to m bits of information bits are used.
The present invention relates to a code error detection circuit that can detect transmission errors in IP codes with a simple configuration.

[Conventional technology]

In digital high-speed transmission systems that multiplex digital audio signals, etc., one parity bit is added to m information bits so that transmission errors can be detected without reducing transmission efficiency. An mBIP code is used in which parity bits are selected so that the number of "1"s among the (m+1) bits containing "1" is an even number.

A conventional code error detection circuit on the receiving side of the mB1P code has conventionally had the configuration shown in FIG. In the figure, 11 is an AND circuit, 12 is a flip-flop, 13.14 is a low-pass filter, 15 is a comparator, 16 is an mB1P code input terminal, 17 is a clock signal input terminal, and 18 is an error detection terminal. This is a signal output terminal. The clock signals reproduced from the mBIP code signal on the received mB1P code signal are input to input terminal 1, respectively.
6.17, the output signal C of the AND circuit 11 is applied to the clock terminal C of the flip-flop 12, and the output signal C causes the flip-flop 12 to perform an inverting operation.

The output terminal of the flip-flop 12 is connected to the data terminal, and a low-pass filter 13.14 is connected to the output terminals Q and Gll, respectively. The components are extracted. This low pass filter 13.14
The output signals f and g are applied to the comparator 15, and the output signal f
Since the output signal of the comparator 15 is inverted in response to a change in the level of , g, it can be used as a transmission error detection signal. Then, this detection signal is transferred from the output terminal 18 to a monitoring circuit or the like, and error rate measurement or the like is performed.

FIG. 4 is an explanatory diagram of the operation when using the mB1P code with m-7, and (al to (h) are the signals a of each part in FIG.
This shows an example of w h, where P in (a)
indicates a parity bit, which is selected so that the number of "1"s among the 8 bits including this parity bit P is an even number. The received mB1P code signal a is shown in (a) of Fig. 4.
In the case shown by the solid line, this signal a and the clock signal S shown in the peak) are added to the AND circuit 11, and the AND circuit 11
The output signal C is shown by the solid line in FIG. 4(C). The flip-flop 12 receives the output signal C of the AND circuit 11.
The signal d at the output terminal Q is the fourth
The result is shown in (d) of the figure.

The flip-flop 12 is “1” among (m+1) bits.
Since the number of is an even number, the parity bit P returns to the initial state. Therefore, flip-flop 12
In the initial state, if the output terminal Q is "1", the position of the parity bit P will be "1", and conversely, if the output terminal Q is "0" in the initial state, the position of the parity bit P will be "1". It becomes “0” at the position. Also, since it is common to set the probability of occurrence of "1" and "0" of m-bit information bits to 1/2, if the output terminal Q of the flip-flop 12 is set to "0" in the initial state, the parity bit Output terminal Q for each P
becomes "O" and the output terminal d becomes "1", so the output signal f of the low-pass filter 13 becomes a low level (L) as shown in (f) in FIG. 1
The output signal g of No. 4 becomes high level (H) as shown in FIG. 4(g). Since the comparator 15 compares the output signals f and g, the output signal of the comparator 15 becomes low (L) as shown in FIG. 4(h).

In addition, if the information bit "0" becomes "1" due to a transmission error as shown by the dotted line in (a) of FIG. 4, the output signal C of the AND circuit 11 also changes to (0) in FIG. As shown by the dotted line, the flip-flop 12 becomes 1", which causes the flip-flop 12 to perform an inverting operation, so the signal at the output terminal Q becomes as shown in FIG. 4(e). That is, the transmission From the position of the error bit, the polarity of the output terminal □ terminal Q of the flip-flop 12 is reversed from the normal case 1. As a result, what was "O" at the position of the parity bit P becomes "1". ”, and the output signal f of the low-pass filter 13
becomes a high level (H) as shown by the dotted line after a predetermined period, and the output signal g of the low-pass filter 14 becomes a low level (L) as shown by the dotted line. As shown by the dotted line in (h) in the figure, the high level (
H), that is, when a transmission error occurs, the error detection signal changes from low level (L) to high level (H), or from high level (I) to low level (L). Become.

It is also possible to determine the error rate by counting such level changes of the error detection signal every unit time. Therefore, it is possible to monitor digital high-speed transmission systems.

[Problems to be solved by the invention] In digital high-speed transmission systems, it is important to avoid using extra bits other than information bits as much as possible, and in the mBIP code, The value of m is selected in consideration of the characteristics of the transmission system, and is selected to be, for example, 24 or more. As mentioned above, even parity is adopted so that if there is no transmission error, the output terminals Q and Q of the flip-flop 12 will be in the initial state at the position of the parity bit.

However, if the m-bit information bits are all "0", the parity bit P will also be "O", so 0's will continue.In such a state, the clock signal on the receiving side There was a drawback that it was difficult to reproduce the data.Also, it is possible to prevent "θ" consecutively by selecting the parity bit P so that the number of "1"s among the (m+1) bits including the parity bit is an odd number. It is possible, but in that case, the output signal d of the flip-flop 12 will not be in the initial state at the position of the parity bit P, but will be alternately "l" and "0", as shown in FIG. With this configuration, transmission errors cannot be detected.

The present invention aims to improve the above-mentioned drawbacks.

[Means for solving problems]

The code error detection circuit of the present invention will be described with reference to FIG. 1. For m information bits where m is an even number,
A code error detection circuit that transmits an mBIP code in which the number of "0s" in (m+1) bits to which a parity bit is added is an even number, and detects transmission errors in this mB1P code, the mB1P code a flip-flop 2 which performs an inverting operation when "0" is set, and a low-pass filter 3.4 which extracts the DC component of the output of this flip-flop 2.
It is composed of a comparator 5 that detects a change in the output level of the low-pass filter 3.4.

[Effect]

By making m an even number, the (m+1) bits become an odd number, and by making the number of "0"s in the (m+1) bits an even number, the number of "1"s becomes an odd number. Therefore,
Even if the m-bit information bits are all 10'', the parity bit becomes "L", so it is possible to prevent continuous ``0'', and it becomes easy to reproduce the clock signal on the receiving side. Since the flip-flop operates inverted due to "0" in the (m+1) bit, the output of the flip-flop returns to its initial state at the parity bit position.The DC component of the output of this flip-flop is extracted and its level is changed. By detecting , code errors can be detected.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, l is an AND circuit, 2 is a flip-flop, 3 and 4 are low-pass filters, 5 is a comparator, 6 is an mB1P code signal input terminal, and 7 is a block diagram of an embodiment of the present invention. 8 is the input terminal for the clock signal, and 8 is the error detection signal l.
The output terminal 9 is a NAND circuit, and it is also possible to use another signal inverting circuit as the NAND circuit 9. Input terminal 6
m where the mB1P code signal power applied to is an even number
One parity bit is added to the information bit of the bit, and the parity bit is selected so that the number of 0'' in the (ffl+1) bits including this parity bit is an even number. That is, ( m+1) will be an odd number, and by making the number of “0” an even number, the number of ’13 will be an odd number. Therefore, even if the m-bit information bits are all “0”, the parity added to it The bit is “
1", it is possible to prevent consecutive "0"s.

From this mB1P code signal signal output terminal 6 to the NAND circuit 9
The output signal C is applied to the AND circuit 1 along with the clock signal C. By inverting the received mB1P code signal a, the number of "1"s in (m+1) bits becomes an even number. Therefore, when the output signal d of the AND circuit 1 is applied to the clock terminal C of the flip-flop 2 and the flip-flop 2 is inverted, this corresponds to the flip-flop 2 being inverted by "0" of the received mB1P code signal a. becomes. Since the number of "0"s in the (m+1) bits is an even number, the output terminals Q and Gl of the flip-flop 2 return to their initial states at the position of the parity bit.

FIG. 2 is an explanatory diagram of the operation when using the mB1P code with an even number of mw5. P in a) indicates a parity bit. This parity bit is
It is selected so that the number of "0"s is an even number among the information bits of m = 6 bits, and if the information bits of m = 6 bits are all "0", the parity bit P Since is selected to be "1'", the number of consecutive "0"s will never be 7 or more, making it easy to reproduce the clock signal on the receiving side.

When the received mBIP code signal a is shown in FIG. The clock signal C shown in (C) of FIG.
The output signal d of the AND circuit 1 is added to (d
). The output signal d of the AND circuit 1 becomes "1" at the timing of the clock signal C from the input terminal 7 when the received mBIP code signal a is "0", and the output signal d of the AND circuit 1 becomes "1" at the timing of the clock signal C from the input terminal 7. added to C. Since the output terminal of the flip-flop 2 is connected to the data terminal, the output signal d of the AND circuit 1 becomes "1", so that the flip-flop 2
will operate in reverse. Therefore, when the mB1P code signal a shown by the solid line in FIG. 2(a) is received, the signal e at the output terminal Q of the flip-flop 2 is
) is shown by the solid line, and if the initial state is 10'', the position of the parity bit P becomes 601.

The low-pass filters 3 and 4 are for extracting the DC component of the output of the flip-flop 2, and as described above,
Signal e of output terminal Q is “0” at the position of parity bit P
Then, the output signal f of the low-pass filter 3 becomes a low level (L) as shown by the solid line in (f) in FIG. It becomes a high level (H) as shown by the solid line. Therefore, the output signal of the comparator 5 becomes a low level (L) as shown by the solid line (hl) in FIG.

When the received mBIP code signal a changes from "1" to "0" due to a transmission error as shown by the dotted line in (a) of FIG. 2, the output signal of the NAND circuit 9 becomes the dotted line in FIG. As shown, "0" becomes "1". Therefore, the output signal d of the AND circuit 1 becomes "1" as shown by the dotted line in FIG.
The signal e at the output terminal Q is as shown by the dotted line in FIG. 2(e). That is, the output terminal Q of the flip-flop 2, which is normally "0" at the position of the parity bit P, becomes "1".

Therefore, the output signal f of the low-pass filter 3 is (
The output signal g of the low-pass filter 4 becomes a low level (L) as shown by the dotted line in (g) of FIG. The output signal becomes high level (H) as shown by the dotted line in FIG. 2(h). That is, detection of a transmission error is indicated by a signal changing from low level (L) to high level (H).

When a transmission error occurs next time, the output signal of the comparator 5 changes from high level (H) to low level (L).

〔Effect of the invention〕

As explained above, the present invention adds 1 bit of parity bit to m bits of information bits, where m is an even number, to make (m+l) bits, and "
By transmitting the mB1P code with an even number of 0's, even if the m bits of information bits are all θ's, the parity bit becomes 1, so it is possible to prevent 0's from occurring continuously. . In this way, mB that prevented continuous 0"
By inverting the flip-flop 2 with the "03" bit of the 1P code, if there is no transmission error, the output of the flip-flop 2 returns to the initial state at the parity bit position. The DC component of can be extracted by the low-pass filters 3 and 4, and since a change in the level of the DC component occurs in the case of a transmission error, it can be detected by the comparator 5.

[Brief Description of the Drawings] Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, and Fig. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a block diagram of a conventional code error detection circuit, and FIG. 4 is a diagram explaining its operation. 1 is an AND circuit, 2 is a flip-flop, 3°4 is a low-pass filter, 5 is a comparator, 6 is an input terminal for the mB1P code signal, 7 is an input terminal for a clock signal, 8 is an output terminal for an error detection signal, 9 is a NAND circuit.

Claims (1)

[Claims] “0” in (m+1) bits, where 1 bit of parity bit is added to m bits of information bits where m is an even number
An mB1P code with an even number of mB1P codes is transmitted, and the mB1P
A code error detection circuit for detecting code transmission errors, the circuit comprising:
A flip-flop that performs an inversion operation depending on the "0" bit among (m+1) bits of the mB1P code, a low-pass filter that extracts a DC component of the output of the flip-flop, and a change in the output level of the low-pass filter. A code error detection circuit comprising: a comparator for detecting a code error;