JPS61172438A - Code error detection circuit - Google Patents

Abstract

PURPOSE:To detect a code error by inverting one bit in (m+1)-bit of an mBIP code, extracting a DC component of a flip-flop inverted by a bit of level '1' and detecting a level change. CONSTITUTION:An output signal (f) of a NOR circuit G1 goes to '1' once in (m+1)-bit, that is, once in 8 bits. Since the output signal (f) is fed to an exclusive OR circuit G2, when the output signal (f) is at '1', the mBIP code signal (a) is inverted and fed to the AND circuit 1 together with a clock signal (b). Since the number of 1s in the (m+1)-bit is an even number, its output signal (h) is fed to a clock terminal C of the flip-flop 2, a signal of output terminals Q, Q' is fed to low pass filters 3, 4, and output signals (j, k) are fed to a comparator 5. Thus, a detection signal (l) representing the level change in the output signals (j, k) is outputted from an output terminal 8 and a code error is detected.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to a digital high-speed transmission system in which mB bits in which one parity bit is added to m bits of information bits are used.
This invention relates to a code error detection circuit that detects transmission errors in IP codes.

[Conventional technology]

In digital high-speed transmission systems that multiplex digital audio signals, etc., one parity bit is added to m information bits so that transmission errors can be detected without reducing transmission efficiency. An mBIP code is used in which parity bits are selected so that the number of "1"s among the (m+1) bits containing "1" is an even number.

A conventional code error detection circuit on the receiving side of this mBIP code has conventionally had the configuration shown in FIG. In the figure, 11 is an AND circuit, 12 is a flip-flop, 13.14 is a low-pass filter, 15 is a comparator, 16 is an mB1P code input terminal, 17 is a clock signal input terminal, and 18 is an error detection terminal. This is a signal output terminal. The clock signals reproduced from the mB1P code signal on the received mB1P code signal are respectively input to input terminal 1.
6.17, the output signal C of the AND circuit 11 is applied to the clock terminal C of the flip-flop 12, and the output signal C causes the flip-flop 12 to perform an inverting operation.

The output terminal of this flip-flop 12 is connected to the data terminal, and the output terminals Q, ? A low-pass filter 13.14 is connected to each of the low-pass filters 13.14, and the DC component of the output of the flip-flop 12 is extracted by the low-pass filter 13.14. The output signals f, g of this low-pass filter 13.14 are applied to a comparator 15, and the output signals f,
Since the output signal of the comparator 15 is inverted in response to a change in the level of g, it can be used as a transmission error detection signal. This detection signal is output from the output terminal 1.
8 to a monitoring circuit, etc., where error rate measurement and the like are performed.

FIG. 4 is an explanatory diagram of the operation when using the mB1P code with m=7, and (a) to (h) are the signals a of each part in FIG.
This shows an example of w h, where P in (a)
indicates a parity bit, which is selected so that the number of "1's" among the 8 bits including this parity bit P is an even number. The received mB1P code signal a is shown in Fig. 4 (a
), this signal a and the black signal shown in (b) are added to the AND circuit 11, and the output signal C of the AND circuit 11 is shown by the solid line in (0) in FIG. Become something. The flip-flop 12 is inverted by the output signal C of the AND circuit 11, and the signal d at the output terminal Q is as shown in FIG. 4(d).

The flip-flop 12 selects “1” among (m+1) bits.
Since the number of is an even number, the parity bit P returns to the initial state. Therefore, flip-flop 12
In the initial state, if the output terminal Q is "1", the position of the parity bit P will be "1", and conversely, if the output terminal Q is "0" in the initial state, the position of the parity bit P will be "1". becomes O”. Also, 61 of the m-bit information bits
'', '0'' is generally set to 1/2, so if the output terminal Q of the flip-flop 12 is initially set to ``0'', the output terminal Q for each parity bit P becomes ``0''. 0" and the output terminal d becomes "1", so the output signal f of the low-pass filter 13 becomes a low level (L) as shown in FIG.
The output signal g of is at a high level (as shown in Fig. 4).
H). Since the comparator 15 compares the output signals f and g, the output signal of the comparator 15 becomes low level (L) as shown in FIG. 4(h).

Furthermore, if the information bit of "O" becomes "1" as shown by the dotted line in (a) of FIG. 4 due to a transmission error, the output signal C of the AND circuit 11 also changes to (C) of FIG. 1" as shown by the dotted line. Since the flip-flop 12 performs an inverting operation due to the "1" shown by the dotted line, the signal at the output terminal Q becomes as shown in (el) in FIG. From the position of the bit, the polarity of the output terminal Q of the flip-flop 12 is reversed compared to the normal case.As a result, what was "0" at the position of the parity bit P becomes "1", and the low frequency After a predetermined period of time, the output signal f of the pass filter 13 becomes high level (H) as shown by the dotted line.
Since the output signal g of the low-pass filter 14 is at a low level (L) as shown by the dotted line, the output signal of the comparator 15 is also at a high level (H) as shown by the dotted line in FIG. 4(h).
In other words, when a transmission error occurs, the error detection signal changes from low level (L) to high level (H).
Or it changes from high level (H) to low level (L).

It is also possible to determine the error rate by counting such level changes of the error detection signal every unit time. Therefore, it is possible to monitor digital high-speed transmission systems.

[Problems to be solved by the invention] In digital high-speed transmission systems, extra bits other than information bits are considered to be avoided as much as possible, and in mB1P code, the transmission system The value of m is selected in consideration of characteristics and the like, and is selected to be, for example, 24 or more. As mentioned above, if there is no transmission error, there is a free 7 at the parity bit position.
Even parity is adopted so that the output terminals Q and Gl of the flip-flop 12 are in the initial state.

However, if the m information bits are all "0", the parity bit P will also be "0", so "0" will continue. In such a situation, it is difficult to reproduce the clock signal on the receiving side.

There was a drawback. Also includes parity bit (m+1)
It is conceivable to select the parity bit P so that the number of "1"s in the bit is an odd number to prevent consecutive "0"s, but in that case, the output signal d of the flip-flop 12 is It is not in the initial state at the position of bit P,
Since the signal becomes "1" and "0" alternately, the configuration shown in FIG. 3 cannot detect a transmission error.

The present invention aims to improve the above-mentioned drawbacks.

[Means for solving problems]

The code error detection circuit of the present invention will be explained with reference to FIG. 1. The code error detection circuit of the present invention will be described with reference to FIG. This is a code error detection circuit that transmits an mB1P code with
A circuit 9 that inverts 1 bit among (m+1) bits of the IP code, a flip-flop 2 that performs an inverting operation on the "1" bit of the output signal of this circuit, and a DC component of the output of this flip-flop 2 is detected. Low pass filter 3.
4, and a comparator 5 for detecting changes in the output level of the low-pass filter 3.4.

[Effect]

By setting the number of "1"s in (m+1) bits to an odd number, even if the m bits of information bits are all "0", the parity bit will be "1", so continuous "0" will be The maximum number of bits is m, making it easy to reproduce the clock signal on the receiving side.By inverting 1 bit among the (m+1) bits of this mBIP code by the circuit 9, Since the number of "1"s is an even number, transmission errors can be detected using the conventional configuration consisting of a flip-flop, a low-pass filter, and a comparator.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which 1 is an AND circuit, 2 is a flip-flop, 3.4 is a low-pass filter, 5 is a comparator, and 6 is an input terminal for mB I P code signal a. , 7 is an input terminal for the clock signal S, 8 is an output terminal for the error detection signal l, 9 is a circuit for inverting 1 bit out of (m+1) bits of the mB1P code, FFI to FF3 are flip-flops, and G1 is a NOR Circuit G2 is an exclusive-OR circuit. Flip-flop FFI in circuit 9
FF3 corresponds to the case of m-7, a clock signal is applied to the clock terminal C of the first stage flip-flop FFI, and this output terminal Q and the clock terminal C of the second stage flip-flop FF2 are connected. connected, and this output terminal Q
is connected to the clock terminal C of the third stage flip-flop, and the output terminal Q of the first and second stage flip-flops is connected to the clock terminal C of the third stage flip-flop.
and the output terminal of the third stage are connected to the NOR circuit G1, and the output signal f of the NOR circuit G1 and mB1P from the input terminal 6 are connected to the NOR circuit G1.
The code signal a is applied to the exclusive OR circuit G2, and its output signal g and the clock signal S are applied to the AND circuit 1.

FIG. 2 is an explanatory diagram of the operation when using the mB1P code with m-7, and (a) to <Il) show examples of the signals awe in each part of FIG. P in represents a parity bit. This parity bit is m-7
If there is an even number of '1's in the bit information bits, l'''
, the number of "1"s in (m+1) bits is selected to be an odd number. Therefore, when the information bits of m-depth 7 are all “0”, the parity bit P is 1
”, so consecutive ’0’s cannot be more than 8,
This facilitates clock signal reproduction on the receiving side.

When the received mB1P code signal a is shown in FIG. 2(a), the clock signal shown in FIG. Signal C is shown in Figure 2 (
C), the signal d at the output terminal Q of the flip-flop FF2 is (d), the signal e at the output terminal of the flip-flop FF3
are as shown in (e), and the output signal f of the NOR circuit Gl is "1" once in (m+1> bits, that is, once in 8 bits), as shown in (f). .

This output signal f is applied to the exclusive OR circuit G2 together with the mB1P code signal a, so when the output signal f is "1", the mB1P code signal a is inverted and the output signal g
is as shown in FIG. 2(g), and is applied to the AND circuit 1 together with the clock signal.

As shown in FIG. 2 (h), the output signal of the AND circuit 1 is an even number of "1"s among the (m+1) bits, so the output signal is applied to the clock of the flip-flop 2. In addition to the signal C, the output terminal Q, this signal is applied to the low-pass filters 3, 4, and their output signals j, k are applied to the comparator 5, thereby detecting a level change in the output signal j, A signal l is output from the output terminal 8.

As mentioned above, the output signal of AND circuit 1 is (m+1
) Since the number of "1"s in the bits is an even number, the output signal i of the flip-flop 2 at the parity bit P position returns to the initial state, and the signal i at the output terminal Q
Assuming that the initial state of is "0", the output signal j of the low-pass filter 3 becomes a low level (L) as shown at 0) in FIG. 2, and the output signal of the low-pass filter 4 has a 2
The output signal 1 of the comparator 5 becomes a high level (H) as shown in (g) of the figure. Therefore, the output signal l of the comparator 5 becomes a low level (L) as shown in (A') of FIG.

When the received mBIP code signal a becomes "1" due to a transmission error as shown by the dotted line in (a) of Figure 2, the output signal of AND circuit 1 becomes "1" as shown by the dotted line in (h). 61'' as shown in FIG. Since the output signal i that was ``1'' becomes 1, the output signal j of the low-pass filter 3 becomes a high level (H) as shown by the dotted line (''), and the output signal of the low-pass filter 4 becomes is low level (L) as shown by the dotted line in (k)
becomes. Therefore, the output signal l of the comparator 5 becomes high level (H) as shown by the dotted line in (1), and this level change of the output signal E indicates the detection of a transmission error.

The circuit 9 determines an arbitrary position among (m+1) bits, and
Any configuration that inverts the bits is sufficient, and various configurations that count the clock signal can be adopted.

〔Effect of the invention〕

As explained above, the present invention adds one pinto parity bit to m information bits (m+1
) By transmitting the mB1P code in which the number of 11s in the bits is an odd number, even if the information bits are “θ′” consecutive, the parity bit is set to “1” to prevent “0” consecutive. be able to. This has the advantage that the clock signal can be easily reproduced on the receiving side. Then, by inverting 1 bit among (m+1) bits by circuit 9, the number of 11''s among (m+1) bits becomes an even number, so the output signal of flip-flop 2 is initialized at the position of parity bit P. Therefore, the DC component of the output of the flip-flop 2 can be extracted by the low-pass filter 3.4, and the change in the level of this DC component is detected by the comparator 5 to eliminate transmission errors. This can be used as a detection signal.

[Brief explanation of drawings]

Figure 1 is a block diagram of an embodiment of the present invention, Figure 2 is an m-7
FIG. 3 is a block diagram of a conventional code error detection circuit, and FIG. 4 is a diagram explaining its operation. 1 is an AND circuit, 2 is a flip-flop, 3°4 is a low-pass filter, 5 is a comparator, 6 is an input terminal for the mB1P code signal, 7 is an input terminal for a clock signal, 8 is an output terminal for an error detection signal, 9 is a circuit for inverting 1 bit among (m+1) bits, FF1 to FF3 are flip-flops,
G1 is a NOR circuit, and G2 is an exclusive OR circuit.

Claims (1)

[Claims] Code error detection that transmits an mB1P code with an odd number of "1"s among (m+1) bits in which 1 parity bit is added to m information bits, and detects transmission errors in the mB1P code. A circuit that inverts one bit out of (m+1) bits of the mB1P code, a flip-flop that performs an inversion operation on a "1" bit of an output signal of the circuit, and a DC component of the output of the flip-flop. 1. A code error detection circuit comprising: a low-pass filter that detects a change in the output level of the low-pass filter; and a comparator that detects a change in the output level of the low-pass filter.