JPH056808B2

JPH056808B2 -

Info

Publication number: JPH056808B2
Application number: JP20369285A
Authority: JP
Inventors: Yasuhiro Fujinobe
Original assignee: Nippon Electric Co Ltd
Current assignee: NEC Corp
Priority date: 1985-09-13
Filing date: 1985-09-13
Publication date: 1993-01-27
Also published as: JPS6264131A

Description

[Detailed description of the invention]

（産業上の利用分野）本発明はデイジタル伝送装置等で伝送路エラー
を監視するため受信部に設けられるエラー検出回
路、さらに詳しく云えばmBnB符号の符号則誤り
によるエラー検出回路に関する。（従来の技術） mBnB符号とは例えば5B6B符号の場合、シリ
アル信号を５ビツト毎のパラレル信号に変換し、
これを“０”または“１”が連続する符号列にな
らないようにして“１”と“０”を平均化して６
ビツトで表現する符号のことをいう。通常、5B6B符号の符号化はROMが用いられ、
入力符号に対応する出力符号のパターンをROM
内に書込むことにより行なわれる。また、復号化
はやはりROMが用いられ、上記とは反対のパタ
ーンがROM内に書込まれている。この書込みの
際、デイスパリテイ（“０”を−0.5、“１”を＋
0.5としたときの符号内の積分値、例えば、６ビ
ツトで011011であれば、デイスパリテイは“＋
１”である）の状態もROM内に書込み、デイス
パリテイの状態によつて２モード（デイスパリテ
イが“＋１”と“０”モードと、“−１”と“０”
のモードの２モード）のいずれかを選ぶように制
御して符号化を行なう。復号部でもデイスパリテイの状態をROMに書
込でおき、その変化の状態から符号則を違反した
ものをエラーとしてカウントする。従来、この種のエラー検出回路として9B10B
符号の場合があるが、9B10B符号の場合は３モ
ードによる積分値制御であり、5B6B符号等の２
モード制御方式についてはエラー検出回路は存在
しない。（発明の目的）本発明の目的は5B6B符号等のデイスパリテイ
の状態を２ビツトで表わし、その２ビツトの情報
からエラーを検出することができる回路を提供す
ることにある。（問題点を解決するための手段）前記目的を達成するために本発明によるエラー
検出回路はmBnB符号のデイスパリテイが“＋
１”の状態、“−１”の状態、“０”の状態および
未使用符号の状態の４状態を２ビツトで表わした
信号を入力とし、未使用の状態を示す信号が入力
したとき、それを検出する未使用符号検出回路
と、前記“＋１”の状態または“−１”の状態を
示す信号が入力したとき、それを１タイムスロツ
ト遅延させ、その後に、“０”の状態を示す信号
が入力したとき、前記“＋１”の状態または“−
１”の状態を示す信号を保持する第１メモリ回路
と、前記未使用符号検出回路の出力信号のうち、
未使用の状態を示す信号以外の信号を１タイムス
ロツト遅延させる第２メモリ回路と、第１メモリ
回路出力のうち、１タイムスロツト遅延させられ
た“＋１”の状態を示す信号、第２メモリ回路出
力および前記２ビツトで表わした入力の一方を入
力とし、１タイムスロツト前が未使用状態を示す
信号以外であり、かつ途中に“０”の状態を示す
信号を挟んだ場合も含み、“＋１”の状態を示す
信号が連続して入力していることを示す信号を出
力する第1AND回路と、第１メモリ回路出力のう
ち、１タイムスロツト遅延させられた“−１”の
状態を示す信号、第２メモリ回路出力および前記
２ビツトで表わした入力の他の一方を入力とし、
１タイムスロツト前が未使用状態を示す信号以外
であり、かつ途中に“０”の状態を示す信号を挟
んだ場合も含み、“−１”の状態を示す信号が連
続して入力していることを示す信号を出力する第
2AND回路と、前記未使用符号検出回路出力の未
使用の状態を示す信号、第1AND回路出力および
第2AND回路出力を入力とし、エラーパルスを出
力するOR回路とから構成してある。（実施例）以下、図面を参照して本発明をさらに詳しく説
明する。第１図は本発明によるエラー検出回路の
実施例を示す回路図で、5B6B符号における２モ
ードによる制御方式に対するエラー検出回路であ
る。本回路は未使用符号検出回路１、第１のメモリ
回路２、第２のメモリ回路３、第１のAND回路
４、第２のAND回路５およびOR回路６により構
成される。本実施例ではデイスパリテイ“１”の状態を
“01”の２ビツトに、デイスパリテイ“−１”の
状態を“10”の２ビツトに、デイスパリテイ
“０”の状態を“11”の２ビツトに、および未使
用符号の状態を“00”の２ビツトにそれぞれ割り
当てている。本発明におけるエラー検出回路は次の条件を満
足するように構成されている。 (Industrial Application Field) The present invention relates to an error detection circuit provided in a receiving section in a digital transmission device or the like to monitor transmission path errors, and more specifically, to an error detection circuit due to a code rule error in an mBnB code. (Prior art) What is an mBnB code? For example, in the case of a 5B6B code, a serial signal is converted into a parallel signal of every 5 bits,
This is made so that "0" or "1" are not consecutive code strings, and "1" and "0" are averaged.
A code expressed in bits. Normally, ROM is used to encode the 5B6B code,
ROM the output code pattern corresponding to the input code
This is done by writing inside. Also, ROM is still used for decoding, and a pattern opposite to the above is written in the ROM. When writing this, disparity (“0” is -0.5, “1” is +
If the integral value in the sign is 0.5, for example, 011011 with 6 bits, the disparity is “+
The state of "1") is also written in the ROM, and depending on the disparity state, there are two modes (disparity is "+1" and "0" mode, and "-1" and "0" mode).
Encoding is performed by controlling to select one of the following two modes. The decoding unit also writes the state of disparity in the ROM, and from the state of change, violations of the coding rules are counted as errors. Conventionally, 9B10B was used as this type of error detection circuit.
In the case of 9B10B code, integral value control is performed in 3 modes, and in 2 modes such as 5B6B code, etc.
There is no error detection circuit for the mode control method. (Object of the Invention) An object of the present invention is to provide a circuit that can express the disparity state of a 5B6B code or the like with 2 bits and detect errors from the 2-bit information. (Means for Solving the Problems) In order to achieve the above object, the error detection circuit according to the present invention has a disparity of mBnB code of “+”.
The input signal is a 2-bit signal representing the four states of "1" state, "-1" state, "0" state, and the state of an unused code, and when a signal indicating an unused state is input, When the signal indicating the "+1" state or "-1" state is input, it is delayed by one time slot, and then a signal indicating the "0" state is input. is input, the state of “+1” or “-
1”, and the output signal of the unused code detection circuit,
a second memory circuit that delays signals other than signals indicating an unused state by one time slot; a signal indicating a “+1” state that is delayed by one time slot among the outputs of the first memory circuit; a second memory circuit; If one of the output and the input represented by the two bits is used as an input, and the signal one time slot before is a signal other than the unused state, and there is a signal indicating the "0" state in the middle, it will be "+1". A first AND circuit that outputs a signal indicating that a signal indicating a state of "" is input continuously, and a signal indicating a state of "-1" delayed by one time slot among the outputs of the first memory circuit. , the second memory circuit output and the other one of the inputs represented by the two bits are input;
A signal indicating a “-1” state is input continuously, including a case where a signal indicating a state of “0” is inserted in the middle, and a signal indicating a state of “0” is not used one time slot before. outputs a signal indicating that
It is composed of a 2AND circuit, a signal indicating the unused state of the output of the unused code detection circuit, an OR circuit which receives as input the output of the first AND circuit and the output of the second AND circuit, and outputs an error pulse. (Example) Hereinafter, the present invention will be described in more detail with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of an error detection circuit according to the present invention, and is an error detection circuit for a two-mode control system in a 5B6B code. This circuit is composed of an unused code detection circuit 1, a first memory circuit 2, a second memory circuit 3, a first AND circuit 4, a second AND circuit 5, and an OR circuit 6. In this embodiment, the state of disparity "1" is set to 2 bits of "01", the state of disparity "-1" is set to 2 bits of "10", the state of disparity "0" is set to 2 bits of "11", and the state of disparity "0" is set to 2 bits of "11". and the status of unused codes are assigned to two bits of "00". The error detection circuit according to the present invention is configured to satisfy the following conditions.

【表】＞
10[Table] ＞
Ten

Claims

[Claims] A signal in which the disparity of a 1 mBnB code represents four states of "+1" state, "-1" state, "0" state, and unused code state in 2 bits is input, When a signal indicating an unused state is input, an unused code detection circuit detects it; and when a signal indicating the "+1" state or "-1" state is input, it is delayed by one time slot. Then, when a signal indicating the "0" state is input, the "+1" state or the "--" state is input.
a first memory circuit that holds a signal indicating a state of "1", and a second memory circuit that delays signals other than the signal indicating an unused state among the output signals of the unused code detection circuit by one time slot; A signal indicating the “+1” state delayed by one time slot among the first memory circuit outputs;
One of the memory circuit output and the input represented by the above two bits is used as an input, and one time slot before is a signal other than the signal indicating an unused state, and there is a "0" in the middle.
“+1” including the case where a signal indicating the status of
a first AND circuit that outputs a signal indicating that signals indicating the state of the memory are input continuously; a signal indicating the state of "-1" delayed by one time slot among the outputs of the first memory circuit; Second
The other one of the memory circuit output and the input represented by the above two bits is used as an input, and one time slot before is a signal other than a signal indicating an unused state, and a signal indicating a "0" state is sandwiched in between. Contains “-
a second AND circuit that outputs a signal indicating that a signal indicating a state of "1" is continuously input; a signal indicating an unused state of the output of the unused code detection circuit; an output of the first AND circuit; and a second AND circuit. An error detection circuit comprising: an OR circuit that receives a circuit output as an input and outputs an error pulse;