JPS61129947A - Code error detection circuit - Google Patents

Abstract

PURPOSE:To detect a code error with a simple circuit by generating a pulse from a storage means when an input signal has an error in the code rules in the synchronization establishing state. CONSTITUTION:A signal (a) comprising an mB1C code is inputted to an EX-OR circuit 2 together with a signal (b) while being delayed by 2 bits at a delay circuit 1, the dissidence of them is detected to generate a signal (c). This is a signal outputting '1' at each (m+1)-th bit when no code error exists. A frequency divider 3 applies 1/(m+1) frequency division to a clock (d) having a bit period to produce a signal (e). A flip=flop 4 receives the signal (c) at the data input D and the signal (e) at the clock input C and produces an output signal (f) of '1' level continuously when the synchronization is established and no code error exists. If any code error exists, however, one pulse of '0' level is generated and it is used as an error signal to detect the error.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a circuit for detecting an error in a transmission code.
In particular, it relates to a code error detection circuit for detecting a code error υ in the mB1c code.

[Conventional technology]

When monitoring the transmission quality of a transmission path or the operating status of a terminal station or repeater, it is necessary to

Monitoring is performed by detecting an error 9 in the transmission code.

Conventionally, this kind of transmission code error detection was done by inserting a parity bit into the transmission code for each frame at the transmitting end station, synchronizing the frame at the receiving end station, and observing whether the parity pits were correct. A so-called parity check method for detecting code errors is often used.

[Problem that the invention seeks to solve]

However, when using the parity check method,
The circuit scale on the transmitting and receiving sides increases. In addition, when a repeater is included in the transmission path, 7-frame synchronization is generally not established in the repeater in order to prevent the cost of increasing the circuit size, so parity checks cannot be performed on the repeater. Even if 9 occurs, it cannot be detected separately from other locations.

The present invention is an attempt to solve the problems of the prior art, and is capable of detecting code errors (code errors) with a simple circuit when used on mB1cB1 as a transmission code, and therefore can also detect errors in repeaters. The present invention aims to provide a simple code error detection circuit.

[Means for solving problems]

The code error detection circuit of the present invention detects a mismatch between an input signal and a signal whose phase is changed by the bit difference between a specific bit of each word and an additional bit in a complementary code relationship with the input signal. At the same time, the frequency dividing means generates an output divided by the bit period clock i (m+1) (m is word length), and according to the frequency divided output, the mismatch detection output is read into the storage means and the next divided When the averaged output of this storage means is below a certain level, the clock input fc! It is designed to stop.

[For production]

In the code error detection circuit of the present invention, when there is an error in the code rule in the input signal in the synchronization established state, a pulse output is generated from the storage means.
Detection can be performed.

〔Example〕

The m81c code is often used for digital signal transmission through optical fibers. This is because in the mBIC code, the same code of '1' or '0' does not continue for a long period of time, so timing extraction and DC regeneration in the optical-to-electric conversion section are easy. □ Figure 2 is An example of the above configuration of mB1cB1 is shown. The mB1c encoding system divides data into bits f m (m is a natural number), and adds a complementary code (f 1 bit) of 1 bit of a specific order among them. In FIG. 2, the C bit indicates such an added bit, and in the same figure, the C bit is the complementary code of bit B two bits before the C bit.

FIG. 1 shows the configuration of an embodiment of the code error 9 detection circuit of the present invention, in which 1 is a delay circuit, 2 is an exclusive OR (EX-OR) circuit, 3 is a frequency dividing circuit, 4 is flip 70
5 is a low-frequency P wave generator, 6 is a comparator, 7 is a timer, 8 is a NAND circuit, and 9 is an AND circuit.

Moreover, FIG. 3 shows the signals of each part in the circuit of FIG.
is the input mB1cB1 formula power, b is the output signal of delay circuit 1,
C is the output signal of the EX-OR circuit 2, d is the clock, e is the output signal of the 1 frequency divider 3, f is the output signal of the FF 4, g is the output signal of the low-frequency ν wave generator 5, h is the comparator 6 1 is the output signal of timer 7, j is the output signal of NAND circuit 8, k
is the output signal of the AND circuit 9.

As shown in FIG. 2, the input signal a consisting of mB1cB1 is added with the complementary code of the bit two bits before as the C bit. The signal a is input to the EX-OR circuit 2 together with the signal delayed by 2 bits in the delay circuit 1, and a mismatch is detected to generate the signal ct-. ) 1 per bit
" is the output signal. In FIG. 3, this state is shown by a thick line. On the other hand, the frequency divider 3 divides the bit period clock d by (m+1) to generate a signal e.

FF4 continuously generates an output signal f of 1'' when there is no code error in a state where the cycle is established by adding the signal C to the data input and the clock input C to the signal ef, but when there is no code error. If this occurs, one O'' pulse is generated as shown by the dotted line in FIG. 3, and this can be used as an error signal to allow for erroneous spending.

When the phase of the signal e frequency-divided by the frequency divider 3 does not match the 11" position of every (m+x) bit of the signal C of the EX-OR circuit 2, the output signal f of the FF4 is % random signal.Therefore, the level of the signal g smoothed through the signal fi low-frequency modulator is lower than when the phases match.

Comparator 6 compares the level of signal g with reference voltage Vref, and outputs signal h' which becomes high level only when the level is higher than a certain level.
l arise. On the other hand, the timer 7 generates a signal lt- which is independent of the period of the clock d and consists of pulses having a period longer than this. When synchronization is not established and the output signal of the comparator 6 is low level, the NAND circuit 8 generates a signal jt- which becomes low level for each pulse of the timer 7, and the AND circuit 9 outputs the signal jt-.
Each time the clock signal a6t becomes low level, a pulse of the clock signal a6t is dropped to generate a signal k, and the frequency divider 3 generates a frequency-divided output signal e. By repeating such operations, the phase of the output signal e of the frequency divider 3 is gradually delayed until it matches the phase of the signal C, and word synchronization is established. In this state, the output signal of the comparator 6 is at a high level as described above (even if there is a code error, the level of the signal is not affected as long as the error rate is small), so the signal i of the timer 7 is is blocked in the NAND circuit 8, so once word synchronization is achieved, this state will be maintained thereafter.

In this manner, in the circuit shown in FIG. 1, the false 9 rate can be detected using the error signal pulse generated from the FF 4 in the synchronization established state.

〔Effect of the invention〕

As explained above, according to the code error detection circuit of the present invention, when transmission is performed using an mBIC code or a code having a similar structure, the circuit of the present invention described above can perform word synchronization and monitor code rules. Code error 9 can be detected by In the circuit of the present invention, mB1c
Since only the C bit in the code and the information bits in the complementary code relationship are observed, the probability of detecting an error pulse is 27m+1. Therefore, the true bit error rate P
When t is the observed error rate t''Po, the following equation is obtained.

Since the code error detection circuit of the present invention can detect code errors with a simple circuit, it is particularly useful when applied to cases where patent errors are monitored even in repeaters.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the code error detection circuit of the present invention, FIG. 2 is a diagram showing an example of the configuration of an mB1c code, and FIG. 3 is a time chart showing various signals in the circuit of FIG. 1. be. 1...Delay circuit, 2...Exclusive OR (EX-OR)
) circuit, 3... Frequency divider circuit, 4... Flip-flop (FF), 5... Low-frequency P wave device, 6... Comparator, 7...
...Timer, 8...NAND circuit, 9...AND circuit.

Claims (1)

[Claims] In a circuit that detects errors in a code in which bits of a complementary code of a specific bit of each word are added to each word, an input signal is combined with a signal whose phase is changed by the bit difference between the specific bit and the additional bit. a discrepancy detection means for detecting a discrepancy between the two and generating an output; a frequency division means for generating an output by dividing a clock having a bit period by (m+1) (m is a word length); storage means that reads the output of the mismatch detection means and holds it until the next output of the frequency division means is generated; and when the output obtained by averaging the outputs of the storage means is below a certain level, a pulse with a period longer than the bit period is generated. A code error detection circuit comprising means for inhibiting clock input to the frequency dividing means, and detecting an error in an input signal using an output pulse when synchronization of the storage means is established.