JPS62274948A - frame synchronizer - Google Patents

Abstract

PURPOSE:To obtain the frame synchronizing signal of sharp autocorrelation with a short signal by using a signal having a pattern where autocorrelation is sharp with the optional number of bits in a data signal sequence to which signal level change and non-change points of the signal, which has a run length to satisfy modulation rules of data, are expressed with codes different from each other. CONSTITUTION:After a modulating circuit 11 subjects a data signal a1 to MILLER<2> modulation to output a level change signal c1, a frame synchronizing signal generating circuit 12 is controlled by a control circuit 15 to generate and output a frame synchronizing signal (s) to a flip flop 14 through an OR circuit 13. When the generation of the frame synchronizing signal (s) is terminated, the modulating circuit 11 starts the MILLHR<2> modulation of a data signal a2 by the control of the control circuit 15 to output a level change signal c2.to the flip flop 14. Since the flip flop 14 ohanges the output level for each input pulse ('1'. of the level change signal (c)), a recording signal (d) is outputted from the flip flop 14 when the level change signal (c) into which the data part and the frame synchronizing signal are synthesized is inputted to the flip flop 14.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] The present invention relates to a frame synchronization method for modulating and demodulating digital data consisting of a plurality of data frames separated by frame synchronization signals. satisfies the modulation rules used for the frame, and the change point of the signal level is 1″,
By using a signal with a pattern in which the autocorrelation becomes sharp when the unchanged point is expressed as "0" as the frame synchronization signal,
This method uses a frame synchronization signal with a short signal length and sharp autocorrelation to reduce data redundancy.

[Industrial application field]

The present invention relates to a frame synchronization method in recording/reproducing, information processing, code transmission, etc. by high-density recording devices such as optical disk memories and magneto-optical memories.

[Conventional technology]

The conventional frame synchronization signal pattern follows the modulation rule used for the data part, satisfies the same rule as the modulated data pattern, and has a sharp autocorrelation.

For example, the modulation method used for the data part is MI LLE.
For R' modulation, the synchronization pattern run length is IT
~3T (where T is the minimum run length of the recording signal),
In other words, the bit rate after modulation is 2t~61 (however,
t is 1 bit length), and a pattern with sharp autocorrelation was selected in the recorded signal.

[Problem that the invention seeks to solve]

The autocorrelation of a signal such as a synchronization signal becomes sharper when "0" and "'1" alternate frequently, so for example, when the minimum run length is 2t as shown above, the minimum run length is t. The autocorrelation becomes weaker than that of

[Means for solving problems]

The present invention provides a signal having a run length that satisfies a data modulation rule, with a signal level change point and a no-change point having different signs.
For example, in a data signal series expressed as "1°,""0", by using a signal with a pattern in which the autocorrelation becomes sharper with an arbitrary number of vias, it is possible to obtain a frame synchronization signal with sharper autocorrelation with a shorter signal than before. I made it.

[For production]

FIG. 1 is a diagram showing the principle of the present invention. When original data a is subjected to MILLER2 modulation, for example, recording data signals S, b2 as shown in the figure are obtained.

If we consider a signal in which the level change point of this recording data signal is set to "1" and the level unchanged point is set to "O", a signal sequence CI+C2 as shown in Figure C is obtained.

These signal series cl, c2 are the recording data signals S,...
There is a change in sign within the same level period that continues in b2, and u1'' is not continuous, and there is always a "0" between "1" and "1".

In this way, when the minimum run length of the recording data signals bI, b2 is 2 or more, the signal series c2 has a smaller minimum run length than the recording data signals bI, b2, and the level changes more frequently.

〔Example〕

FIG. 2 is a diagram showing the data modulation process of the embodiment.
As in the figure, a is the original data signal before modulation, b is the recorded data signal obtained by MILLER2 modulation of the data signal a,
C is a signal series in which the signal level change point of this recording data signal is indicated by "l" (hereinafter referred to as a level change signal), and d is a recording signal to the optical disk memory, which is the same as the recording data signal above. satisfies the modulation rule of the above-mentioned "MILLER" modulation.

"0100101" is added to the level change signal C as a frame synchronization signal S.

The minimum run length of the signal with MILLER2 modulation is 2
Since the maximum run length is 6t at t, the level change signals c, , c2 always include one or more and five or less 0's between "1" and "0" at the beginning. So,
The frame synchronization signal “0100101”S is
When changed to recording signal d, it becomes MILL like the data part.
satisfies the modulation rules for ER'' modulation.

FIG. 3 is a block diagram of a signal generating circuit, which generates a recording signal d from the data signal a.

The modulation circuit 11 modulates the data signal a with "MILLER",
A level change signal C is generated based on the modulated recording data signal S, and this level change signal C is input to a flip-flop 14 via an OR circuit 13.

When the modulation circuit 11 modulates the data signal al and outputs the level change signal C3, the frame synchronization signal generation circuit 12 generates the frame synchronization signal S under the control of the control circuit 15. It is output to the flip-flop 14 via the OR circuit 13.

When the frame synchronization signal S has been generated, the modulation circuit 11 starts modulating the data signal a2 again under the control of the control circuit 15, and transfers the level change signal c2 to the flip-flop 1.
Output to 4.

Since the flip-flop 14 changes the output level for each input pulse (“1” of the level change signal C), the level change signal C, which is a combination of the data part and the frame synchronization signal, is output to the flip-flop I under the control of the control circuit 15.
4, the recording signal d is output from the flip-flop 14.

FIG. 4 is a block diagram of the frame synchronization detection circuit, and c/ and d/ in the figure are level change signals C1 of the signal generation circuit.
The signal after reproduction of the recording signal d is shown.

The reproduced signal d' read from the optical disk memory is E
At the same time, it is input to one input terminal of the XOR circuit 22, delayed by one pin in the delay circuit 21, and input to the other input terminal of the EXOR circuit, and the level change signal C' is outputted from the EXOR circuit 22. It is input to the matched filter 23.

Q(τ) = (241) is suitable as a prediction function for the synchronization signal “010010” in this embodiment, and this prediction function Q(τ) is adjusted according to the level change signal C′ input manually to the matched filter 23. The prediction function generation circuit 24 outputs the signal to the addition circuit 25 at a predicted time based on a control signal or a frame synchronization detection signal output from a comparison circuit 26 (to be described later). On the other hand, the matched filter 23 counts the number of matching bits between the manually input level change signal C' and the frame synchronization signal pattern r010010J, and outputs the counted value to the sequential addition circuit 25.

The addition circuit 25 adds the value of each digit of the prediction function Q(τ) sequentially inputted from the prediction function generation circuit 24 and the count value of the number of matching bits inputted sequentially, and compares the sums. Output to circuit 26.

The comparison circuit 26 compares the value output from the addition circuit 25 with a set value 7 in the case of this embodiment, and compares the value output from the addition circuit 25 with the set value 7.
When the output value reaches the set value 7, a frame synchronization detection signal is output.

By using the above prediction function Q<t), it is possible to detect up to 3-bit errors with 3 bits in the detection window.

In the above embodiments, the frame synchronization signal is MIL L
In order to satisfy the E R2 modulation rule, the first bit had to be "0".Next, we will explain an example of a frame synchronization signal in which the first bit is "1" and uses a pattern with sharp autocorrelation. .

FIG. 5 is a diagram showing a data modulation process similar to that in FIG. 2, and the data part is the same as in FIG. 2 and the first embodiment. S
"1010010" is added.

The data part immediately before the frame synchronization signal is modulated with 01, so if the beginning of the frame synchronization signal is "↑", two consecutive 1" bits will be generated, and this will be converted into a recording signal. Since the modulation rule of M I L L E R2 modulation is no longer satisfied, the frame synchronization signal S "101
Signal “010101001” with “010” or “000” added as a combination bit before “0010”
0'' or 0001010010'' (hereinafter referred to as a combined frame synchronization signal) is used between the level change signals C1 and C2.

This way the combined bit “010” or “OOO”
By adding , a pattern starting with "1" can be used as a frame synchronization signal while satisfying the modulation rules of MILLER2 modulation.

When selecting “010” and “000” as the above combination bits, if the number of “1”s in the frame synchronization signal is odd,
The combination focus is selected so that the sum of the number of "1"s in the data part and the combination bit in one frame of the level change signal before inserting the frame synchronization signal is an even number, and the number of "1"s in the frame synchronization signal is an even number. In this case, the combination bits are selected so that the sum of the number of "I"s in the data section and the combination bits in one frame is an odd number.

In other words, in the case of this embodiment, the frame synchronization signal S''10
Since the number of 1's in ``10010'' is an odd number, if the number of ``l'' in the data part in one frame of the level change signal c1 before inserting the frame synchronization signal is an even number, the combined bit u000'' is selected; If there is, the combination bit “010”
"Select frame synchronization signal S"1010010
Add to ″.

By doing so, the phase of the frame synchronization signal is inverted every frame, so that the DC component of the frame periodic signal, which causes disturbance to tracking, etc., is canceled out.

Note that the data part is DC-free due to the nature of MTLLER2 modulation, so there is no need to consider DC drift.

FIG. 5 is a block diagram of a signal generation circuit when combined bits are used.

In the figure, a modulation circuit 31, a frame synchronization signal generation circuit 32,
The flip-flop 34 operates in the same manner as in the first embodiment, and the counter 37 is connected to the modulation circuit 31 via the OR circuit 33.
The number of "1"s in the level change signal C6 outputted from the circuit is counted, and a signal indicating whether the counted value is an odd number or an even number is outputted to the combined bit generation circuit 36, and the combined bit generation circuit 36 Depending on the signal from the counter 37, "000" or "010" is selected as described above and a combined bit is output.

The OR circuit 33 includes data parts CI and C2 of the level change signal output from the modulation circuit 31, the combination bit output from the combination bit generation circuit 36, and the frame synchronization signal generation circuit 32.
The frame synchronization signal S outputted by the synthesizer and the frame synchronization signal S are synthesized and output. Further, the control circuit 35 controls each of the circuits described above to output each signal in a time-division manner.

With the second embodiment, it is possible to completely reduce the DC drift to zero just by counting the number of "1"s in the frame, and it is possible to make a pattern with a sharp autocorrelation with the leading bit "1" MILL.
It can be used as a frame synchronization signal that satisfies ER2 modulation.

The second embodiment is particularly effective when the beginning of the frame synchronization signal pattern is "1", but when the beginning is "0", the combination bit is set to 00" or 0.
Needless to say, it may be set to 1'' or the like.

Further, frame synchronization detection is performed in the same manner as in the first embodiment, so a description thereof will be omitted.

〔effect〕

According to the present invention, a signal having a pattern in which the autocorrelation becomes sharp in a signal sequence in which the signal level change points and unchanged points of a signal having a run length that satisfies the modulation rules of the data part are expressed with different codes is used as a frame synchronization signal. By using this, frame synchronization detection can be performed using a short frame synchronization signal with sharp autocorrelation.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the principle of the present invention, Fig. 2 is a diagram showing the data modulation process of the first embodiment, Fig. 3 is a block diagram of the signal generation circuit of the first embodiment, and Fig. 4 5 is a diagram showing the data modulation process of the second embodiment, and FIG. 6 is a block diagram of the signal generation circuit of the second embodiment.

Claims (2)

[Claims] (1) In a frame synchronization method when modulating and demodulating digital data consisting of multiple data frames separated by frame synchronization signals, the modulation rules used for data frames are satisfied, and the points of change and point of no change in signal level are A frame synchronization method characterized by using a frame synchronization signal with a pattern in which the autocorrelation becomes sharp when expressed with different codes. (2) A combination bit satisfying the modulation rule and selected according to the number of signal level change points of data in each frame is added to the front of the frame synchronization signal. Frame synchronization method.