KR100226022B1 - A system for showing an action completion state of equalizer - Google Patents

Abstract

The present invention relates to an equalizer operation completion state display system for indicating an operation completion state of a line equalizer for compensating for a signal from a transmitting end attenuated on a data transmission line. Means for outputting a peak signal from the first and second reference voltage signals (Vref1, Vref2) and outputting a peak detection signal; and receiving a data rate information and a first clock signal from an external source; Means for outputting a second clock signal, and means for receiving and storing the peak detection signal, and outputting the peak detection signal in response to the second clock signal. By such a system, it is possible to confirm the operation completion state and signal disconnection state of the line equalizer, thereby preventing data errors due to detecting data during the operation of the line equalizer or in the signal disconnection state.

Description

Equalizer operation completion status display system

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an equalizer, and more particularly, to an operation completion state display system of an equalizer for displaying an operation completion state of a line equalizer for compensating a signal from attenuated transmitters on a data transmission line. It is about.

The line equalizer compensates for the attenuated signal on the data transmission line and always maintains a constant level.

Data transmitted from the transmitting end is attenuated while passing through the line, and the amount varies depending on the distance of the line. Therefore, the attenuated received signal is constantly recovered at the receiving end according to the gain of the equalizer, and the data is extracted using the recovered signal.

However, if the data extraction process is performed while the equalizer compensates for the attenuation of the received signal or when there is no received signal, an error occurs in the extracted data.

Thus, it is necessary to inform that the equalizer compensates for all attenuation of the received signal and also states that the signal has been raised, i.e. compensated, for a certain level.

Particularly, in case of coding only without modulation or demodulation in digital communication, when 0 data is transmitted above a certain level in the system, it is in the same state as no transmission at the transmitting end. There is a need for a separate device that can be distinguished.

The present invention proposed to solve the above-described problem, to provide an operation completion state display system of the equalizer for displaying the operation completion state of the line equalizer for compensating the signal from the attenuated transmitting end on the data transmission line Its purpose is to.

Another object of the present invention is to provide an operation completion state display system of an equalizer capable of actively changing the final operation display state of a line equalizer according to a data pattern.

1 is a view showing in detail the configuration of the equalizer operation completion state display system according to an embodiment of the present invention;

2 is a view for explaining a peak detection method of the equalizer operation completion state display system shown in FIG.

3 is an operation timing diagram for explaining the operation of the equalizer operation completion state display system shown in FIG.

* Explanation of symbols on the main parts of the drawing *

110, 120: comparator 310: divider

150, 330, 350, 380: Inverter 200, 320, 370: De-flip flop

160, 340, 360, 390: NAND Gate

(Configuration)

According to the present invention for achieving the above object, the equalizer operation completion state display system, the peak signal is received from the outside, and compared with the first and second reference voltage signals (Vref1, Vref2) to detect the peak Means for outputting a signal; Means for receiving data rate information and a first clock signal from an external source and outputting a peak reset signal and a second clock signal; And a means for receiving and storing the peak detection signal and outputting the peak detection signal in response to the second clock signal.

In a preferred embodiment of this system, the peak signal comparing means comprises: first comparing means for comparing an externally input peak signal with a first reference voltage signal; Second comparing means for comparing the peak signal input from the outside with the second reference voltage signal and outputting the second signal; A first inverter for inverting and outputting the output of the first comparing means; The first input terminal includes a first NAND gate that receives an output of the first inverter and the other input terminal receives an output of the second comparing means.

In a preferred embodiment of this system, the first comparing means is a comparator where the non-inverting terminal receives the peak signal and the inverting terminal receives the first reference voltage signal Vref1.

In a preferred embodiment of this system, the second comparing means is a comparator in which the non-inverting terminal receives the peak signal and the inverting terminal receives the second reference voltage signal Vref2.

In a preferred embodiment of this system, the peak reset signal and the second clock signal output means include: means for receiving a first clock signal from an external source and dividing it in response to externally input data rate information; A first flip-flop which receives the output of the division means as data and outputs a previous input signal in response to the first clock signal; A second flip flop that receives the output of the first flip flop as data and outputs a previous input signal in response to the first clock signal; A second inverter for inverting and outputting the first clock signal; A third inverter for inverting and outputting the output of the first flip flop; A fourth inverter for inverting and outputting the output of the second flip flop; A second NAND gate having one input terminal receiving an output of the dispensing means and the other input terminal receiving an output of the third inverter; A third NAND gate on which one input terminal receives an output of the first flip flop and another input terminal receives an output of the fourth inverter and outputs a peak reset signal; One input terminal includes an output of the second inverter, and the other input terminal includes a fourth NAND gate that receives an output of the second NAND gate and outputs a second clock signal.

In a preferred embodiment of this system, the first and second flip flops are de-flip flops.

In a preferred embodiment of the system, the means for outputting the peak detection signal in response to the second clock signal receives the output of the first NAND gate as data and the previous input in response to the output of the fourth NAND gate. A third flip flop that outputs a signal.

(Action)

By such an equalizer operation completion state display system, it is possible to confirm the operation completion state and signal disconnection state of the line equalizer, and thus to detect data errors caused by detecting data in the operation of the line equalizer or in the signal disconnection state. It can prevent.

(Example)

Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram showing the configuration of an equalizer operation completion state display system according to an embodiment of the present invention. 2 and 3 show an operation timing diagram for explaining the peak detection method and operation of the equalizer operation completion state display system shown in FIG. 1, respectively.

Referring to FIGS. 1, 2, and 3, first, a state in which a signal is not disconnected, that is, a first section shown in FIG. 3 will be described.

First, a peak signal detected from a peak detector (not shown) is input to the non-inverting terminal (+) of the comparators 110 and 120, and the comparators 110 and 120 respectively convert the peak signal into an inverting terminal (-). Compared to the first reference voltage (Vref1) and the second reference voltage (Vref2) input to the output.

Here, it is assumed that the voltage level to be equalized, that is, the peak signal is 1V, and the first and second reference voltages Vref1 and Vref2 are 1.1V and 0.9V, respectively.

Accordingly, as shown in FIG. 2, the comparator 110 applied with the first reference voltage Vref1 outputs a low level, and the comparator 120 applied with the second reference voltage Vref2 has a high level. level), it can be seen that equalization has been achieved at a desired voltage level.

Next, the output of the comparator 110 is inverted by the inverter 150 and applied at a high level to one input terminal of the NAND gate 160, and the output of the comparator 120 is applied to the other input terminal of the NAND gate 160 to be a D-Flip Flop. It is input as 200 data.

The output of the de-flip flop 200 is controlled by a clock signal CLK, which is variably divided and output by a divider 310 that receives data rate information according to a user setting.

Referring to FIG. 3, when the peak signal detected in the first section is applied to the de-flop flop 200, the output of the de-flop flop 200 may be output when the last clock signal CLK in the first section transitions to a low level. Output at high level to indicate completion of equalizer operation.

In other words, the clock signal CLK transitioned to the low level is inverted by the inverter 350 and applied to one input terminal of the NAND gate 360. The clock signal CLK divided by the divider 310 is output at a high level and input as data of one input terminal of the NAND gate 340 and the de-flop flop 320.

In addition, the de-flop 320 received a high level outputs a low level, which is a previous input signal in synchronization with the clock signal CLK, and the low level output signal is applied to the other input terminal of the NAND gate 340 through the inverter 330. do.

Accordingly, the NAND gate 340 outputs a high level signal, and the NAND gate 360 that receives the output of the inverter 350 and the NAND gate 340 outputs a high level clock signal.

In addition, in response to the clock signal output from the NAND gate 360, the de-flip flop 200 outputs the peak detection signal received from the NAND gate 160 from the time when the second section starts, as shown in FIG. 3.

Subsequently, the peak detector reset by the peak reset signal of the NAND gate 390 that receives the output of the de-flop flop 320 and the output of the de-flop flop 370 performs detection for the next section, that is, the second section. .

However, since no signal is input in the second section, no peak is detected. Therefore, the de-flop flop 200 receives low-level data from the NAND gate 160.

In addition, the operation of the input and the divider 310 and the de-flop flop 320 of the clock signal CLK are the same as those of the above-described first period. Accordingly, a high level clock signal is output from the NAND gate 360, and in response to the clock signal, the de-flip flop 200 transitions the last operation indication of the second section to a low level as shown in FIG. do.

By the equalizer operation completion display system as described above, the operation completion state and signal disconnection state of the line equalizer can be confirmed, and therefore, data errors due to detecting data during operation of the line equalizer or in the signal disconnection state. Can be prevented.

Claims (7)

Means (100) for receiving a peak signal from an external source, comparing the peak signal with the first and second reference voltage signals (Vref1, Vref2) and outputting a peak detection signal; Means (300) for receiving data rate information and a first clock signal (CLK) from an external source and outputting a peak reset signal and a second clock signal; And means for receiving and storing the peak detection signal and outputting the peak detection signal in response to the second clock signal. The method of claim 1, The peak signal comparing means 100 includes: first comparing means for comparing a peak signal input from the outside with a first reference voltage signal Vref1 and outputting the first signal; Second comparing means for comparing the peak signal input from the outside with the second reference voltage signal Vref2 and outputting the second signal; A first inverter 150 for inverting and outputting the output of the first comparing means; Equalizer operation completion state display system comprising a first NAND gate 160, one input terminal receives the output of the first inverter 150, the other input terminal receives the output of the second comparison means. The method of claim 2, The first comparator means is a comparator (110) in which the non-inverting terminal (+) receives a peak signal and the inverting terminal (-) receives a first reference voltage signal (Vref1). The method of claim 2, The second comparison means is a comparator (120) in which the non-inverting terminal (+) receives a peak signal and the inverting terminal (-) receives a second reference voltage signal (Vref2). The method of claim 1, The peak reset signal and the second clock signal output means 300 may include: means 310 for receiving a first clock signal CLK from an external source and dividing the first clock signal CLK in response to data rate information input from the external device; A first flip flop (320) receiving an output of the division means (310) as data and outputting a previous input signal in response to the first clock signal (CLK); A second flip flop (370) for receiving an output of the first flip flop (320) as data and outputting a previous input signal in response to the first clock signal (CLK); A second inverter 350 inverting and outputting the first clock signal CLK; A third inverter 330 which inverts the output of the first flip flop 320 and outputs the inverted output; A fourth inverter 380 for inverting and outputting the output of the second flip flop 370; A second NAND gate 340 on which one input terminal receives the output of the distributing means 310 and the other input terminal receives the output of the third inverter 330; A third NAND gate 390 on which one input terminal receives the output of the first flip flop 320 and the other input terminal receives the output of the fourth inverter 380 and outputs a peak reset signal; Equalization including a fourth NAND gate 360 to which one input terminal receives an output of the second inverter 350 and the other input terminal receives an output of the second NAND gate 340 to output a second clock signal. Operation completion status display system. The method of claim 5, And the first and second flip flops (320, 370) are de-flip flops. The method of claim 1, The means 200 for outputting the peak detection signal in response to the second clock signal receives the output of the first NAND gate 160 as data and the previous input in response to the output of the fourth NAND gate 360. Equalizer operation completion status display system that is a third flip-flop (200) for outputting a signal.

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