JP2841918B2 - Frame synchronization monitoring method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization monitoring system for a PCM communication apparatus, and more particularly to a PC for performing a cyclic code check.
The present invention relates to a frame synchronization monitoring method for an M communication device.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a communication system for performing PCM communication. Reference numerals 211 and 212 denote low-order group multiplexing devices which are PCM communication devices having a cyclic code checking function, and 202 denotes a high-order group multiplexing device connected thereto. The multiplexer 202 is connected to the relay device 24 through the switcher 203.
1,242. Although not shown in the figure, actually, to the right of the relay devices 241, 242,
Similarly, a multiplexing device, a switcher, and a relay device are sequentially connected.

In such a system, for example, the relay device 2
When a line failure or line quality deterioration occurs in 41, the switcher 203 switches the line to the relay device 242 side. As a result, after detecting the PCM input disconnection, the higher-order group multiplexer 202 restarts communication based on the switched PCM signal from the switched relay device 242. However, since the input of the PCM is momentarily interrupted in the high-order group multiplexing device 202, the PL
Due to the relationship between the pull-in time of clock synchronization of the L (Phase Locked Loop) circuit and the like, the internal circuit is not immediately stabilized, and the multiplexing device 202 has a P which contains many errors.
Outputs a CM signal.

In the low-order group multiplexing devices 211 and 212, frame synchronization is lost due to switching of the relay device.
When the PCM signal from the high-order group multiplexing device 202 becomes stable enough to perform synchronization detection, a frame synchronization signal is searched for and confirmed, and a communication service is started. Thereafter, a cyclic code check is performed to confirm that the detected frame synchronization signal is not a pseudo synchronization signal. If the number of error detections is equal to or less than a predetermined value, the communication service is continued.

[0005]

However, in the cyclic code check, unlike the frame synchronization detection based on the coincidence of discrete patterns, all the PCM signals are used, so that the error detection rate is high, and in many cases, the multiplexing apparatus is used. 211 and 212 determine that the confirmed frame synchronization signal is not correct, remove the confirmed frame synchronization again, and search for the frame synchronization signal again. That is, the conventional PCM communication system has a problem that if a communication service is interrupted due to a line failure or the like, the communication service is immediately interrupted even if the communication service is restarted.

SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem and to prevent the service from being interrupted immediately after the result of the cyclic code check after the frame synchronization is established and the communication service is started. It is an object of the present invention to provide a frame synchronization monitoring method.

[0007]

According to the present invention, in a frame synchronization monitoring system for a PCM communication apparatus, a frame synchronization signal included in a PCM signal is detected and a frame synchronization coincidence pulse is output, and the frame synchronization signal cannot be detected. A frame synchronization signal detection circuit for outputting a frame synchronization mismatch pulse, a first gate circuit for passing a predetermined clock based on the first to third control signals,
Counting the clock passing through the gate circuit, a frame counter that outputs a frame position pulse every time the count value reaches a predetermined value, and when the frame position pulse is input, passes the frame synchronization coincidence pulse. A second gate circuit that outputs the passed frame synchronization coincidence pulse to the first gate circuit as the third control signal for opening the first gate circuit, and an input of the frame position pulse. A third gate circuit that passes the frame synchronization non-coincidence pulse; and a set signal when the frame synchronization coincidence pulse input through the second gate circuit counts to a predetermined value. When the frame synchronization mismatch signal is input through the third gate circuit. Data and the third the frame counts the synchronization mismatch pulse count input through the gate circuit outputs a reset signal when it becomes a predetermined value,
A forward protection counter that is reset when the frame synchronization coincidence signal is input through the second gate circuit, and a forward protection counter that is set by the set signal and outputs an output signal at that time to open the first gate circuit A flip-flop circuit that outputs to the first gate circuit as one control signal and is reset by the reset signal;
A synchronization recovery delay circuit for delaying the output signal of the flip-flop circuit by a predetermined time and outputting the same, and a cyclic code check based on the cyclic code included in the PCM signal, and operating with the output signal of the synchronization recovery delay circuit And the number of times that the check result by the check circuit becomes erroneous. When the count value reaches a predetermined value, the first gate circuit is set to one cycle of the clock. An error counter is provided, which outputs the second control signal for closing for a corresponding time to the first gate circuit, and starts an operation by an output signal of the synchronization return delay circuit.

[0008]

Next, an embodiment of the present invention will be described. FIG.
FIG. 1 shows an example of a low-order group multiplexing apparatus configured based on the frame synchronization monitoring method according to the present invention. The PCM signal input from the terminal 1 includes a frame synchronization signal, check bits for cyclic code inspection, an audio signal, and the like. This low-order group multiplexing device detects a frame synchronization signal included in the PCM signal from the terminal 1, and when detecting the frame synchronization signal, outputs a frame synchronization coincidence pulse 14.
On the other hand, when detection is not possible, the frame synchronization mismatch pulse 1
5, a frame synchronization signal detection circuit that outputs
A gate circuit 9 for passing the clock input from the terminal 8 based on the control signal of the above, and counting the clocks passing through the gate circuit 9 and outputting a frame position pulse 16 every time the counted value reaches a predetermined value. Frame counter 1
0, when the frame position pulse 16 is input, the frame synchronization coincidence pulse 14 is passed and the passed frame synchronization coincidence pulse 14 is output to the gate circuit 9 as a third control signal for opening the gate circuit 9. And an AND circuit 4 for passing the frame synchronization mismatch pulse 15 when the frame position pulse 16 is input.
And

The low-order group multiplexing device further counts the frame synchronization coincidence pulse 14 input through the AND circuit 3, and when the counted value reaches a predetermined value, the synchronization recovery signal 1
8 is output, and when the frame synchronization mismatch signal 15 is input through the AND circuit 4, the backward protection counter 5 that is reset and the frame synchronization mismatch pulse 15 input through the AND circuit 4 are counted, and the count value is calculated. An out-of-synchronization signal 17 is output when the value reaches a predetermined value, and when a frame synchronization coincidence signal is input through the AND circuit 3, the signal is set by the forward protection counter 6 to be reset and the synchronization recovery signal 18, and at that time, becomes A flip-flop 7 that outputs the level synchronization recovery latch signal 19 to the gate circuit 9 as a first control signal for opening the gate circuit 9 and is reset by an out-of-sync signal 17.

The low-order group multiplexing device is included in the synchronization recovery delay circuit 11 for delaying the synchronization recovery latch signal 19 from the flip-flop 7 by a predetermined time and outputting the same, and the PCM signal from the terminal 1. A cyclic code check is performed based on the cyclic code, the cyclic code check circuit 12 reset when the output signal 22 from the synchronization recovery delay circuit 11 is at a low level, and the number of times the check result by the check circuit becomes erroneous is counted. , When the count value reaches a predetermined value,
The pseudo-sync detection signal 2 which is a second control signal for closing the gate circuit 9 for a time corresponding to one cycle of the clock
And an error counter 13 that outputs 0 to the gate circuit 9 and is reset by a low-level output signal 22 from the delay circuit 11.

Next, the operation will be described. When the frame synchronization signal detection circuit 2 detects a frame synchronization signal included in the PCM signal from the terminal 1, the frame synchronization signal detection circuit 2
When the frame synchronization signal cannot be detected, a frame synchronization mismatch pulse 15 is output. In the initial state, the frame counter 10 has the frame position pulse 1
6 is held at a high level, so that the coincidence pulse 1
4 is input to the counter 5 through the AND circuit 3 and is input to the gate circuit 9 as a third control signal. As a result, the counter 5 starts counting the coincidence pulse 14, and the gate circuit 9 opens to supply the clock from the terminal 8 to the counter 10, so that the counter 10 starts counting.

After the counter 5 starts counting, if the non-coincidence pulse 15 is input, the counter 5 is reset. However, if the coincidence pulse 14 is input continuously a predetermined number of times for backward protection, the synchronization is stopped. A return signal 18 is output.
At this time, synchronization is confirmed, and the synchronization recovery signal 1
8, the flip-flop 7 is set, and the gate circuit 9 is held open by the high-level synchronization return latch signal 19 output from the flip-flop 7.
Therefore, the clock from the terminal 8 is continuously input to the counter 10. In this state, the frame synchronization signal is not temporarily detected, and the coincidence pulse 14 is not supplied to the gate circuit 9 as the third control signal. Therefore, the counter 10 continues counting the clock.

On the other hand, the forward protection counter 6 has a logical product circuit 4
When the non-coincidence pulse 15 is input through the counter, the number is counted. When the coincidence pulse 14 is not input and the non-coincidence pulse 15 is input continuously for a predetermined number of times for forward protection, synchronization is lost, and the counter 6 outputs an out-of-sync signal 17. As a result, the flip-flop 7 is reset, the gate circuit 9 is closed by the low-level synchronization return latch signal 19 output at that time, and the counter 10 stops while maintaining the frame position pulse 16 at the high level. That is, the state returns to the state in which the detection circuit 2 waits for the detection of the frame synchronization signal.

When the coincidence pulse 14 is continuously input to the counter 5 for the predetermined number of times and the synchronization is confirmed, the cyclic code check circuit 12 and the error counter 13 are reset and the operation starts. Since the synchronization recovery latch signal 19 is delayed by the synchronization recovery delay circuit 11,
The test circuit 12 and the counter 13 are not released from the reset immediately after the synchronization return latch signal 19 is output, and after a predetermined time has elapsed, the reset is released and the operation starts. Then, the inspection circuit 12 detects P from the terminal 1
Check bit for cyclic code detection included in the CM signal and P
The CM signal is compared with the cyclic code detection value, and when the comparison result does not match, a signal 23 indicating that is output.
The counter 13 counts the number of times that the signal 23 is output, and when the value reaches a predetermined value, outputs the pseudo synchronization detection signal 20 to the gate circuit 9 as a second control signal.
Thus, the gate circuit 9 is closed for a time corresponding to one cycle of the clock. As a result, the frame position pulse 16
And the coincidence pulse 14 has a different timing, the non-coincidence pulse 15 is continuously input to the counter 6, and the flip-flop 7 is reset. That is,
When the counter 13 outputs the pseudo synchronization detection signal 20, it is determined that the synchronization signal detected by the detection circuit 2 is a pseudo synchronization signal. In this case, the process exits the synchronization confirmation state and searches for a new synchronization signal. I do.

In this multiplexer, the delay circuit 1
1 is provided, the synchronization return signal 19 is output from the flip-flop 7, and even if the synchronization is confirmed,
The detection circuit 12 does not start operating immediately. Accordingly, the PCM signal is further stabilized during this period, and thereafter, when the test circuit 12 starts operating, the error rate is reduced, and the counter 13 outputs the pseudo-synchronous detection signal 20 unless there is any abnormality. Never. Therefore, in a system using such a multiplexing device, after confirming synchronization and restarting communication service as in the related art, the service is not interrupted immediately due to the result of the cyclic code check.

[0016]

As described above, in the frame synchronization monitoring method of the present invention, the frame synchronization is confirmed by detecting the frame synchronization signal included in the PCM signal, and then the confirmation of the frame synchronization by the pseudo synchronization signal is prevented. When performing a cyclic code check to perform the operation, the operation of the cyclic code check circuit is started with a delay of a predetermined time.
Therefore, the cyclic code check is performed in a state where the PCM signal is sufficiently stable, and it is possible to prevent the service from being interrupted immediately after resuming the communication service after confirming the frame synchronization.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a configuration example of a low-order group multiplexing device based on a frame synchronization monitoring system of the present invention.

FIG. 2 is a block diagram illustrating an example of a communication system that performs PCM communication.

[Explanation of symbols]

 1, 8 terminal 2 frame synchronization signal detection circuit 3, 4 AND circuit 5 backward protection counter 6 forward protection counter 7 flip-flop 9 gate circuit 10 frame counter 11 synchronization return delay circuit 12 cyclic code check circuit 13 error counter 202 higher order group multiplexing Device 203 Switcher 211, 212 Low-order group multiplexing device 241, 242 Relay device

Claims (1)

(57) [Claims] In a frame synchronization monitoring method for a PCM communication device, a frame synchronization signal included in a PCM signal is detected and a frame synchronization coincidence pulse is output. If the frame synchronization signal cannot be detected, a frame synchronization non-coincidence pulse is output. A frame synchronizing signal detection circuit, and a first circuit for passing a predetermined clock based on the first to third control signals.
A gate circuit that counts the clocks that have passed through the first gate circuit, and outputs a frame position pulse every time the count value reaches a predetermined value; and when the frame position pulse is input, A second gate circuit that passes the frame synchronization coincidence pulse and outputs the passed frame synchronization coincidence pulse to the first gate circuit as the third control signal for opening the first gate circuit And a third gate circuit that passes the frame synchronization mismatch pulse when the frame position pulse is input, and counts the frame synchronization match pulse input through the second gate circuit to determine a predetermined value. Output a set signal when the value of
When the frame synchronization mismatch signal is input through the gate circuit, the backward protection counter that is reset and the frame synchronization mismatch pulse input through the third gate circuit are counted and the count value becomes a predetermined value. When the frame synchronization coincidence signal is input through the second gate circuit, a reset signal is output, and the forward protection counter to be reset is set by the set signal. A first control signal for opening the gate circuit to the first gate circuit, the flip-flop circuit reset by the reset signal, and an output signal of the flip-flop circuit delayed by a predetermined time. An output synchronization recovery delay circuit, and a cyclic code detection based on a cyclic code included in the PCM signal. Was carried out, and cyclic redundancy check circuit to start the operation by the output signal of the synchronous return delay circuit counts the number of times the test result by the testing circuit is an error,
When the count value reaches a predetermined value, outputting the second control signal for closing the first gate circuit for a time corresponding to one cycle of the clock to the first gate circuit, A frame synchronization monitoring system, comprising: an error counter that starts operation in response to an output signal of the synchronization recovery delay circuit.