JPH0983503A - Frame synchronizing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid erroneous synchronous detection by means of a pseudo frame synchronizing other than a frame synchronizing signal included in a reception signal. SOLUTION: A means 31 detects the frame synchronizing signal in the reception signal with the error allowance of a prescribed bit. A control means 33 controls an aperture for outputting an aperture signal (A) which causes a detection signal to pass through by a gate 32 at every time L corresponding to a frame synchronizing period from the supply time of the detection signal. A protection means 34 judges it as a frame synchronous state when it continuously detects passage detection signals for the prescribed number of times. Furthermore, a means for storing the number of erroneous bits less than error allowance which the detection means 31 outputs and a comparison means 36 outputting the aperture set signals(AS) to the means 33 when the number of the erroneous bits is less than the number of stored erroneous bits are provided. The means 33 rests previous aperture control at the time of AS input and outputs A at every time L from input time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization device. This frame synchronization device is used for a communication device and is a device for receiving a digital signal by a time division multiplexing system, for detecting a frame synchronization signal from a received signal and establishing frame synchronization.

Particularly, for some reason, when the received signal includes a signal having a pattern similar to the frame synchronization signal in the same cycle as the frame cycle, false synchronization due to the pseudo frame synchronization signal is detected and the original normal synchronization signal is detected. It is a frame synchronization device for resynchronizing with.

[0003]

2. Description of the Related Art Generally, in communication by a time division multiplexing system, a signal is divided into signals of a certain length (length L bits) called "frames" and transmitted. To detect the beginning of the frame at the beginning of each frame or at a predetermined position,
A frame synchronization signal (denoted as S0) having a predetermined specific pattern is inserted.

On the receiving side, the pattern matching the S0 is detected from the received signal to start the frame. The problem here is that the frame sync signal is overlooked due to noise or the like, or a detection error occurs.

Therefore, when the S0 is searched first, the means of "error tolerance" and "backward protection" are used. “Error tolerance” means t0 out of m bits when a known S0 (length m bits) is detected from the received signal sequence.
This is a technology that reduces the probability of missing a sync signal even in a noisy environment by allowing errors up to bits.

The "backward protection" is based on the position where S0 is detected first, and the detection position of the next sync word determines the detection result only at a specific timing determined by an integral multiple of the frame length L. This is a technique for determining that the frame synchronization is established only when the synchronization signals for the predetermined number of protection stages N times are continuously detected.

This prevents erroneous synchronization due to detection under error tolerance (frame synchronization at erroneous timing due to erroneously determining a signal other than the original frame synchronization signal as a synchronization signal).

FIG. 8 shows a block diagram of a conventional frame synchronization device having three detection error allowable bits of a synchronization word and three stages of backward protection, and FIG. 9 shows the timing of the frame synchronization operation of the frame synchronization device shown in FIG. A chart is shown.

The frame synchronizer shown in FIG. 8 comprises a pattern detector 31, an AND circuit 32, an aperture control circuit 33, and a rear protection circuit 34. The pattern detector 31 detects the individual bits of the received signal S1 to detect the UW (synchronization word) shown in FIG. 8 for frame synchronization, and the detected signal S
2 is output to the AND circuit 32. Its error tolerance is 3 out of m bits of UW.

The aperture control circuit 33 closes the aperture signal S3 as "L" level from the input of the detection signal S2 to the time corresponding to the L bit shown in FIG. 9, and the AND circuit 32 cuts off the detection signal S2. .

The rear protection circuit 34 is a circuit for performing the above-mentioned rear protection on the signal which has passed through the AND circuit 32, and is started only when the synchronizing signal of the frame length L is detected three times in succession. It is determined that the frame synchronization has been established, and the synchronization state display display signal S4 indicating the determination result, that is, synchronization / asynchronization, is output.

In such a structure, the frame synchronizer starts searching for the UW at time t1 shown in FIG.
At the initial stage, the aperture signal S3 is in the "H" level open state.

At time t2, it is assumed that the sync word is detected with a 1-bit error. As a result, the aperture control circuit 33 closes by setting the aperture signal S3 to the “L” level, and the detection signal (detection pulse) S2 is transmitted to the rear protection circuit 3 up to the detection position after the time corresponding to L bits.
It is prohibited to input in 4.

Therefore, at time t3, the detection signal S2 detected with a 3-bit error is not transmitted to the rear protection circuit 34 and the subsequent circuits. Then, when the sync word is detected at time t5 and time t8, the rear protection circuit 34 detects that the sync word is detected for three consecutive frames, and the sync status display signal S4 indicates the frame sync status. Will be shown.

[0015]

By the way, in the above-described conventional frame synchronization apparatus for performing error tolerance and backward protection, the received signal is located in a place other than the original frame synchronization signal, that is, next to UW in FIG. If there is a signal in the information shown that has a pattern very close to the frame synchronization signal and appears in synchronization with the frame period, there is a problem in that it is erroneously synchronized.

In this case, erroneous synchronization occurs even in a good reception state in which an error is not mixed in the received signal due to noise or the like. FIG. 10 shows an operation timing chart showing such a case.

In FIG. 10, the sync word detecting operation is started at time t1 '. The first detected sync word is a similar pattern in the information at time t3,
It is assumed that the error is detected with 3 bits.

The aperture control circuit 33 closes the aperture signal S3 and prohibits the transmission of the detection signal S2 until the time L elapses. Therefore, the detection signal S2 at the time of reception of the regular synchronization word at time t5 is also prohibited.

At time t6 and time t9, since the sync word is detected with a 3-bit error, the backward protection circuit 3
4 operates as if the frame synchronization has been established and outputs the synchronization state display signal S4 indicating the synchronization, which actually means that the synchronization has been made at the wrong timing.

The present invention has been made in view of the above circumstances, and provides a frame synchronization device capable of avoiding erroneous synchronization detection due to a pseudo frame synchronization signal other than the frame synchronization signal included in the received signal. Is intended.

[0021]

FIG. 1 shows the principle of a frame synchronizer according to the present invention. The frame synchronization device shown in this figure detects a detection means 31 for detecting a frame synchronization signal in a received signal with an error tolerance of a predetermined bit, and every time after a time L corresponding to a frame synchronization section from the time when the detection signal of the detection means 31 is supplied. Further, the control means 33 for performing aperture control for outputting the aperture signal to the gate 32 for allowing the detection signal to pass through the gate 32, and the frame synchronization state when the detection signal passing through the gate 32 is detected a predetermined number of times in succession. The protection means 34 is provided.

A feature of the present invention is that the storage means 37 for storing the number of error bits output from the detection means 31 which is equal to or less than the predetermined number of bits, and the number of error bits output from the detection means 31 are stored in the storage means 37. And a comparison means 36 for outputting an aperture set signal to the control means 33 when the number of stored error bits is smaller than the stored error bit number.
When the aperture set signal is input, the aperture control up to the previous time is reset, and the aperture signal is output every time the above-mentioned time L has elapsed from the input.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of a frame synchronization device having a synchronization word detection error allowable bit number of 3 and backward protection of 3 stages according to the first embodiment of the present invention. In FIG. 2, parts corresponding to the respective parts of the conventional example shown in FIG. 8 are designated by the same reference numerals, and description thereof will be omitted.

The configuration of the first embodiment shown in FIG. 2 is different from the conventional example shown in FIG. 8 in that an error number comparison circuit 36 and an error number storage circuit 37 are newly provided, and the aperture control circuit 33 causes the aperture set signal S8. This is because the aperture control until then is reset at the time of input and the aperture control is newly performed.

The error number comparison circuit 36 is used by the pattern detector 3
The error bit number signal S5 output from 1 is compared with the error number S7 stored in the error number storage circuit 37, and when the error bit number signal S5 is smaller than the error number S7, the aperture set signal S8 is output. Is.

The error number storage circuit 37 includes an error number comparison circuit 3
The error bit number signal S5 sent via 6 is stored. Further, the aperture control circuit 33 releases the forcibly closed state of the aperture signal S3 after a time corresponding to L bits from the time when the aperture set signal S8 was input.

The operation of the frame synchronizer having such a configuration will be described with reference to FIG. At time t1 ′ shown in FIG. 3, the pattern detector 31 starts the search for the synchronization word,
It is assumed that an incorrect sync word is detected by bit error 3 in 3.

In this case, the error number comparison circuit 36 transfers the detected error number by the error bit number signal S5 to the error number storage circuit 37 because of the first synchronization word detection, and the content of the error number storage is " Set to 3 ”.

The aperture control circuit 33 closes the aperture signal S3 at "L" level as usual, and thereafter prohibits passage of the detection signal S2 until the time L elapses. Time t5
When the pattern detector 31 detects a sync word with a bit error of 0, the error number comparison circuit 36 determines that the error bit number S7 of “3” stored in the error number storage circuit 37 and the current pattern detector 31 are "0" of detected error bit number
Compare.

As a result, since the number of errors in the pattern detected this time is smaller, the aperture set signal S8 is output. As a result, the aperture control circuit 33 causes the time t
The information about the time L held on the basis of 3 is reset, and the aperture control is restarted on the basis of the time t5.

Next, the aperture signal S3 is opened at the times t8 and t12, and at these positions, since the normal sync word is received, the detection signal S2 is generated and the rear protection circuit 34 makes the appropriate signal. A process for establishing frame synchronization is performed.

In the first embodiment described above, the backward protection operation can be corrected and continued by the detection result of the sync word having a smaller number of errors even during the backward protection, so that erroneous synchronization may occur. Even when the reception signal S1 is being received, correct frame synchronization can be established faster.

Next, a second embodiment will be described with reference to FIG. However, in FIG. 4, parts corresponding to the respective parts of the first embodiment shown in FIG. 2 are designated by the same reference numerals, and description thereof will be omitted.

In the second embodiment shown in FIG. 4, an error counter circuit group 39 and a set signal generating circuit 40 are newly provided,
This is because the aperture control circuit 33 resets the aperture control until then when the open aperture set signal S12 is input, and outputs the aperture signal S3 as in the initial stage.

The error counter circuit group 39 comprises counters for the number of bits of the sync word UW to be detected. For example, when using a 4-bit synchronization word, four counter circuits are required. Each counter performs a count-up operation corresponding to the bit position where an error has occurred (indicated by the error bit position signal S10) when the sync word is detected. Further, it is reset when the open aperture set signal S12 is input.

The set signal generation circuit 40 opens the open aperture set signal S when the error number signal S11 from the error counter circuit group 39 exceeds the allowable error number "3".
12 is an error counter circuit group 39 and an aperture control circuit 3
It is designed to output to 3.

The operation of such a configuration will be described with reference to FIG. It is assumed that the synchronization word search is started from time t1 ′ shown in FIG. 5, and the fixed data pattern in the information is erroneously detected as a synchronization word due to bit error 3 at time t3.

The error positions at that time are b0, b1,
It is assumed that there are 3 bits of b3. At this time, the error counter 1, the error counter 2, and the error counter 4 corresponding to each error position perform a count-up operation, and the values thereof become “1, 1, 0, 1” in the order of the counters 1 to 4.

The aperture control circuit 33 closes the aperture signal in the conventional manner and thereafter prohibits passage of the detection signal S2 until the time L elapses, and at the same time, the error counter circuit group 3
The operation of 9 is also prohibited. At time t7 and time t10, when the fixed data pattern in the information is erroneously detected as the synchronization word with the number of errors of 3, the error counter 1, the error counter 2, and the error counter 4 perform the count-up operation, and their contents Becomes 3.

The set signal generation circuit 40 detects that the output of any of the error counters exceeds a predetermined number of errors (3 in this case) and outputs an aperture set signal. As a result, the aperture control circuit 33 becomes the open aperture state again, and starts searching for the synchronization word again.

Although not shown in FIG. 5, once the detection at the normal sync word position is performed at time 12, the error counter circuit operates only at the normal position thereafter, and the error counter counts up. Is only when an error occurs due to thermal noise or the like, and the probability that only a specific error counter corresponding to a specific bit position will count up is low. Therefore, the value of the error counter is not counted up to the number at which the open aperture set signal S12 should be output, so that the synchronization is established at the regular position.

According to the second embodiment described above, after the synchronization is established, without waiting for a result such as error information in the information,
Only with the received data pattern and the sync word detection mechanism, false sync can be detected and returned to the open aperture.

Next, a third embodiment will be described with reference to FIG. However, in FIG. 6, parts corresponding to the respective parts of the first embodiment shown in FIG. 2 are designated by the same reference numerals, and description thereof will be omitted.

In the third embodiment shown in FIG. 6, a pattern recording / majority decision processing circuit 42 is newly provided, and when the aperture control circuit 33 inputs the open aperture set signal S12, the aperture control until then is reset, and the same as in the initial stage. Is to output the aperture signal S3.

The pattern recording / majority decision processing circuit 42 records an odd number of patterns of the reception signal S1 corresponding to the synchronization word detected by the pattern detector 31, and for each bit of the recorded reception signal pattern. The majority decision is performed by arranging a large number into each bit to make a majority decision pattern.The majority decision pattern is compared with the original synchronization word pattern, and if the majority decision pattern differs by a predetermined number of bits or more, the open aperture is set. The set signal S12 is output.

The operation of such a configuration will be described with reference to FIG. It is assumed that the synchronization word search is started from time t1 ′ shown in FIG. 7, and the fixed data pattern in the information is erroneously detected as a synchronization word due to bit error 3 at time t3.

At this time, the received signal pattern (UWt1) corresponding to the detected sync word is recorded in the pattern recording circuit 42. The aperture control circuit 33 closes the aperture signal in the conventional manner, and thereafter prohibits passage of the detection pulse until the time L elapses, and at the same time prohibits the operation of the pattern recording circuit.

At time t7 and time t10,
When the fixed data pattern in the information is erroneously detected as a synchronization word with the number of errors of 3, the pattern recording circuit 4
2 the received signal patterns (UWt2 and UWt3;
(Not shown) is recorded.

At the time when detection of a predetermined odd number (three times in this case) is completed, the pattern recording / majority decision processing circuit 42 performs a majority decision process for each bit on the received signal patterns UWt1 to UWt3 recorded up to that point. To do. In this case, the majority vote is 2/3. In the majority processing circuit 42,
Compared to the original sync word pattern,
More than a predetermined number of bits (in this case, for example, 1 bit)
If they are different, the open aperture set signal S12 is output.

As a result, the aperture control circuit 33
The state becomes the open aperture state again, and the search for the sync word is started again. Although not shown in FIG.
Once the detection is performed at the regular sync word position, the error counter circuit operates only at the regular position thereafter, so the error counter counts up only when an error occurs due to thermal noise, The probability of error concentration at a particular bit position is low.

Therefore, the result of the majority vote can be expected to match the original synchronization word pattern with the error bit number smaller than the error bit number in one reception.
As a result, the synchronization establishing operation is performed without outputting the open aperture set signal S12 depending on the result of the majority decision process.

According to the third embodiment described above, after the synchronization is established, without waiting for a result such as error information in the information,
Only with the received data pattern and the sync word detection mechanism, false sync can be detected and returned to the open aperture.

[0053]

As described above, according to the frame synchronization signal of the present invention, it is possible to avoid the false synchronization detection due to the pseudo frame synchronization signal other than the frame synchronization signal included in the received signal.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram of a frame synchronization device according to a first exemplary embodiment of the present invention.

3 is a timing chart for explaining a frame synchronization operation by the frame synchronization device shown in FIG.

FIG. 4 is a block diagram of a frame synchronization device according to a second exemplary embodiment of the present invention.

5 is a timing chart for explaining a frame synchronization operation by the frame synchronization device shown in FIG.

FIG. 6 is a block diagram of a frame synchronization device according to a third exemplary embodiment of the present invention.

7 is a timing chart for explaining a frame synchronization operation by the frame synchronization device shown in FIG.

FIG. 8 is a block diagram of a conventional frame synchronization device.

9 is a timing chart for explaining a frame synchronization operation by the frame synchronization device shown in FIG.

10 is a timing chart for explaining a frame synchronization malfunction by the frame synchronization device shown in FIG.

[Explanation of Codes] 31 Detecting Means 32 Gates 33 Control Means 34 Protecting Means 36 Comparing Means 37 Storage Means

Claims (5)

[Claims] 1. A detection means for detecting a frame synchronization signal in a received signal with error tolerance of a predetermined bit, and a time L corresponding to a frame synchronization section from the time when the detection signal of the detection means is supplied.
Each time after, control means for performing aperture control for outputting an aperture signal to the gate for passing the detection signal to the gate, and a frame synchronization state when the detection signal passing through the gate is continuously detected a predetermined number of times In the frame synchronization device, the storage means stores the number of error bits output from the detection means, and the number of error bits output from the detection means is the error bit stored in the storage means. When it is smaller than a number, the control means is provided with a comparison means for outputting an aperture set signal, the control means resets the aperture control up to the previous time when the aperture set signal is input, and from the input time. A frame synchronization apparatus, wherein the aperture signal is output every time the time L has passed. 2. The frame synchronization apparatus according to claim 1, wherein said storage means stores the number of error bits output from said detection means and which is equal to or less than said error allowable number. 3. A detection means for detecting a frame synchronization signal in a received signal with error tolerance of a predetermined bit, and a time L corresponding to a frame synchronization section from the time when the detection signal is supplied by the detection means.
Each time after, control means for performing aperture control for outputting an aperture signal to the gate for passing the detection signal to the gate, and a frame synchronization state when the detection signal passing through the gate is continuously detected a predetermined number of times In the frame synchronization device including the protection means for controlling the error bit, an error counter that counts error bits for each error bit position output from the detection means, and a count value of any error bit of the error counter is a predetermined value. And a generating means for generating an open aperture set signal when the above, when the open aperture set signal is generated,
The frame synchronization device, wherein the error counter is reset, and the control means performs control similar to control for outputting the aperture set signal at an initial stage. 4. The generator according to claim 3, wherein the generating means generates the open aperture set signal when the count value becomes equal to a predetermined value equal to or less than the allowable error number. Frame synchronizer. 5. A detection means for detecting a frame synchronization signal in a received signal with error tolerance of a predetermined bit, and a time L corresponding to a frame synchronization section from the time when the detection signal is supplied by the detection means.
Each time after, control means for performing aperture control for outputting an aperture signal to the gate for passing the detection signal to the gate, and a frame synchronization state when the detection signal passing through the gate is continuously detected a predetermined number of times In the frame synchronization device including the protection means, the pattern of the received signal corresponding to the frame synchronization signal detected by the detection means is recorded in an odd number of sets, and the recorded odd number of received signal patterns is recorded for each bit. The majority decision is performed by arranging a large number of numerical values as a representative value, the arranged one pattern is made into a majority decision pattern, and the majority decision pattern and the original synchronization word pattern are compared, and the majority decision pattern is different by a predetermined number of bits or more. A majority decision processing unit for outputting an open aperture set signal, If the Tsu door signal is generated,
A frame synchronization device, wherein the received signal pattern recorded in the majority processing means is reset, and the control means performs the same control as the control for outputting the aperture set signal at the initial stage.