JP2000224153A - Synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correctly detect a synchronization code even if a false synchronization code are produced. SOLUTION: In this synchronization circuit, a synchronization code detection circuit 2 detects a synchronization code from a digital data series and outputs a synchronization code detection signal. A pseudo-detection signal output circuit 3 outputs a pseudo-detection signal for a time when a succeeding synchronization code is to be detected and a predication signal circuit 4 outputs a prediction signal. A counter circuit 5 counts the number of times when the prediction signal and the synchronization code detection signal are received with coincidence, a comparator circuit 7 compares the count of the counter circuit 5 with a register value of a register circuit 6 and a prediction control circuit 8 outputs a prediction control signal under a prescribed condition from the comparison result. When there is a temporal deviation between the synchronization code detection signal and the pseudo-detection signal, a detection signal adjustment circuit 9 outputs only a signal that was received earlier.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization circuit for detecting a delimiter (synchronization code) for each group (frame) of data when reading information from an information recording medium such as an optical disk on which information is recorded. And an optical disc recording apparatus.

[0002]

2. Description of the Related Art In a detection operation of a synchronization code indicating a frame segment of a digital data string, a pseudo signal output when a synchronization code is not detected at a predicted time position and an actual synchronization code detection signal are compared with each other. When both signals are shifted in time in this way,
A synchronizing circuit for preventing a malfunction that occurs when the count value of the frame number advances by one is disclosed in, for example, Japanese Patent Laid-Open No.
No. 15 discloses this.

[0003]

SUMMARY OF THE INVENTION Japanese Patent Application Laid-Open No. Hei 10-13
The synchronous circuit disclosed in Japanese Patent No. 4515 predicts the time at which the next synchronous code will occur based on the synchronous code detection signal. However, in a data string other than the synchronization code,
False due to scratches on the recording medium (optical disk etc.)
When the next synchronization code is predicted based on the false synchronization code, there is a problem that the prediction signal does not match the true synchronization code and malfunctions. .

Further, when the clock frequency used in the synchronization circuit and the clock frequency of the digital data sequence on the recording medium are temporarily shifted, the mismatch between the prediction signal and the true synchronization code continues, causing a malfunction. There's a problem. The present invention has been made to solve such a problem, and a first object of the present invention is to provide a synchronization circuit that can correctly detect a synchronization code even when a false synchronization code occurs. Even if the true sync code mismatches continue,
A second object is to provide a synchronization circuit capable of correctly detecting a synchronization code.

[0005]

In order to achieve the first object, the present invention provides a synchronous circuit having the following means. That is, the synchronization circuit according to the present invention includes: a synchronization code detection unit that detects a synchronization code from a digital data sequence configured in units of frames including a synchronization code and outputs a detection signal; Prediction signal output means for predicting a time at which the next synchronization code is to be detected by the synchronization code detection means based on the detection signal, and outputting a prediction signal at the time at which the synchronization code is to be detected; A pseudo-detection unit that predicts the time at which the next synchronization code is to be detected by the synchronization code detection unit based on the detection signal output from the unit, and outputs a pseudo-detection signal at the detection time. Signal output means.

Further, a counting means for counting the number of times the detection signal is output while the prediction signal is being output, and if the count value of the counting means is less than a predetermined value M, A gate means for invalidating the prediction signal and passing the detection signal at all times and, if the count value is equal to or more than the predetermined value M, passing the detection signal only when the prediction signal is input; When there is a time difference between the two signals, there is provided a detection signal adjusting means for outputting the earlier signal of the two signals. Then, means for arbitrarily setting the predetermined value M as a natural number value may be provided.

The present invention also provides a synchronous circuit configured as follows by partially changing the synchronous circuit in order to achieve the second object. That is, the synchronizing circuit outputs the prediction signal based on a signal from the prediction determining unit that determines whether or not the detection signal is output when the prediction signal is being output. The first counting means for counting the number of times the detection signal is output when the detection signal is output, and the detection signal is not output when the prediction signal is output based on a signal from the prediction determination means. Second counting means for counting the number of continuous times.

If the count value of the first counting means is less than a first predetermined value M, the prediction signal is invalidated and the detection signal is always passed,
If the count value is equal to or more than a first predetermined value M, the detection signal is passed only when the prediction signal is input, and the count value of the second counting means is equal to or more than a predetermined second predetermined value N. , When the prediction signal is invalidated, the detection signal is always passed, and the count value of the first counting means is set to 0, and when there is a time difference between the detection signal and the pseudo detection signal, Detection signal adjusting means for outputting the earlier signal of the two signals. Then, it is preferable to provide means for setting the first predetermined value M and the second predetermined value N which are larger than the first predetermined value M as arbitrary natural numbers.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment of the synchronization circuit according to the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing the configuration of the synchronization circuit. This synchronization circuit includes a PLL (Phase Locked Loop) circuit 1 that is a circuit that outputs a clock synchronized with a change point of data of an input digital data series.
The clock output from the PLL circuit 1 is input to each circuit constituting the synchronous circuit.

Further, the synchronization circuit detects a synchronization code from the input digital data sequence and outputs a synchronization code detection signal based on the detection of the synchronization code. Have. Further, based on the synchronization code detection signal from the synchronization code detection circuit 2, a pseudo synchronization code detection signal having a pulse width of 1 clock is output at a time when the next synchronization code is to be detected by the synchronization code detection circuit 2. A pseudo detection signal output circuit 3 is provided as a pseudo detection signal output means.
Then, the pseudo synchronization code detection signal is used as a pseudo detection signal.

Similarly, based on the synchronization code detection signal from the synchronization code detection circuit 2, a time at which the next synchronization code is to be detected by the synchronization code detection circuit 2 is predicted, and a prediction signal is output at the predicted time. And a prediction signal output circuit 4 serving as a prediction signal output unit. This prediction signal is a signal having a longer time width than the pseudo detection signal output from the pseudo detection signal output circuit 3 and a pulse signal having a time width of several clocks before and after the pseudo detection signal. .

An AND circuit 11 is provided between the synchronization code detection circuit 2 and the pseudo detection signal output circuit 3 and the prediction signal output circuit 4, and the synchronization code detection signal is pseudo detected through the AND circuit 11. The signal is output to the signal output circuit 3 and the prediction signal output circuit 4.

The synchronization circuit has an AND circuit 12 to which a prediction signal from the prediction signal output circuit 4 and a synchronization code detection signal from the synchronization code detection circuit 2 are input, respectively. The counter circuit 5 counts the number of times that the prediction signal and the synchronization code detection signal coincide with each other according to the output of the counter 5 and are input. That is, the AND circuit 12 and the counter circuit 5 constitute a counting unit.

Further, the synchronizing circuit has a register circuit 6 for holding a predetermined value M of a natural number as a register value.
It is arbitrarily set from the PU, and here it is assumed that M = 2 as an example.

The synchronizing circuit comprises a counter circuit 5
And a prediction control circuit 8 for outputting a prediction control signal under predetermined conditions based on the comparison result. The predetermined condition is that if the count value is less than the predetermined value M from the comparison result of the count value of the counter circuit 5 and the register value (predetermined value M) of the register circuit 6 by the comparison circuit 7, the prediction control circuit 8 Outputs a predictive control signal,
If the count value is equal to or more than the predetermined value M, the condition is that the prediction control circuit 8 does not output the prediction control signal.

An OR circuit 1 for inputting the prediction control signal and the prediction signal output from the prediction signal output circuit 4
And the control-predicted signal output from the OR circuit 13 is input to the AND circuit 11 together with the synchronization code detection signal from the synchronization code detection circuit 2 to generate a synchronization code detection signal. Is passed or not.

That is, if the count value of the counter circuit 5 is less than the predetermined value M, the prediction control signal is input to the AND circuit 11 to invalidate the prediction signal from the prediction signal output circuit 4 and the synchronization code detection signal is generated. The signal always passes through the AND circuit 11 and the count value of the counter circuit 5 is a predetermined value M.
In this case, the prediction control signal is not input to the AND circuit 11 and the synchronization code detection signal passes through the AND circuit 11 only when the prediction signal from the prediction signal output circuit 4 is input. Therefore, a gate means is constituted by the register circuit 6, the comparison circuit 7, the prediction control circuit 8, the OR circuit 13, the AND circuit 11, and the like.

On the other hand, in this synchronous circuit, the respective signals from the pseudo detection signal output circuit 3 and the prediction signal output circuit 4 are input, and the synchronous code detection signal from the synchronous code detection circuit 2 is transmitted via the AND circuit 11. And a detection signal adjustment circuit 9 which is a detection signal adjustment means to be inputted.
Then, this detection signal adjustment circuit 9 removes only the previous signal when there is a time lag between the synchronization code detection signal from the synchronization code detection circuit 2 and the pseudo detection signal from the pseudo detection signal output circuit 3. Output.

Here, the operation of the synchronous circuit shown in FIG. 1 will be described with reference to the timing chart shown in FIG. A case where a digital data sequence is input to the synchronization circuit and a synchronization code detection signal as shown in FIG. 2 is output from the synchronization code detection circuit 2 in FIG. 1 will be described. FIG.
In the synchronization code detection signal shown in (1), the pulse marked with x is a false synchronization code detection signal. A pulse indicated by a broken line with a triangle indicates a case where a true synchronization code is not detected, and there is actually no pulse. The pulse with a circle is a true synchronization code detection signal.

First, when the entire synchronous circuit is reset, the count value of the counter circuit 5 is set to 0, and the prediction control signal output from the prediction control circuit 8 becomes H (high level). When the prediction control signal is H, since the H prediction control signal is input to the AND circuit 11 via the OR circuit 13, the synchronization code detection signal is input to the prediction signal output circuit 4 as it is.

Therefore, one frame after the occurrence of a pulse with a cross of the synchronization code detection signal, the prediction signal output circuit 4 outputs a prediction signal indicating when the next synchronization code should arrive, and outputs a pseudo detection signal. The circuit 3 outputs a pseudo detection signal. After that, when the prediction signal becomes H as shown in FIG. 2, the synchronization code detection signal has no pulse and the prediction has been lost, so that no signal is output from the AND circuit 12 and the counter circuit 5 counts. The value remains at 0.

FIG. 2 in which a true synchronization code is not detected
At the time point represented by, no synchronization code detection signal is output from the synchronization code detection circuit 2, so no signal is output from the AND circuit 12, and the count value of the counter circuit 5 remains at 0, as in the above case. Next, when the pulse of the true synchronization code detection signal indicated by ○ is output from the synchronization code detection circuit 2, the prediction signal output circuit 4 and the pseudo detection signal output circuit 3
Outputs a prediction signal and a pseudo detection signal one frame after that point.

Since the next pulse of the true synchronization code detection signal matches the prediction signal and is predicted, the count value of the counter circuit 5 becomes 1. At this time, the pulse of the pseudo detection signal and the pulse of the synchronization code detection signal usually have a slight time lag. Therefore, the detection signal adjustment circuit 9 outputs the pulse generated earlier as a synchronization signal of the synchronization circuit.

Further, when the count value of the counter circuit 5 is 1
After that, in the synchronization code detection signal shown in FIG.
When the next true sync code detection signal pulse is output,
The prediction is performed again, and the count value of the counter circuit 5 becomes “2” which is a predetermined natural number M held as a register value of the register circuit 6.

Then, the comparison circuit 7 outputs a signal indicating that the count value of the counter circuit 5 matches the register value of the register circuit 6 to the prediction control circuit 8, and the prediction control circuit 8 outputs the prediction control signal to H To L (low level). As a result, the synchronization code detection signal passes through the AND circuit 11 only when the prediction signal from the prediction signal output circuit 4 is input.

Therefore, after that, when the prediction signal is L, the pulse of the false synchronization code detection signal is output to the synchronization code detection circuit 2.
The synchronous circuit operates stably without being adversely affected even if the signal is output from the synchronous circuit. Thereafter, the count value of the counter circuit 5 increases by one each time a prediction is made, and stops at the maximum value. As described above, even if the occurrence of the next synchronization code is predicted based on the false synchronization code detection signal,
Until the prediction reaches M times set as the predetermined value, the configuration is such that the prediction signal is not employed, so that a malfunction does not occur with the prediction being incorrect.

Here, a specific configuration example of the detection signal adjusting circuit 9 is shown in FIG. 3, and its operation will be described with reference to a timing chart shown in FIG. This detection signal adjustment circuit 9
The above operation is basically realized by preset and reset control of the flip-flop circuit 22.

First, at least one of the synchronization code detection signal and the pseudo detection signal is supplied to the detection signal adjusting circuit 9.
When the signal is input to the OR circuit 24 shown in FIG. When the OR signal A and the prediction signal B are input to the AND circuit 25, the AND signal C from the AND circuit 25 is input to the preset terminal S of the flip-flop circuit 22.

Thus, when the prediction signal is H, the output of the flip-flop circuit 22 can be set to H by the earlier pulse of the input synchronization code detection signal and the pseudo detection signal. Thereafter, the flip-flop circuit 22 is reset by inputting the output signal D of the fall detection circuit 21 for detecting the fall of the prediction signal to the reset terminal R of the flip-flop circuit 22.

Then, the rise of the output signal E of the flip-flop circuit 22 is detected by the rise detection circuit 23, and the output signal F is output. As a result, the detection signal adjusting circuit 9 can output the earlier pulse of the pseudo detection signal pulse and the synchronization code detection signal pulse.

Next, a second embodiment of the synchronization signal according to the present invention will be described with reference to FIGS. FIG. 5 is a block diagram showing the configuration of the synchronization circuit. In the synchronization circuit of this embodiment, the counter circuit 5, register circuit 6, comparison circuit 7 and AND circuit 12 in the synchronization circuit of the second embodiment shown in FIG. 1 are replaced with the respective circuits shown in FIG. is there.

As shown in FIG. 5, these circuits include a prediction judgment circuit 30 as prediction judgment means for judging whether a prediction signal and a synchronization code detection signal match or not, and an OK signal from the prediction judgment circuit 30. An OK counter circuit 31 serving as first counting means for counting the number of times that the prediction signal matches the synchronization code detection signal by input of the pulse.
And an NG counter circuit 32 which is a second counting means for counting the number of consecutive times that the prediction signal and the synchronization code detection signal do not match due to the input of the NG pulse from the prediction determination circuit 30.

Further, there is provided a first register circuit 33 for holding a first predetermined value M based on a natural number as a register value, and the first predetermined value M in the first register circuit 33 can be arbitrarily set by a CPU (not shown). This is set, but here, for example, M = 2. Further, a second register circuit 34 for holding a second predetermined value N by a natural number as a register value
And a predetermined value N in the second register circuit 34.
Is also set arbitrarily by the CPU, but here N = 3 as an example.

Further, the synchronizing circuit includes a first comparing circuit 35 for comparing the count value of the OK counter circuit 31 with a set value (first predetermined value M) of the first register circuit 33,
A second comparison circuit 36 is provided for comparing the count value of the NG counter circuit 32 with the set value (second predetermined value N) of the second register circuit 34. The signals output from the first comparison circuit 35 and the second comparison circuit 36 are input to the prediction control circuit 8, respectively.

That is, in the synchronous circuit of this embodiment, the prediction control circuit 8, the OR circuit 13, and the AND circuit 11
Besides, the first register circuit 33, the second register circuit 34, the first comparison circuit 35, the second comparison circuit 36 and the like constitute a gate means.

Here, an example of the configuration and operation of the prediction determination circuit 30 in this synchronous circuit will be described with reference to FIGS. FIG. 6 is a block diagram showing a specific configuration example of the prediction determination circuit 30 in FIG. 5, and FIG. 7 is a timing chart for explaining its operation. The prediction determination circuit 30 is a circuit that detects the presence or absence of a pulse of the synchronization code detection signal while the prediction signal is at H for several clocks, and basically includes a counter circuit 41 and a comparison circuit 42. The circuit to use. Note that the pulse width of the prediction signal is x.

In FIG. 6, the synchronization code detection signal G is input to the reset terminal 41a of the counter circuit 41, and the prediction signal H is input to the enable terminal 41b. Further, the rise of the prediction signal H is detected by a rise detection circuit 4.
3 detects and inputs the pulse of the detection signal I to the load terminal 41c of the counter circuit 41.

As shown in FIG. 7, when the prediction signal H becomes H, "1" is loaded to the in terminal 41d of the counter circuit 41, and the counting operation starts. When the pulse of the synchronization code detection signal G is input to the reset terminal 41a during the counting operation, the counter circuit 41 is temporarily reset, and the count value becomes “0”. Thereafter, when the counting is continued and the prediction signal H becomes L, the counter circuit 41 sets x
A count value J of less than is output from the out terminal 41e and stopped.

On the other hand, when the pulse of the synchronization code detection signal G is not input to the reset terminal 41a, the counter circuit 41 is not reset on the way.
Outputs x as the count value J from the out terminal 41e and stops. When the comparison circuit 42 detects that the count value is less than x, the comparison circuit 42 outputs an OK pulse, which is a signal indicating that the prediction is successful, to the OK counter circuit 31 via the AND circuit 44. Is the prediction signal H
When it is detected that x is given in advance as the pulse width of, an NG pulse, which is a signal indicating that prediction has been lost, is output to the NG counter circuit 32 via the AND circuit 45.

The operation of the synchronization circuit shown in FIG. 5 will be described below based on the timing chart during operation shown in FIG. Here, the clock frequency of the output of the PLL circuit 1 and the clock frequency of the digital data series are temporarily shifted due to noise, signal abnormality on the digital data series, or the like, and the true synchronization code detection signal and the prediction signal are shifted. Explain the case when it comes off.

The operation sequence from the reset of the entire synchronizing circuit to the stable output of the synchronizing signal is the same as that of the first embodiment, but in this embodiment, when the prediction is successful. Then, the count value of the OK counter circuit 31 increases by "1" and stops when the count value reaches the maximum value.

The NG counter circuit 32 sets the count value to 0 when the prediction is successful in order to count only when the prediction is continuously missed. Specifically, the count value is set to “0” by resetting with an OK pulse from the prediction determination circuit 30. First, the synchronization circuit operates stably, and the synchronization code detection signal and the prediction signal match,
It is assumed that the NG counter circuit 32 is reset and outputs “0”, and the OK counter circuit 31 increases the count value by one or stops at the maximum value.

Thereafter, when noise or the like occurs, the prediction signal and the true synchronization code detection signal do not continuously match,
The count value of the NG counter circuit 32 increases to “3”. At this time, the second comparison circuit 36 determines that the NG counter circuit 3
A signal indicating that the count value of 2 has become equal to the register value of the second register circuit 34 is output to the prediction control circuit 8. Accordingly, the prediction control circuit 8 sets the prediction control signal to H
Therefore, the synchronization code detection signal passes through the AND circuit 11 as it is without using the prediction signal. At the same time, the prediction control circuit 8 resets the OK counter circuit 31 to set its count value to “0”.

Thereafter, the synchronization code detection signal is input to the prediction determination circuit 30. The operation is the same as that of the synchronization circuit of FIG. 1 and the prediction signal is output when the prediction is performed twice or more corresponding to the first predetermined value M. The synchronization code detection signal passes through the AND circuit 11 only at the time of input. In addition, the second
When the prediction is missed three times corresponding to the predetermined value N, the synchronization code detection signal passes through the AND circuit 11 without using the prediction signal again, and the synchronization operation is restarted. It does not continue malfunctioning when it is off.

[0045]

According to the first synchronization circuit of the present invention, even after a synchronization code is detected, a prediction signal is used after a predetermined number of detections of the next synchronization code have been predicted. Even if a fake synchronization code is detected, the synchronization code can be correctly detected without malfunctioning with a wrong prediction. In addition, if the number of times the prediction has been made can be set to an arbitrary natural number as the predetermined value M, the operation state of the synchronization circuit can be optimally adjusted according to the occurrence state of the data reading error.

The second synchronizing circuit according to the present invention, in addition to the same effect as described above, stops the synchronization when the prediction of the detection of the next synchronization code is continuously deviated by the second predetermined number of times or more, and performs the synchronization operation. Since the restart is performed, there is an effect that the synchronization code can be correctly detected without continuing the malfunction while the prediction is incorrect. Further, if the number of times the prediction is continuously deviated can be set to an arbitrary natural number as the second predetermined value N, the operation state of the synchronization circuit is optimally adjusted according to the occurrence state of the data reading error. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a synchronization circuit according to the present invention.

FIG. 2 is a timing chart of each signal when the synchronous circuit shown in FIG. 1 operates.

FIG. 3 is a block diagram illustrating a specific configuration example of a detection signal adjustment circuit 9 in FIG. 1;

4 is a timing chart of each signal when the detection signal adjustment circuit shown in FIG. 3 operates.

FIG. 5 is a block diagram showing a configuration of a second embodiment of the synchronization circuit according to the present invention.

6 is a block diagram illustrating a specific configuration example of a prediction determination circuit 30 in FIG.

7 is a timing chart of each signal when the prediction determination circuit shown in FIG. 6 operates.

8 is a timing chart of each signal when the synchronous circuit shown in FIG. 5 operates.

[Explanation of symbols]

 2: Synchronous code detection circuit 3: Pseudo detection signal output circuit 4: Prediction signal output circuit 5: Counter circuit 6: Register circuit 7: Comparison circuit 8: Prediction control circuit 9: Detection signal adjustment circuit 11: AND circuit 12: AND circuit 13: OR circuit 30: Prediction determination circuit 31: OK counter circuit 32: NG counter circuit 33: First register circuit 34: Second register circuit 35: First comparison circuit 36: Second comparison circuit

Claims (4)

[Claims] 1. A synchronization code detecting means for detecting a synchronization code from a digital data sequence constituted by a frame including a synchronization code as a unit and outputting a detection signal, and a detection signal output from the synchronization code detection means. A prediction signal output unit for predicting a time at which the next synchronization code is to be detected by the synchronization code detection unit, and outputting a prediction signal at the detection time, based on the output from the synchronization code detection unit. Pseudo detection signal output means for predicting a time at which the next synchronization code is to be detected by the synchronization code detection means based on the detected detection signal and outputting a pseudo pseudo detection signal at the time at which the next synchronization code is to be detected Counting means for counting the number of times the detection signal is output when the prediction signal is output; and a count value of the counting means is predetermined. If the count value is less than a predetermined value, the prediction signal is invalidated, and the detection signal is always passed.If the count value is equal to or more than the predetermined value, a gate unit that passes the detection signal only when the prediction signal is input, When there is a time difference between a detection signal and the pseudo detection signal, a detection signal adjusting means for outputting a signal out of these signals is provided. 2. The synchronization circuit according to claim 1, further comprising means for setting the predetermined value as an arbitrary natural number. 3. A synchronizing code detecting means for detecting a synchronizing code from a digital data string constituted by a frame including a synchronizing code as a unit and outputting a detection signal, and a detecting signal output from the synchronizing code detecting means. Prediction signal output means for predicting the time at which the next synchronization code is to be detected by the synchronization code detection means, and outputting a prediction signal at the time to be detected, and output from the synchronization code detection means. Pseudo detection signal output means for predicting a time at which the next synchronization code should be detected by the synchronization code detection means based on the detection signal, and outputting a pseudo pseudo detection signal at the detection time. A prediction determining means for determining whether or not the detection signal is output when the prediction signal is being output, based on a signal from the prediction determining means, First counting means for counting the number of times the detection signal is output when the detection signal is output, and the detection signal is output when the prediction signal is output based on a signal from the prediction determination means. A second counting means for counting the number of consecutive times that there was no; if the count value of the first counting means is less than a first predetermined value, the prediction signal is invalidated and the detection signal is constantly If the count value is equal to or more than the first predetermined value M, the detection signal is passed only when the prediction signal is input, and the count value of the second counting means is set to a predetermined second value. When the value becomes equal to or more than a predetermined value, the prediction signal is invalidated, the detection signal is always passed, and the count value of the first counting means is set to 0.
And a detection signal adjusting means for outputting a previous signal of the detection signal and the pseudo detection signal when there is a time difference between the detection signal and the pseudo detection signal. circuit. 4. The synchronization circuit according to claim 3, further comprising means for setting each of said first predetermined value and said second predetermined value as an arbitrary natural number.