JPH04245734A - Synchronizing circuit - Google Patents

Abstract

PURPOSE:To offer a synchronizing circuit capable of shortening a synchronism establishing time without starting synchronism establishing operation from a forward protecting state at the time of turning on a power supply for a device, in a synchronizing circuit for synchronizing receiving data. CONSTITUTION:The synchronizing circuit for generating an internal synchronizing pattern by a synchronizing pattern generation part 6, detecting coincidence between the internal synchronizing pattern with a synchronizing pattern included in receiving data by a synchronizing pattern coincidence detecting part 2, deciding step-out by the continuous detection of the prescribed number of times of discrepancy by a synchronous protection part 3, allowing a synchronizing pattern generation part 6 to execute hunting for shifting the timing of the internal synchronizing pattern, and deciding the establishment of synchronism with the receiving data based upon the continuous detection of the prescribed number of times of coincidence is provided with a set signal generation part 7 to forcedly set up the protection part 3 to a step-out deciding state at the time of inputting a power ON signal indicating the ON of the power supply for the device.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization circuit in an information transmission system, and more particularly to a synchronization circuit that establishes synchronization by recognizing the position of synchronization data in a received signal using an internally created synchronization pattern.

[0002] A receiving section of an information transmission destination in an information transmission system synchronizes the received information with a synchronization signal in order to determine what type of information was sent from where. The locations that must be synchronized vary depending on the system, but are generally scattered throughout the system, from the transmission section to the exchange section and terminals.

[0003] In such a case, the synchronization circuit that performs the process of establishing synchronization should not perform unnecessary operations to establish synchronization even when the power is turned on, and the time required to establish synchronization should be short. is requested.

0004

2. Description of the Related Art FIG. 4 is a block diagram showing an example of the configuration of a conventional synchronization circuit, in which 1 is a synchronization counter that generates a signal indicating the position of an internal frame bit, and 2 is a synchronization counter that detects matching of synchronization patterns. synchronization pattern matching detection unit, 3
Reference numeral 4 designates a synchronization protection unit that performs a synchronization protection operation, 4 and 5 gate circuits, and 6 a synchronization pattern creation unit that creates an internal synchronization pattern.

FIG. 5 is a time chart showing the operation of a conventional synchronization circuit, in which ■ indicates the output signal of the synchronization counter 1 in the circuit of FIG. 4, ■ indicates the output signal of the synchronization pattern matching detector 2, 2 indicates the output signal of the synchronization protection section 3, 2 indicates the output signal of the gate circuit 4, and 2 indicates the output signal of the gate circuit 5, respectively.

[0006] The synchronous counter 1 outputs a signal (2) indicating the frame bit position F by counting clocks. The synchronization pattern creation section 6 creates synchronization data consisting of a fixed pattern in synchronization with the signal (2). The synchronization pattern matching detection unit 2 detects synchronization data in externally input data according to the frame bit position F,
Compare with the synchronization data created by the synchronization pattern creation unit 6, and when they match, a signal indicating a match (indicated by a circle)
is generated, and when there is a mismatch, a signal indicating mismatch (indicated by ×)
occurs.

[0007] The synchronization protection unit 3 determines whether synchronization is achieved or not, and in order to prevent malfunctions due to data errors or deterioration of the transmission path, the synchronization protection unit 3 determines whether or not synchronization is achieved. to determine whether synchronization is achieved or out of synchronization. When out of synchronization occurs from a synchronized state, forward protection is performed, and an output indicating that out of synchronization has been determined is generated by continuously detecting mismatches a predetermined number of times, and at the same time, the backward protection state is entered. Further, when changing from an unsynchronized state to a synchronized state, backward protection is performed, synchronization restoration is determined by successive detection of coincidence a predetermined number of times, and at the same time, the forward protection state is entered. The output signal ■ of the synchronization protection section 3 is at a high level in the forward protection state, and is at a low level in the backward protection state.

When the synchronous circuit is in the forward protection state, the output signal (2) of the gate circuit 4 is at a low level, and therefore the clock is inputted from the gate circuit 5 to the synchronous counter 1 as is. When the synchronization pattern detection section 2 consecutively counts a predetermined number of mismatches as shown by A in FIG. Becomes protected. When the synchronization pattern match detection unit 2 detects a mismatch in this state, the gate circuit 4 generates a high-level output signal ■, which inhibits the clock input to the synchronization counter 1. Output signal■
The frame bit position F in is shifted. In this way, the comparison position in the synchronization pattern match detection section 2 gradually changes, and when a match is detected a predetermined number of times in succession, synchronization is achieved as shown in B. In FIG. 5, arrows indicate that hunting has been performed to change the frame bit position.

[0009]

[Problems to be Solved by the Invention] When the power to operate the device is turned on, the internal state of the circuit is uncertain. Therefore, it is possible for the device to start in a synchronized state, but in such cases with conventional synchronization circuits, the synchronization protection section first enters the forward protection state, and then once the synchronization is lost and the backward protection is detected by detecting a mismatch. In some cases, synchronization is established through a process in which the synchronization state is established, and then the synchronization state is restored upon detection of a match. Therefore, there is a problem in that it takes a long time to establish synchronization, and incorrect data processing is performed during that time.

[0010] The present invention aims to solve the problems of the prior art as described above, and when the power of a device having a synchronous circuit is turned on, the synchronization establishment operation does not start from the forward protection state. The object is to provide a synchronization circuit that can shorten the establishment time.

[0011]

[Means for Solving the Problems] The present invention provides a synchronization pattern creation section that creates internal synchronization data, and a synchronization pattern match detection section that detects a match between this internal synchronization data and synchronization data in received data. Then, by detecting a predetermined number of consecutive mismatches, it is determined that the synchronization is out of synchronization, and the synchronization pattern creation unit performs hunting to shift the timing of the internal synchronization data, and by continuously detecting a predetermined number of matches, it is possible to synchronize with the received data. The synchronization circuit includes a synchronization protection section that determines whether the synchronization is established, and is characterized in that it includes a setting signal generation section that forcibly sets the synchronization protection section to an out-of-synchronization determination state when the device is powered on.

0012

[Operation] FIG. 1 shows the basic structure of the present invention. In the synchronization circuit, a synchronization pattern creation section 6 creates internal synchronization data, and a synchronization pattern match detection section 2 detects whether or not this internal synchronization data matches the synchronization data in the received data. The synchronization protection section 3 determines out-of-synchronization by continuously detecting a predetermined number of mismatches in the synchronization pattern matching detection section 2, and causes the synchronization pattern creation section 6 to perform hunting to shift the timing of internal synchronization data. As a result, when the internal synchronization data matches the synchronization data in the received data, synchronization with the received data is established by consecutively detecting the match a predetermined number of times.

In such a synchronization circuit, a setting signal generation section 7 is provided to forcibly set the synchronization protection section 3 to an out-of-synchronization determination state when the device is powered on. Therefore, according to the present invention, when the power of the device is turned on, the synchronization circuit does not start operating from the forward protection state and can immediately enter the backward protection state and start hunting operation, so the synchronization establishment time is shortened. Ru.

[0014]

[Embodiment] FIG. 2 shows an embodiment of the present invention, in which the same parts as in FIG. This is the creation department.

FIG. 3 is a time chart showing the operation of the synchronous circuit of the present invention.
is the same as in FIG. 5, and ■ indicates the output signal of the setting signal generation section 7.

When the device is powered on, a power supply voltage signal (power-on signal) is input to the setting signal generator 7. The setting signal generation section 7 sets the output signal (2) to a high level in response to the input of the power-on signal. The synchronization protection unit 3 is forcibly set to an out-of-synchronization state when the signal ■ becomes high level, and when the power supply rises to a normal voltage level, it enters the backward protection state as shown by C in FIG. Start hunting. And synchronization pattern matching detection section 2
By shifting the frame bit position F every time a mismatch is detected, the synchronization data input from the outside and the synchronization data created by the synchronization pattern creation section 6 gradually become consistent, When a match is detected a certain number of times in succession, the output signal (2) from the synchronization protection section 3 becomes high level, as shown by D, and the synchronization is restored.

Therefore, in the synchronous circuit of the present invention, even if a match is detected in the synchronous pattern match detecting section 2 when the power is turned on, it does not enter the forward protection state but immediately enters the backward protection state and performs the hunting operation. Therefore, the synchronization establishment time can be shortened compared to conventional synchronization circuits.

[0018]

As explained above, according to the synchronization circuit of the present invention, the synchronization circuit does not start synchronization operation from the forward protection state when the device is powered on, and the synchronization establishment time is shortened.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a time chart showing the operation of the synchronous circuit of the present invention.

FIG. 4 is a block diagram showing a configuration example of a conventional synchronous circuit.

FIG. 5 is a time chart showing the operation of a conventional synchronous circuit.

[Explanation of symbols]

2 Synchronization pattern match detection section 3 Synchronization protection section 6. Synchronization pattern creation section 7 Setting signal creation section

Claims (1)

[Claims] 1. A synchronization pattern creation unit (6) that creates an internal synchronization pattern, a synchronization pattern matching detection unit (2) that detects a match between the internal synchronization pattern and a synchronization pattern in received data, and Out-of-synchronization is determined by successive detections of mismatches, and the synchronization pattern creation unit (6) is caused to perform hunting to shift the timing of the internal synchronization pattern, and synchronization with the received data is established by continuously detecting matches a predetermined number of times. Synchronous protection unit to judge (
3), the synchronous circuit includes a setting signal generator (7) that forcibly sets the synchronization protection unit (3) to an out-of-synchronization determination state when a power-on signal indicating power-on of the device is input. Characteristic synchronous circuit.