JPH08125649A - Frame synchronization detection system - Google Patents

Abstract

PURPOSE: To reduce a time till received data establishes correct frame synchronization by allowing the received data to be quickly escaped from the synchronization with a pseudo pattern. CONSTITUTION: The system is provided with a synchronization pattern comparison section (a) detecting a frame synchronization pattern, a count section (b) whose operation is started at detection time t0 of a first pattern to count a time T for a prescribed period, a memory section (c) storing a position t1 of the frame synchronization pattern detected on the way of count, and a synchronization establishment discrimination section (d) detecting a synchronization pattern for a prescribed number of times for each prescribed time T to discriminate frame synchronization. When the synchronization pattern comparison section (a) recognizes pseudo synchronization because a synchronization detected at a time t1 at first from the received data cannot be detected at a time t0' after the prescribed period T, frame synchronization is established by using a time position t1 of the synchronization pattern of the memory section (c).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention does not have a special timing signal for frame synchronization of data transmission, and periodically inserts a specific pattern of code 1/0 into transmission data to establish frame synchronization. The present invention relates to a frame synchronization detection method for data transmission of a synchronization pattern insertion type for transmission.

With the recent increase in speed of communication networks,
A large number of data can be time-division multiplexed and transmitted on one transmission line. In order to synchronize the frame of the received data on the receiving side of the transmission line when the specific pattern for frame synchronization is inserted (time division multiplexed) in the transmitted data and transmitted. When detecting a synchronization pattern that is transmitted periodically, even if a pseudo pattern is temporarily detected, the correct synchronization pattern is quickly detected a predetermined number of times to quickly establish frame synchronization of transmission data. Required to do so.

[0003]

2. Description of the Related Art A conventional frame synchronization detection method is performed according to the following procedure, although not particularly shown. That is, a specific pattern of code 1/0 for frame synchronization is detected from the received data. When the specific pattern is detected, the counter starts counting the clock and a certain period of one cycle of transmission data
The T is counted, and it is checked at every fixed time T whether or not the specific pattern for frame synchronization is detected. However, the specific pattern for frame synchronization is not detected during the time T 1 of the one cycle. It is assumed that the frame synchronization of the received data is established when the specific pattern for synchronization is continuously detected a predetermined number of times. The number of times of continuous detection is determined by each data transmission device. When the above-mentioned specific pattern for synchronization is not detected a predetermined number of times in succession, the above detection operation is repeated.

[0004]

In the above-mentioned conventional frame synchronization detection method, when a specific pattern for synchronization is once detected from the received data, the received data is not received until after a certain period T of one cycle. Does not check whether or not the frame is synchronized. If the check result of the frame synchronization after the time T of one cycle is not the correct frame synchronization but the pseudo synchronization, the detection is started again from the detection of the specific pattern for the synchronization, which is correct. It takes a considerable amount of time to establish frame synchronization. An object of the present invention is to provide a frame synchronization detection method in which, when received data is pseudo-synchronized, it is possible to quickly get out of the pseudo-synchronization, detect a specific pattern for correct frame synchronization and establish the synchronization. Is to realize.

[0005]

The basic configuration of the present invention for achieving this object is as follows. (1) Timing diagram and (2) Basic configuration diagram of specific pattern detection for explaining the principle of the present invention in FIG. And the sync pattern comparison unit (a) refers to
Even when a pseudo pattern that is not a specific pattern for frame synchronization is detected for the first time, at the time of detection t0, the counting unit (b) that counts clocks starts counting operation,
When the counting unit (b) that started the counting operation detects a specific pattern for frame synchronization at an arbitrary time t1 in the middle of counting the constant time T of one cycle of transmission data, Holds the time position t1 at the time of detection of the specific pattern in the memory unit (c), and the specific pattern is repeatedly detected at t2 and t3 after a fixed period of time T from the detection position t1. Check whether the synchronization is established or not (d)
1), the frame synchronization detection circuit (2) of FIG. 1 is configured.

[0006]

Operation: Referring to (1) Timing diagram and (2) Basic configuration diagram of FIG.
Consider the case where the frame synchronization of the received data is established when a predetermined specific pattern is detected by comparison in succession. At the first time t0, the synchronization pattern comparison unit
(a) compares the received data with a predetermined specific pattern,
Assume that a pseudo sync pattern is detected from the received data. In the configuration of the conventional example, at time t0 ', which is a period T after one cycle from this time t0, it is not detected again by comparison with the specific pattern, and it is recognized that it is pseudo synchronization. Then, the subsequent time t2, the time t3 after the constant time T of the cycle from the time t2, and the time t4 after the constant time T after three more consecutive detection of the synchronization pattern, the frame synchronization is performed. However, in the configuration of the present invention, the count unit (b) starts counting the period time T 1 at time t0 when the pseudo synchronization pattern is detected. Even during this counting, the synchronization pattern comparison unit
(a) continues the detection operation, and when the synchronization pattern is detected at time t1, the detected time t1 is stored in the memory section (c). Then, at time t0 ′ after a certain time T from time t0,
When the synchronization establishment determining unit (d) determines that the first synchronization is the pseudo synchronization, the time t2 after one cycle time T from the next time t1
Then, compare again. Then, at time t3, comparison is made, and time t
If the synchronization pattern is detected three times consecutively at 1, t2 and t3, the synchronization is established. Therefore, in the configuration of the present invention, frame synchronization is established earlier than the conventional example by the fixed time T 1 of one cycle.

According to claim 2 of the present invention, another memory part (e) is provided in place of the memory part (c) of claim 1 and is provided in parallel with the first counting part (b) from time t1. And start counting. As a result, similarly to the above, if the synchronization pattern is detected three times consecutively at times t1, t2, and t3, the synchronization is established. Therefore, similarly to the first aspect, the frame synchronization is established earlier than the conventional example by the fixed time T 1 of one cycle.

In the present invention, as described above, when the sync pattern comparison unit (a) first detects a pattern, it is unknown at t0 whether it is pseudo sync or regular frame sync. At the time of detection t0, the counting unit (b) starts counting, performs comparison detection of the synchronization pattern and holds the detection time even during the counting of the constant time of the cycle T, and
If the synchronization pattern is not detected at t0 'and it is recognized that it is pseudo synchronization, it is discontinued at that time t0', so repeated detection of pseudo synchronization is avoided several times, and the frame synchronization is early. Will be able to be established.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows the structure of a frame synchronization detecting circuit of an embodiment corresponding to claim 1. First, the data receiving unit 10 receives input data. However, when the input data is serial serial format, the received data of the serial format is converted into parallel format received data of the parallel number equal to the number of bits of the synchronization pattern. The synchronization pattern comparison unit (a) compares the parallel-type reception data with a predetermined synchronization pattern, and detects a synchronization pattern from the reception data. At the time t0 when the first sync pattern is detected, the counting section (b)
Enters a count of a fixed time T of the cycle of the synchronization pattern. Arbitrary time t1 during the counting of this counting part (b)
When one more synchronization pattern is detected, the count value t1 of the detection time is stored in the memory unit (c). The synchronization establishment determination unit (d) determines whether the synchronization pattern detected by the synchronization pattern comparison unit (a) at the first time point t0 is pseudo synchronization. If the sync pattern is detected again after the fixed time T of one cycle, it is determined that the sync pattern is not the pseudo sync but the correct sync pattern. When the synchronization establishment determination unit (d) determines that the synchronization pattern detected at the first time point t0 is pseudo synchronization, the count value t1 stored in the memory unit (c) is used as the time reference. As a result, a comparison is made at times t2 and t3 after a fixed time T, and it is determined whether or not it is a frame synchronization pattern. When it is determined by the synchronization establishment determination unit (d) that the frame synchronization has been established, the display signal indicating the synchronization establishment state, the synchronization timing signal from the synchronization timing signal generation unit 20, and the data reception unit 10 The received data and the received data are output to another block (not shown), and necessary data processing is performed there.

FIG. 3 shows the configuration of a frame synchronization detection circuit of an embodiment corresponding to claim 2. In FIG. 3, a second counting unit (e) is provided instead of the memory unit (c) of FIG. The operations (1) to (3) of this embodiment are the same as those of the above-mentioned claim 1. Arbitrary time t1 in the middle of counting by the first counting unit (b)
In the case where one more synchronization pattern is detected, the second counting unit (e) starts counting from the count value t1 of the detection time and counts the period T of the synchronization pattern for a certain period of time. enter. The synchronization establishment determination unit (d) first determines whether the synchronization at t0 is pseudo synchronization. When the synchronization establishment determination unit (d) first determines that the synchronization at t0 is the pseudo synchronization, the second counting unit (e) counts one cycle T for a fixed time to determine whether the synchronization pattern is a synchronization pattern. Determine whether or not. Further, when the correct synchronization pattern is detected at any time t1 between these times, the first counting section (b) enters the count of the time T 1 of the cycle of the synchronization pattern. By repeating the operations 1 to 3, the first counting unit (b) and the second counting unit (e) count the period T 1 of the synchronization pattern in parallel and detect the synchronization pattern. When the synchronization establishment determination unit (d) determines that the synchronization is established, the display signal indicating the synchronization establishment state, the synchronization timing signal from the synchronization timing signal generation unit 20, and the reception data from the data reception unit 10 Are output to another block (not shown), and necessary data processing is performed there.

FIG. 4 shows the structure of a frame synchronization detection circuit of an embodiment corresponding to claim 3. In the configuration of FIG.
It has only a plurality of memory units (c) in parallel. The operations (1) to (4) are the same as those in the above-mentioned claim 1. At any time t1 during the counting of the counting section (b),
When one synchronization pattern is detected, the count value t1 is stored in the memory unit (C). The synchronization establishment determination unit (d) determines whether the initial synchronization is pseudo synchronization. Further, if a synchronization pattern is detected at time t2 between these times, the count value t2 is stored in the next memory unit (C). In this way, the detection positions t1 to tn of the synchronization pattern are stored by the number n of the memory section (C). The synchronization establishment determination unit (d) sequentially determines whether or not pseudo synchronization is performed from the first synchronization. When it is determined that the detection position of the synchronization pattern stored in a certain memory unit (C) is pseudo synchronization, the operation of detecting a new synchronization pattern is started again. (10) When the synchronization establishment determination unit (d) determines that synchronization has been established, the display signal indicating the synchronization establishment state, the synchronization timing signal from the synchronization timing signal generation unit 20, and the data reception unit 10 The received data from is output to another block (not shown), and necessary data processing is performed there.

FIG. 5 shows the structure of a frame synchronization detection circuit of an embodiment corresponding to claim 4. In the configuration of FIG.
Only a plurality of the second counting units (e) are provided in parallel. The operations (1) to (4) are the same as those in the above-mentioned claim 1. When one more synchronization pattern is detected during counting by the first counting unit (b), the next counting unit (b) counts the period T 1 of the synchronization pattern. The synchronization establishment determination unit (d) determines whether the initial synchronization is pseudo synchronization. Further during this time, if a sync pattern is detected,
The following counting unit (e) counts the period T of the synchronization pattern. In this way, the detection positions of the synchronization pattern are counted by the number of the counting units (e). The synchronization establishment determining unit (d) sequentially determines from the first synchronization whether or not it is pseudo synchronization. Certain counting section
When it is determined that the cycle of the synchronization pattern counted by (e) is pseudo synchronization, the detection operation of a new synchronization pattern is started again. (10) When the synchronization establishment determination unit (d) determines that synchronization has been established, the display signal indicating the synchronization establishment state, the synchronization timing signal from the synchronization timing signal generation unit 20, and the data reception unit 10 The received data from is output to another block (not shown), and necessary data processing is performed there.

[0013]

As described above, according to the present invention, the next sync pattern is detected and the detection time is held even while counting the time of the cycle of the sync pattern detected first from the received data. Therefore, if the first detected sync pattern is found to be pseudo sync after a certain period of time, it is possible to avoid discontinuing the pseudo sync detection at that time and to establish correct frame sync early. The effect that can be obtained is obtained.

[Brief description of drawings]

FIG. 1 is a principle diagram showing a specific pattern detection timing and its basic configuration in a frame synchronization detection method of the present invention.

FIG. 2 is a circuit configuration diagram of an embodiment corresponding to claim 1 of the present invention.

FIG. 3 is a circuit configuration diagram of an embodiment corresponding to claim 2 of the present invention.

FIG. 4 is a circuit configuration diagram of an embodiment corresponding to claim 3 of the present invention.

FIG. 5 is a circuit configuration diagram of an embodiment corresponding to claim 4 of the present invention.

[Explanation of symbols]

(a) is a sync pattern comparison part, (b) and (e) are count parts,
(c) is a memory unit, (d) is a synchronization establishment determining unit, 10 is a data receiving unit, and 20 is a synchronization timing signal generating unit.

Claims (4)

[Claims] 1. A frame for periodically inserting a specific pattern of code 1/0 into transmission data to form a frame synchronization pattern, and detecting the synchronization pattern a predetermined number of times from reception data of data transmission to establish frame synchronization of the reception data. In the sync detection method, a sync pattern comparison unit (a) that detects a frame sync pattern from the received data, and a count that starts the operation at the first pattern detection (t0) and counts the time (T) of a fixed cycle. Part (b), a memory part (c) that stores the position (t1) of the frame synchronization pattern detected in the middle of the count, and the fixed time (t1) based on the detection position (t1) of the synchronization pattern ( T) includes a synchronization establishment determination unit (d) that determines that the frame synchronization of the received data has been established by detecting the synchronization pattern a fixed number of times, and the synchronization pattern comparison unit (a) Or When the sync pattern detected at the beginning (t0) is not detected after a certain period (T) (t0 ') and is recognized as pseudo sync, the sync pattern stored in the memory section (c) is detected. A frame synchronization detection method characterized by establishing frame synchronization of received data using position (t1). 2. A cycle (T) of a pattern detected at first (t0) by the synchronization pattern comparison section (a), comprising a second counting section (e) instead of the memory section (c). While the first counting unit (b) is counting, when the synchronization pattern is detected (t1), the second counting unit (e) starts counting for the fixed period (T). Then, the synchronization pattern comparison unit (a)
When it is found that the synchronization detected at the first time (t0) is pseudo synchronization, the pattern is detected immediately at the count start time (t1) of the second counting section (e) and at a constant period (T). Position (t2, t
3. The frame synchronization detection method according to claim 1, wherein the frame synchronization of the received data is established by 3). 3. A plurality of n memory units (c) are provided in parallel, and the synchronization pattern comparison unit (a) detects the count unit (b) while counting a certain time (T). The frame synchronization detection method according to claim 1, wherein the time positions (t1 to tn) of a plurality of n synchronization patterns are held to establish the frame synchronization of the received data. 4. A plurality of n second counting units (e) are provided in parallel, and a first counting unit (b) is provided when a synchronization pattern comparing unit (a) first detects a synchronization pattern (t0). Starts counting, and then the second counting units (e) of the multiple n start counting in parallel at the time positions (t1 to tn) of the multiple synchronization patterns that are subsequently detected. 3. The frame synchronization detecting method according to claim 2, wherein the frame synchronization is detected and the synchronization is established.