JP3265423B2 - Transmission delay time measuring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for measuring a transmission delay time of a communication network without being affected by errors caused by the communication network.

[0002]

2. Description of the Related Art One of the evaluations of a communication network is a time required for transmitting a data signal, that is, a transmission delay time.

When measuring the transmission delay time, it is desirable that the measurement can be performed under conditions close to the actual line use state and only on one line side.

[0004] For this reason, conventionally, a line to be measured is previously set in a loopback mode, a fixed pattern error is added to a continuous signal of a predetermined pattern with a short bit length and output to a communication network. An error is detected by comparing the signal folded back from the signal pattern before the error is added, and the error of the fixed pattern is returned after the added error is output to the communication network. Is measured to determine the transmission delay time.

However, since the transmission delay time varies depending on the state of the communication line network, the operation of adding the next error each time a fixed pattern error returns is repeated a predetermined number of times. The time is obtained a plurality of times, and this is continuously displayed on a display or the like, or the communication network is evaluated based on the result of statistical processing.

[0006]

However, in the above-mentioned conventional measuring method, if an error having the same pattern as that of the error to be added is added in the communication network, all subsequent measurements will be erroneous. There was a problem that would.

That is, as shown in FIG. 3A, an error E of a fixed pattern added between a certain time t0 and a certain time t1 is output to the communication line network. When the signal is normally folded back as shown in FIG. 3 (b), this time T1 is correctly measured as the transmission delay time as shown in FIG. 3 (c).

However, the error E added between the time t2 and the time t3 is different from the error t added before the time t6 when the return is made.
At 4 o'clock, when an error E 'having the same pattern as that of the error E is output to the line by the communication network, this error E' has the same pattern as the error E added immediately before it, and as shown in FIG. In addition, the time T2 'from t3 to t4, which is shorter than the correct transmission delay T2 from t3 to t6, is measured as the transmission delay.

Further, since the next error E is added between the time t4 and the time t5, the error E added before the time t6 before the time t8 at which the error E is looped is looped back. The time T3 'from t5 to t6, which is shorter than the correct transmission delay T3 from t5 to t8, is measured as the transmission delay, and this erroneous measurement continues thereafter.

Therefore, it is not possible to correctly evaluate the communication network from the transmission delay time obtained by such measurement.

It is an object of the present invention to provide a transmission delay time measuring apparatus which can solve the above problem and greatly suppress the influence of an error added by a communication network.

[0012]

In order to achieve the above object, a transmission delay time measuring apparatus of the present invention provides a pattern signal generating means (21) for outputting a signal of a predetermined pattern to a communication network (1) in a loopback mode. ), An error pattern generation means (22) capable of selectively outputting a plurality of different error patterns, and the error signal being output from the pattern signal generation means to the communication network every time an error addition instruction is received. Error adding means (23) for adding an error of the error pattern output from the pattern generating means, and comparing the pattern of the signal looped back from the communication network with the pattern of the signal output by the pattern signal generating means. An error detecting means (24) for detecting an error and an error pattern detected by the error detecting means are provided by the error adding means. An error pattern determining unit (25) for instructing the error adding unit to add an error each time the error pattern matches, and determining whether the error added by the error adding unit matches the error pattern. A timer means (26) for measuring a time from output to the communication network until a match of an error pattern is determined by the error pattern determination means as a transmission delay time, and an output from the error pattern generation means. An error pattern switching means (29) for switching an error pattern at every predetermined timing is provided, and the transmission delay time is measured while switching an error pattern to be added to a different pattern at every predetermined timing.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a transmission delay time measuring device 20 according to an embodiment of the present invention. In FIG. 1, a pattern signal generating means 21 continuously outputs a signal of a predetermined pattern to an uplink 2a of the communication network 1 set to a loopback mode via an output terminal 20a.

Here, the signal generated by the pattern signal generating means 21 is set so as to satisfy conditions close to actual use conditions.
For example, a signal sequence of a pseudo-random pattern is used. This pseudo-random pattern signal is not only a signal generated and output in real time by feeding back the exclusive OR of the output of the predetermined stage and the output of the final stage of the shift register connected in series to the first stage, and May be read from a pseudo-random pattern stored in a memory in advance.

The error pattern generating means 22 selectively outputs an error pattern designated by an error pattern switching means 29 described later from a plurality of different error patterns. Assuming that the error pattern is “1” for the error bit and “0” for the no error bit, for example,
A pattern having consecutive errors of different bit lengths, such as a pattern "11" having two consecutive bits and a pattern "111" having three consecutive errors, or a pattern "10101" having three consecutive errors every other bit Any pattern including a pattern in which a discontinuous error is repeated a plurality of times, such as a pattern “11011011” in which a 2-bit error is repeated three times with an interval of one bit (the pattern length is determined by the communication network In order to make it less susceptible to 1-bit errors that occur most frequently in 1s, 2 bits or more are desirable).
Here, the error pattern generating means 22 can generate 2
Pe (1) to Pe
(N).

The error adding means 23 outputs the signal output from the pattern signal generating means 21 to the upstream line 2a as it is until a measurement start signal S is input from an operation unit (not shown) or an external device or the like. Immediately after the start signal S is input, and every time an error pattern determination unit 25, which will be described later, determines that an error pattern matches, a signal output from the pattern signal generation unit 21 is output from the error pattern generation unit 22. Error pattern P
The error e is added and output to the uplink 2a. The error adding means 23 outputs the pattern signal generating means 21 at the timing when the error pattern Pe is “0” (no error).
Is output as it is to the uplink 2a, and at the timing when the error pattern Pe is "1" (with an error), the signal output from the pattern signal generator 21 is inverted and output to the uplink 2a.

The error detecting means 24 receives, via the input terminal 20b, a signal which has been returned to the down line 2b paired with the up line 2a by the communication line network 1, and receives the same signal as the signal output by the pattern signal generating means 21. An error is detected by comparing with a reference signal of the pattern.

The error detecting means 24 internally has a signal generating section for generating a reference signal having the same pattern as the signal output from the pattern signal generating means 21.
3 establishes synchronization between the signal looped back from the communication network 1 and the reference signal during the measurement preparation state in which no error is added, and during the measurement period, the signal generator automatically generates the reference signal. The signal and the signal looped back from the communication network 1 are compared in bit units. For example, a signal that is "0" when they match (no error) and "1" when they do not match (error) is output. .

The error pattern determining means 25 determines whether the error pattern detected by the error detecting means 24 matches the error pattern added by the error adding means 23, and determines whether the error pattern matches. Every time it is determined, the error adding means 23 is instructed to add an error.

The time counting means 26 measures the time from when the error added by the error adding means 23 is output to the uplink line 2a until the error pattern determining means 25 determines that the error pattern matches, as a transmission delay time. .
Note that the time counting means 26 keeps the time from when the error added by the error adding means 23 is output to the uplink 2a until a certain time (set in advance to several times the expected normal transmission delay time) elapses. Error pattern determining means 25
If no error pattern match is determined, the error pattern switching unit 29 is instructed to switch the error pattern, and the error adding unit 2
3 is instructed to add an error.

The statistical processing means 27 performs statistical processing on the transmission delay time measured by the timer means 26, for example, an average value, a variance, a maximum value, a minimum value, and the like.

The display device 28 displays the transmission delay time measured by the clock unit 26, the calculation result of the statistical processing unit 27, and the like.

The error pattern switching means 29 outputs the error pattern generating means 22 at every predetermined timing and each time an instruction to switch the error pattern is received from the timing means 26.
Switches the output error pattern to a different pattern.

As will be apparent from the following description of the operation, in order to minimize the effect of an error added in the communication network 1, the switching of the error pattern by the error pattern switching means 29 is performed by the error pattern determining means. It is desirable to perform this every time the coincidence of the error patterns is determined in 25.

However, the present invention is not limited to this. For example, each time the error pattern determination means 25 determines that the error pattern matches a plurality of times (preferably less), the error pattern is switched.
Irrespective of the determination of the match, even if the error pattern is switched at regular time intervals, there is an effect of reducing the influence of the error added in the communication network 1.

In the following description, the error pattern switching means 29 switches the error pattern output from the error pattern generation means 22 to a different pattern each time the error pattern determination means 25 determines that the error pattern matches. Shall be.

Next, the operation of the above embodiment will be described. The signal output from the pattern signal generating means 21 is output as it is to the upstream line 2a of the communication line network 1 previously set to the loopback mode without adding an error, and is returned from the communication line network 1 to the downstream line 2b. The reference signal of the error detection means 24 is synchronized with the incoming signal.

The error pattern switching means 29 switches the error pattern output from the error pattern generation means 22 in order from Pe (1) to Pe (N), for example, sequentially and cyclically.

Here, as shown in FIG. 2A, when the measurement start signal S is inputted at t0 in a state where the error pattern generating means 22 is outputting the error pattern Pe (1), FIG. As shown in FIG. 2 (b), the error adding means 23 generates an error E corresponding to the error pattern Pe (1).
1 is added from t0 to t1 and output to the uplink 2a.

If there is no abnormality in the communication network 1, this error E1 is returned to normal at t2, which is T1 time after t1 as shown in FIG. 2C, and detected by the error detecting means 24. The error pattern determination unit 25 determines whether the error patterns match.

For this reason, as shown in FIG. 2D, the T1 time is correctly measured as the first transmission delay time by the timer 26.

At time t2 when the error pattern determination unit 25 determines that the error patterns match, as shown in FIG. 2A, the error pattern output by the error pattern generation unit 22 by the error pattern switching unit 29 is Pe as shown in FIG. Switching from (1) to Pe (2), an error E2 corresponding to this error pattern Pe (2) is added between t2 and t3, and output to the uplink 2a.

This error E2 indicates that, if there is no abnormality in the communication network 1, when the time T2 elapses from the time t2, the downlink 2
b, an error occurs in the communication network 1 and at time t4, an error E is generated by the communication network 1.
2 is output to the downlink 2b, the error pattern determination means 25 outputs the error E2 '.
It is determined that 2 ′ is a return of the error E2 added at the previous time point t3.

For this reason, as shown in FIG. 2 (d), the time delay means 26, which is shorter than the correct transmission delay time T2,
An erroneous time T2 'from t3 to t4 is measured as the second transmission delay time.

At time t4, the error pattern output from the error pattern generation means 22 changes from Pe (2) to P
e (3), and the error pattern Pe (3)
Is added between t4 and t5 and output to the uplink 2a.

The error E2 is looped back until t6 at which the error E3 is looped back in the communication network 1. At this time, the error pattern output from the error pattern generating means 22 is Pe (3 ) And the error E
2 is different from the error pattern Pe (2).

Therefore, the error pattern judging means 25 judges that the error patterns do not match, and this error E2 is ignored.

When the error E3 is looped back at t6, the error pattern determining means 25 determines the coincidence of the error patterns.

For this reason, as shown in FIG. 2D, the time T3 from the time t5 to the time t6 is set to 3 by the time counting means 26.
It is correctly measured as the second transmission delay time.

Further, the error E4 of the error pattern Pe (4) different from the error E3 between the time t6 and the time t7.
Is output to the uplink 2a, and from time t7, T4
At time t8 after the time, the signal is looped back to the downlink 2b to determine the coincidence of the error pattern, and the T4 time is correctly measured as the fourth transmission delay time.

Thereafter, as long as the error pattern generated by the communication network 1 does not match the error pattern generated by the error pattern generating means 22, the transmission delay time will be correctly measured.

In this embodiment, the error pattern is changed each time the error pattern determination means 25 determines the coincidence of the error pattern.
Even if such an error occurs in the communication network 1, only an erroneous measurement needs to be performed only once.

As described above, the error pattern judging means 25 determines that the error pattern matches M times (M is plural).
When the error pattern is switched each time the determination is made, if an error of the same pattern as the error pattern added by the error adding means 23 occurs in the communication network 1, erroneous measurement is performed at most M times. Only then can correct measurements be made.

As described above, the transmission delay time measuring device 20 according to the embodiment includes the error pattern generating means 22 which can selectively output a plurality of different error patterns, and determines the error pattern output from the error pattern generating means 22 in a predetermined manner. An error pattern switching means 29 for switching at each timing is provided to measure a transmission delay time while switching an error pattern to be added to a signal to a different pattern at each predetermined timing.

For this reason, even when an error having the same pattern as the error added by the error adding means 23 occurs in the communication network 1, only an erroneous measurement need be performed temporarily.
It is possible to return to the correct measurement after the switching of the error pattern, the reliability of the measurement result is significantly improved, and the evaluation of the line can be performed correctly.

[0046]

As described above, the transmission delay time measuring apparatus of the present invention is provided with the error pattern generating means capable of selectively outputting a plurality of different error patterns, and the error pattern output by the error pattern generating means is provided. An error pattern switching means for switching at every predetermined timing is provided, and the transmission delay time is measured while switching the error pattern to be added to the signal to a different pattern at every predetermined timing.

For this reason, even when an error having the same pattern as the error added by the error adding means occurs in the communication network, only an erroneous measurement need be performed temporarily, and a correct measurement is returned after the error pattern is switched. The reliability of the measurement result is significantly improved, and the line can be evaluated correctly.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment;

FIG. 3 is a timing chart for explaining the operation of the conventional device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Communication network 2a Up link 2b Down link 20 Transmission delay time measuring device 20a Output terminal 20b Input terminal 21 Pattern signal generating means 22 Error pattern generating means 23 Error adding means 24 Error detecting means 25 Error pattern judging means 26 Clocking means 27 Statistics Processing means 28 Display device 29 Error pattern switching means

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G04F 10/00 G04F 10/04 H04B 3/46

Claims (1)

(57) [Claims] 1. A pattern signal generating means (2) for outputting a signal of a predetermined pattern to a communication network (1) in a loopback mode.
(1) an error pattern generating means (22) capable of selectively outputting a plurality of different error patterns; and each time an instruction to add an error is received, a signal output from the pattern signal generating means to the communication network is generated. An error adding unit (23) for adding an error of the error pattern output from the error pattern generating unit; and comparing a pattern of a signal returned from the communication network with a pattern of the signal output by the pattern signal generating unit. Error detecting means (24) for detecting an error by detecting whether the error pattern detected by the error detecting means matches the error pattern added by the error adding means. Error pattern determining means (25) for instructing the error adding means to add an error each time the A time measuring means (26) for measuring, as a transmission delay time, a time from when the error added by the error pattern is output to the communication network until the error pattern determining means determines that the error pattern matches, and Error pattern switching means (29) for switching the error pattern output by the generation means at predetermined timings, wherein the transmission delay time is measured while switching the added error pattern to a different pattern at predetermined timings. Transmission delay time measuring device.