JP3365160B2 - Error measurement circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit error evaluation device, and more specifically, it has a pseudo random pattern (hereinafter referred to as PN pattern) sent from a transmitting device side in a receiving device. The present invention relates to an error measuring circuit for detecting an error by comparing with a reference PN pattern generated by a PN pattern generating circuit.

[0002]

2. Description of the Related Art A PN pattern is often used for testing communication devices, transmission devices, transmission lines and the like. In a test device that transmits and receives a PN pattern to perform a test, a receiving device synchronizes a received signal with an internally generated reference signal, compares the received data with the reference signal,
The number of erroneous bits is counted and the received data is evaluated.

That is, in this type of test, the PN pattern generated in the transmission device is received by the reception device via the device or the transmission device, and is stored in the reception device.
It is compared with a reference PN pattern generated by the N pattern generation circuit. Then, the PN pattern generated in the transmitting device is compared with the reference PN pattern generated by the PN pattern generating circuit in the receiving device, and the number of bit errors in the received data is counted and output.

Next, a conventional technique of an error measuring circuit for counting the number of bit errors of received data will be described with reference to FIG. FIG. 3 is a block diagram of an error measuring circuit in the prior art. 1 in FIG. 3 is a reception data input terminal, 2
Is a PN pattern generation circuit for outputting reference data in the receiving device, 3 is a comparison circuit, 4 is a counter circuit, 5 is a latch circuit, and 6 is an error count value output terminal.

In FIG. 3, the reception data input by the receiving device is input to the reception data input terminal 1. Latch circuit 5
Latches a continuous pattern of received data, and outputs the latched data to the PN pattern generation circuit 2. The PN pattern generation circuit 2 uses the data output from the latch circuit 5 as an initial value, and outputs a PN pattern serving as reference data based on this.

The comparison circuit 3 compares the reception data input to the reception data input terminal 1 with the reference data output from the PN pattern generation circuit 2, and outputs a detection pulse whenever they differ. The counter circuit 4 counts the number of the pulses and outputs the count value to the error count output terminal 6.

Next, a time chart for explaining the operation of FIG. 3 is shown in FIG. In FIG. 10, each bit of the PN pattern is assigned a code such as PN-n (n is an integer of 1 or more) for easy understanding. In the example of the time chart of FIG. 8, correct received data without error is input to the received data input terminal 1 as the first received data, and the received data PN- which is erroneous at the y-th bit after being received. The case where y is input is shown (the bar is shown above in FIG. 8). Further, in FIG. 10, the value of y (the number of bits) is a value sufficiently larger than the number of bits a necessary for generating the PN pattern.

When the received data is received, the latch circuit 5 performs P measurement in order to measure an error from the beginning of the received data.
Hold N-1 to PN-a. Here, a is an integer equal to or larger than the number of bits required for the PN pattern generation circuit 2 to start. Generally, when the PN pattern generating circuit 2 tries to output the number of PN stages x, a must have a value of at least x.

After the latch circuit 5 holds the received data,
The PN pattern generation circuit 2 uses the output of the latch circuit 5 as an initial value, and the reference PN patterns PN-1 and PN-.
2 ,. ． ． Is output. The comparison circuit 3 compares the reception data input to the reception data input terminal 1 with the reference data output from the PN pattern generation circuit 2. In the case of FIG.
Since the received data in PN-y differs from the reference PN pattern, a pulse is output at that time. The counter circuit 4 counts this pulse and outputs the counter value from N to N + 1.

[0010]

However, in such a conventional error measuring circuit, if the data PN-1 to PN-a initially held by the latch circuit 5 is erroneous, accurate error measurement cannot be performed. . That is, when the value of y is smaller than a, accurate error measurement cannot be performed if the received data is used as a reference. An actual example at that time is shown in the time chart of FIG.

In FIG. 4, erroneous received data PN-y is shown.
Is smaller than PN-a, the latch circuit 5 holds this erroneous received data, and the PN pattern generation circuit 2 generates reference data with this received data as an initial value. Therefore, the initial value data PN-1 to PN
The received data and the output (reference data) of the PN pattern generation circuit 5 are the same at the points -y to PN-a, and no error is counted in PN-y.

After that, since the PN pattern generation circuit 5 starts with an incorrect initial value, it is not the pattern synchronized with the received data but the PN patterns PN-xx ,. ． ． To occur. Since the received data and the data output from the PN pattern generation circuit 5 are not synchronized, the value of the counter circuit 4 becomes indefinite. Thus, when y is smaller than a, accurate error measurement cannot be performed.

As described above, in the conventional error measuring circuit, the data latched by the latch circuit 5 should not have an erroneous pattern. If erroneous received data is received and the latch circuit 5 latches the erroneous pattern,
The PN pattern generation circuit 2 starts with an incorrect initial value. Therefore, there is a problem in that the PN pattern synchronized with the received data cannot be output and the error cannot be accurately measured.

On the other hand, when the data is sent from the transmitting side to the receiving side, the data are often sent in bursts. Below, the pattern shown in FIG.
The case where the data is input to the reception data input terminal 1 will be described. In the pattern of FIG. 5, the PN pattern occurs in bursts, and is divided into a section 11 in which no data exists and a section 12 in which a PN pattern exists. In addition, it is unknown when the section in which the PN pattern exists occurs, the length of the section, and from which pattern the PN pattern starts.

When the pattern as shown in FIG. 5 is evaluated by the conventional technique, the latch circuit 5 latches the first data in the section in which the data exists, and the PN pattern generation circuit 2 uses the latched data as an initial value. The PN pattern is output and the number of errors is measured only in the section where data exists.

However, when there is a section 11 in which no data exists and a section 12 in which the data exists as shown in FIG. 5, the first pattern of the section 12 in which the data exists is that of the section in which the data exists due to the pattern effect. It is more likely to make a mistake than the pattern on the way. When the first pattern of the section 12 in which the data exists is erroneously received, the latch circuit 5 latches the erroneous pattern, so that the PN pattern generation circuit 2 starts with an erroneous initial value. Therefore, there is a problem that the received signal and the signal output from the PN pattern generating circuit 2 of the reference signal cannot be synchronized and the error cannot be measured.

According to the present invention, it is assumed that a test pattern having a section 11 where data is not present and a section 12 where data is present is received and the first pattern of the section where data is present is erroneously received due to a pattern effect or the like. Another object of the present invention is to provide an error measuring circuit capable of accurately counting bit errors.

[0018]

In order to achieve this object, the present invention compares received data input to a received data input terminal 1 with reference data output from a pseudo random pattern generating circuit in a receiving device. However, the error measuring circuit for detecting an error in the received data is the received data input terminal 1
The number of bits of the received data input to is counted, the timing generation circuit 9 that outputs a timing signal when the number of bits reaches a predetermined number, and the received data input to the received data input terminal 1 are accumulated, A FIFO buffer 8 that outputs the received data accumulated in the input order when a timing signal is input from the timing generation circuit 9.
When a timing signal is input from the timing generation circuit 9, the received data is held by a predetermined number of bits from that point, and the latch circuit 5 that outputs the held bit and the output of the bit held by the latch circuit 5 are output. An n-multiplexing PN pattern generating circuit 7 that outputs an n-series multiplexing pseudo-random pattern as an initial value, and a timing generating circuit 9 among the n-series pseudo-random patterns that the n-multiplexing PN pattern generating circuit 7 outputs. An n: 1 select circuit 10 that selectively outputs one sequence corresponding to a predetermined number of bits, received data output from the FIFO buffer 8, and a pseudo random pattern that is reference data output from the n: 1 select circuit 10. Is input, and the comparison circuit 3 that performs detection output when these data do not match and the comparison circuit 3 outputs And a counter circuit 4 for counting the detection output that.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION In the error measuring circuit of the present invention,
First, the reception data input to the reception data input terminal 1 is stored in the FIFO buffer 8. Then, instead of generating the reference PN pattern by holding the beginning of the received data that is likely to be erroneous due to the pattern effect when the received data is received, the data after the received data is input a few bits after it is input Is held by the latch circuit 5. From the held value, the n multiplexing PN pattern generating circuit 7 and n: 1
The select circuit 10 outputs the reference PN pattern, and FI
The error measurement is performed by the comparison circuit 3 and the counter circuit 4 in synchronization with the received data stored in the FO buffer 8.

FIG. 1 is a block diagram showing an embodiment of an error measuring circuit according to the present invention. In FIG.
1 is a reception data input terminal, 3 is a comparison circuit, 4 is a counter circuit, 5 is a latch circuit, 6 is an error count value output terminal, 7 is an n-multiplexing PN pattern generation circuit, and 8 is a FIFO.
A buffer, 9 is a timing generation circuit, and 10 is an n: 1 select circuit.

First, the multiplexing PN pattern generating circuit 7 will be described with reference to FIG. FIG. 6 shows an example of a PN pattern generation circuit that outputs a PN pattern that is not for multiplexing. The PN pattern generation circuit of FIG. 6 is an N-stage DFF circuit 22-1.
The shift register 22-N includes an exclusive OR operation circuit 23 serving as a feedback input of the shift register. In FIG. 6, 20 is a clock input terminal and 2 is a clock input terminal.
Reference numeral 1 is a PN pattern output terminal. The pattern generated by this circuit has a period of (2 ^N -1) bits and is usually
It is called an N-stage PN pattern.

Here, as a method of outputting the above-mentioned PN pattern at low cost and at high speed, there is a method of outputting a plurality of parallel PN patterns and multiplexing those outputs by a multiplexing circuit to output the PN pattern. And
A PN pattern generating circuit that outputs this parallel PN pattern is called a multiplexing PN pattern generating circuit, and one that outputs n parallel PN patterns is called an n multiplexing PN pattern generating circuit.

Next, FIG. 7 shows a block diagram of the n-multiplexing PN pattern generating circuit 7. PN pattern generation circuit 7 for n multiplex
Is composed of n DFF circuits 32-1 to 32-n. The PN arithmetic circuit 33 is composed of an exclusive OR arithmetic circuit, and receives the outputs of the DFF circuits 32-1 to 32-n as inputs and calculates the state of the DFF of the next clock. 31-1 to 1
31-n are parallel PN pattern output terminals.

The output pattern of this n-multiplexing PN pattern is shown in the time chart of FIG. The result of multiplexing the outputs of the multiplexing PN pattern generation circuit, that is, pn
(1), pn (2) ,. ． ． , Pn (n), pn (n +
The result of multiplexing with 1) becomes a PN pattern. Also, PN
As a property of the pattern, the result of sampling the PN pattern at regular intervals also has the property of becoming the PN pattern. Therefore, each PN pattern output terminal 31
The patterns output by -1-32-n are PN patterns n
It is the result of sampling at bit intervals, and these are all PN patterns.

Then, the PN patterns are output with a constant gap, as shown in FIG. In FIG. 9, the same pattern output from the PN pattern output terminal 31-1 is the same as the PN pattern output terminal 31-2.
Are output with a delay of Δ bits, and the PN pattern output terminal 31-3 is output with a delay of Δ bits. Then, Δ is Δ = 2 ^N / n when the number of bits in one cycle of the PN pattern is 2 ^N −1 bits.

From this, it can be seen that the output of the n-multiplexing PN pattern generating circuit can obtain n PN patterns each shifted by a constant bit when given an initial value.

Next, an embodiment of the present invention will be described with reference to FIG. When the received data is input to the received data input terminal 1, the received data is first stored in the FIFO buffer 8. The timing generation circuit 9 counts the number of bits of data input to the reception data input terminal 1 and outputs a timing signal.

The timing of outputting the timing signal is
Data in which any one of the n outputs of the n-multiplexing PN pattern generating circuit 7 is synchronized with the output of the FIFO buffer 8 when the received data is latched and input as the initial value of the n-multiplexing PN pattern generating circuit 7. Is when it occurs.
That is, the timing at which the timing signal is actually output is determined according to the selected output sequence of the n outputs of the n-multiplexing PN pattern generating circuit 7. Specifically, when the PN pattern output terminal 31-a (a is one of 1 to n) is selected, the timing generation circuit 9 determines that the number of bits of the input received data is the PN pattern output terminal 31-.
When the number of bits corresponding to a is reached, a timing signal is output.

When the timing generation circuit outputs the timing signal, the latch circuit 5 holds the pattern input to the reception data input terminal 1 at that time. The n-multiplexing pattern generation circuit 7 outputs an n-series PN pattern shifted by Δ bits at regular intervals, using the pattern latched by the latch circuit 5 as an initial value.

Further, when the timing signal is input, the FIFO buffer 8 outputs the stored signal to the comparison circuit 3 in the input order. At this time, assuming that the number of bits from the input of the reception data to the output of the timing signal is b bits, the data output to the comparison circuit 3 is output after being delayed by b bits from the input of the reception data input terminal 1. Will be. Therefore, in the n: 1 select circuit 10,
Among the n outputs of the multiplexing PN pattern generating circuit 7, the PN pattern output terminal 31 that outputs data of b bits before the initial value is selected, and this data is output to the comparing circuit 3 as reference data.

The comparison circuit 3 compares the received data sent from the FIFO buffer 8 with the reference data from the n: 1 select circuit 10, and outputs a pulse each time the received data differs from the reference data. The counter circuit 4 counts the pulse and outputs the count value to the count value output terminal 6.

Next, a time chart for explaining the operation of the circuit of FIG. 1 is shown in FIG. In FIG. 2, as in the time chart of FIG. 4, PN-1 and PN- are assigned to each bit of the received data.
2 ,. ． ． Like this, here is PN-2
Suppose that the bit was received by mistake. Then, it is assumed that the timing signal is output j bits after the received data is input, and the pattern of the jth to (j + n) th bits after j bits is latched by the latch circuit 5 and the n-multiplexing PN pattern generating circuit is generated. 7, and the n-multiplexing PN pattern generating circuit 7 outputs the PN pattern sequence using this as an initial value. Further, of these PN pattern sequences, the i-th output corresponding to b bits is selected by the n: 1 select circuit 10, and the received data PN-1, PN-.
2 ,. ． ． And reference data PN- (j + i), PN-
(J + n + i) ,. ． ． Are compared by the comparison circuit 3, respectively.

In the time chart of FIG. 2, the timing generation circuit 9 counts the number of bits of received data after being input, and outputs a timing signal when j is counted. When the timing signal is output, the latch circuit 5 holds the patterns PN-j to PN- (j + n) necessary for the n-multiplexing PN pattern generating circuit 7 to start, and the n-multiplexing PN pattern generating circuit 7 holds the pattern. With that as the initial value, n PN patterns shifted by constant bits are output. Since the i-th output of the n PN patterns is output in synchronization with the data input from the beginning of the received data, the n: 1 select circuit 10 uses the n-multiplexing PN.
The pattern generation circuit 7 output i is selected and output.

After the timing signal is output, the FIF
The O buffer 8 outputs the received data from the beginning, and the comparison circuit 3 compares the output from the FIFO buffer 8 with the output from the n: 1 select circuit 10. In the time chart, the reception data PN-2 of the second bit is erroneously received, so that the comparison circuit 3 outputs a pulse at that time, and the counting circuit 4 counts the pulse and counts up.

[0035]

According to the present invention, the reference PN pattern is not generated with the leading pattern of the received data, which is highly likely to be erroneous due to the pattern effect, as the initial value, and some bits of the received data have passed and the pattern Since the reference PN pattern is generated in synchronization with the data stored in the FIFO buffer 8 by holding the received data that is less affected by the effect and the error is measured, for example, the data as shown in FIG. 5 does not exist. Section 11 and section 12 where data exists
Even if the first data of the section 12 in which the data exists is erroneously received by the receiving device due to the pattern effect or the like, accurate error counting can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an error measuring circuit according to the present invention.

FIG. 2 is a time chart explaining the operation of the block diagram of FIG.

FIG. 3 is a block diagram showing an example of an error measuring circuit according to a conventional technique.

FIG. 4 is a time chart explaining the operation of the block diagram of FIG.

FIG. 5 is a diagram showing an example of received data.

FIG. 6 is a block diagram showing a configuration of a PN pattern generation circuit.

FIG. 7 is a block diagram showing a configuration of an n-multiplexing PN pattern generating circuit.

FIG. 8 is a time chart showing the output of the n-multiplexing PN pattern generating circuit.

FIG. 9 is a PN output from an n-multiplexing PN pattern generation circuit.
It is a time chart explaining the state of a pattern.

[Explanation of symbols]

1 Received data input terminal 2 PN pattern generator 3 comparison circuit 4 counter circuit 5 Latch circuit 6 Error count value output terminal 7 n multiplex PN pattern generation circuit 8 FIFO buffer 9 Timing generation circuit 10 n: 1 select circuit

Claims (2)

(57) [Claims] 1. An error measuring circuit for detecting an error in the received data by comparing received data input to a received data input terminal (1) with reference data output from a pseudo random pattern generation circuit in a receiving device. , A timing generation circuit (9) that counts the number of bits of the reception data input to the reception data input terminal (1) and outputs a timing signal when the number of bits reaches a predetermined number, and a reception data input terminal When the received data input to (1) is accumulated and the timing signal is input from the timing generation circuit (9), a FIFO buffer (8) that outputs the accumulated received data in the order of input, and a timing generation circuit ( When the timing signal is input from 9), the received data is held at the specified number of bits from that point, and the held bit is output. n for outputting a latch circuit (5), the pseudo-random pattern for multiple n series output bits held in the latch circuit (5) as an initial value for
Multiplexing PN pattern generating circuit (7), and n sequences of pseudo-random patterns output from n multiplexing PN pattern generating circuit (7), 1 sequence corresponding to the number of bits predetermined by the timing generation circuit (9) The n: 1 select circuit (10) for selectively outputting the received data, the received data output from the FIFO buffer (8) and the pseudo random pattern which is the reference data output from the n: 1 select circuit (10) are input. An error measuring circuit characterized by having a comparison circuit (3) for performing detection output when these data do not match, and a counter circuit (4) for counting the detection output output from the comparison circuit (3). . 2. The error measuring circuit according to claim 1, wherein the timing of the timing signal output from the timing generating circuit (8) is arbitrarily variable according to the series selected by the n: 1 select circuit (10). An error measuring circuit characterized by being capable.