JP3058805B2 - Bit error test equipment for communication networks - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention measures a bit error of digital data transmitted through a communication line formed in a communication network for transmitting and receiving digital data represented by ISDN (Integrated Services Digital Network). The present invention relates to a bit error test device for a communication network.

[0002]

2. Description of the Related Art ISDN (Integrated Services Digital Network) is a communication network for transmitting a large number of multiplexed digital data at high speed and efficiently. When such a communication network is newly constructed or at regular intervals after the start of operation, it is necessary to measure various characteristics of the communication network and test whether the communication network operates normally. Among the test items for testing whether or not this communication network operates normally, there is a bit error test for testing whether or not digital data is correctly transmitted through a formed communication line.

A test method for measuring a bit error of digital data transmitted on a transmission line is disclosed in Japanese Patent Laid-Open No. 4-5402.
No. 4 proposes a transmission path test method. According to this test method, a test device is attached to one end of a transmission path to be tested, and a folding device is connected to the other end. Then, a PN (pseudo-random) pattern signal is transmitted from the test apparatus to the transmission path. Then, the test device receives the PN pattern signal that is turned back by the turn-back device attached to the opposite end of the transmission path. This received PN pattern signal,
P output from a separately provided PN pattern generation circuit
Synchronize with the N pattern signal, and
If the pattern and the received PN pattern do not match, it is determined that a bit error has occurred. Then, the number of occurrences and the occurrence rate of the detected bit errors are calculated, and the transmission quality of the transmission path is evaluated using the number of occurrences and the occurrence rate.

[0004]

However, the above-described bit error test method has the following problems to be improved. That is, in the conventional method,
Statistical data such as the occurrence of a bit error during transmission of digital data on the transmission path and the occurrence rate and the number of occurrences can be accurately grasped, and the transmission quality of the transmission path can be grasped quantitatively.

[0005] The statistically grasping of the bit error means that the transmission path to be measured has basically no failure, the occurrence of the bit error is very small, and the failure that the same bit error always occurs at the same position is considered. Not at all.

However, for example, when a switch in a communication network is newly constructed, or when this communication network is operated for a long period of time, bit errors frequently occur at the same position due to a design error or a failure. In some cases.

[0007] In addition, for example, when the operation rate of the communication network increases during the day of the week other than the daytime and Saturday and Sunday, bit errors may occur frequently. In such a case, the bit error occurrence rate increases, but the error occurrence position, the error occurrence time, and the time zone cannot be specified only by the bit error occurrence rate.

[0008] Therefore, there is a problem that it is not possible to investigate the cause of the abnormality or take an appropriate response to the occurrence of the abnormality at an early stage. The present invention has been made in view of such circumstances, and not only detects a bit error, but also detects a state before and after an error bit, thereby enabling a bit error generation process, [0 continuation], [ It is an object of the present invention to provide a bit error test apparatus for a communication network capable of detecting a detailed bit error characteristic such as [1 continuous] and capable of investigating the cause of an abnormality and appropriately coping with the occurrence of the abnormality at an early stage.

[0009]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a communication network in which a transmitting side measuring device and a receiving side measuring device are connected to each other via a communication network. In a bit error test apparatus of a communication network for measuring a bit error of digital data transmitted through the communication line, PN pattern signal transmitting means for transmitting a PN pattern signal to the communication line to a transmission side measuring device is provided. Has been added.

Further, a PN pattern generating circuit for outputting the same PN pattern signal as that on the transmitting side to the receiving side measuring instrument, and a PN pattern signal output from the PN pattern generating circuit via the communication line. A synchronization establishing means for synchronizing with the PN pattern signal; an exclusive OR means for obtaining an exclusive OR signal of the synchronized PN pattern signal and the received PN pattern signal; A bit pattern consisting of a predetermined number of consecutive bit data included in the output exclusive OR signal is extracted, and when the bit pattern includes bit data other than 0, an error is determined in which the bit pattern is determined to be an error pattern. Determining means for adding the time information read from the clock circuit to the determined error pattern and outputting the error data as error data; And data output means, and adding the error type determination means for determining the error type based on the bit pattern of the received PN pattern signal corresponding to the error pattern and the error pattern.

[0011]

The PN pattern signal output from the PN pattern generation circuit provided in the receiving-side measuring device in the bit error test apparatus of the communication network having the above-described configuration is used for the communication line formed in the communication network. Is synchronized with the received PN pattern signal received via the. An exclusive OR signal between the PN pattern signal after the synchronization is established and the received PN pattern signal is obtained.

When the exclusive OR signal contains the bit [1], it can be determined that a bit error has occurred. In the conventional method, the number of generated bits [1] and the rate of generated bits [1] are calculated. According to the present invention, a bit pattern including a predetermined number of bit data, such as eight, included in the exclusive OR signal is extracted at regular intervals, and the bit pattern includes the bit [1]. In this case, the bit pattern composed of a plurality of bits is defined as an error pattern.

[0013] Then, time information is added to this error pattern to obtain error data. Therefore, when an error occurs, the occurrence time can be grasped simultaneously. Further, when an error occurs, a bit pattern of a received PN pattern signal corresponding to the error pattern is checked to determine an error type. This error type includes [0 continuous] and [1 continuous]. If the error pattern is only [1], for example, it means that a bit slip has occurred. Therefore, when a pit error is detected, the error type can be grasped by referring to the bit data before and after the pit error.

[0014]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a schematic diagram showing the entire configuration of the bit error test device of the communication network according to the embodiment.

Two measuring devices 2a and 2b and one control device 3 are connected to ISDN 1 as a communication network. In an actual test apparatus, more than 1000 measuring instruments 2a,
2b is connected, but for the sake of simplicity, it is assumed in the example test apparatus that there are two measuring devices.

FIG. 1 is a block diagram showing a schematic configuration of one measuring device 2a. Control CP for executing various information processing
A memory 5 dedicated to the control CPU 4 is connected to U4. Furthermore, the call control CPU 4 is connected to the control CPU 4 via the common memories 6, 7, 8, 9, and 10, respectively.
11, LAPB ₁ 12 (B ₁ channel packet communication control unit), LAPB ₂ 13 (B ₂ channels of data communication control unit), the measurement unit (DSP 1) 14, measuring unit (DSP 3)
15 are connected.

The measuring section (DSP1) 14 and the measuring section (DS)
The measuring section (DSP2) 16 and the measuring section (DSP4) 17 are connected to the P2) 15 respectively. Measuring unit 14,
15 is input with the current time from the clock circuit 18. This time _DT is, as shown in FIG. 7, the year, month, day, hour, minute,
Seconds, numerical values in units of 250 μs from 0 to 3999. That is, the time _DT of the clock circuit 18 is 250 μ
It has an accuracy of s units.

The clock circuit 18 is driven by a driving pulse signal supplied from a crystal oscillator 20 via a PLL circuit 19. The frame pulse signal FP is input to the PLL circuit 19 from the layer 1 circuit 21. Layer 1 circuit 2
1 is a frame pulse signal having a period corresponding to the frame period of a control signal on a D channel transmitted between the measuring device 2a and the ISDN1 switch when the measuring device 2a is connected to the ISDN1 switch. FP to PL
It is sent to the L circuit 19. The PLL circuit 19 always controls the frequency of the drive pulse signal supplied to the clock circuit 18 to a correct value based on the frequency of the frame pulse signal FP. Therefore, as described above, the clock circuit 18 measures the time _DT with high accuracy.

The LAPB ₁ 12, LAPB ₂ 13, and measuring units 16 and 17 are two-stage time-division switch circuits 22 and 23.
Are connected to the above-described layer 1 circuit 21 and the monitoring layer 1 circuit 24.

The monitoring layer 1 circuit 24 stores various information transmitted / received on each of D (call control) channels and B ₁ and B ₂ communication channels (communication lines) formed between the layer 1 circuit 21 and the ISDN ₁ . Monitor. D, B ₁ ,
B ₂ transmitted on the measuring device 2a side to ISDN1 side monkey information _{D (T), B 1 (} T), B 2 (T) and ISDN1 each information received from the side to the instrument 2a side D (R), B ₁
(R), B ₂ (R) and the state of the layer 1 circuit 21 are input to the measurement units 16 and 14 via the time division switch circuits 23 and 22 as necessary.

The call control CPU 11 has a common memory 25.
The operation of the LAPD (call control unit) 26 is controlled via the.
The LAPD (call control unit) 26 includes the layer 1 circuit 21 and the IS
It has a function of connecting a communication line to another measuring device 2b or control device 3 via the DN1.

The other measuring device 2b has substantially the same configuration as the measuring device 2a. For example, when the control CPU 4 exchanges information with another measuring device 2b or the control device 3,
A line formation command for designating the measuring device 2b or the control device 3 as the information exchange destination is sent to the call control CPU 11. C for call control
The PU 11 starts an LAPD (call control unit) 26. LA
The PD (call control unit) 25 outputs the I
A call is made to the exchange of SDN1.

This call enters, for example, the other measuring device 2 b via the ISDN 1 exchange, and is called to the LAPD (call control unit) 26 via the layer 1 circuit 14. As a result, a digital communication line is formed between the measuring devices 2a and 2b. Thus, the control CPU 4 of one measuring device 2a and the control CPU 4 of the other measuring device 2b are connected to the LAPB ₁ 12 or LAPB ₂ 13, the time-division switch circuits 22, 23, and the layer 1 circuit 21 in the measuring device 2a. , ISDN 1, layer 1 circuit 21 in measuring device 2b, time division switch circuit 2
Information can be exchanged via 3, 22, LAPB ₁ 12 or LAPB ₂ 13.

According to the same procedure, each measuring device 2a, 2b
Can exchange information with the control device 3 via the ISDN 1. Each of the measuring units 15 and 17 is constituted by a kind of computer, and based on a test command from the control CPU 4, a bit error of digital data transmitted and received through a communication line formed with the other measuring device 2b. It has the function of conducting tests. In this embodiment, the measuring unit 15 is in charge of the main part of the bit error test, and the measuring unit 1
Reference numeral 7 has a data input / output function.

FIG. 3 is a block diagram showing a schematic configuration of the measuring section 15. The PN pattern generation circuit 27 is, for example, (2 ⁹
A PN (pseudo-random) pattern signal a of nine stages having a bit period of -1) is output. The PN pattern signal a output from the PN pattern generation circuit 27 is
, And is input to one input terminal of a nine-stage synchronization establishing circuit 29. The PN pattern signal (received PN pattern signal b) received from the other measuring instrument 2b (2a) via the measuring unit 17 is input to the other input terminal of the synchronization establishing circuit 29.

The synchronization establishing circuit 29 synchronizes the PN pattern signal a with the received PN pattern signal b.
When synchronization is established, the synchronization establishment signal c is sent to the control unit 31, and the PN pattern signal a ₁ after synchronization establishment is applied to one input terminal of the exclusive OR gate 30. The other input terminal of the exclusive OR gate 30 receives the reception PN pattern signal b. The exclusive OR signal d output from the exclusive OR gate 30 is input to the next control unit 31. The control unit 31 includes the reception PN
The pattern signal b is input.

The control unit 31 controls the operation of the gate circuit 28 and receives the signal via the communication line formed with the counterpart measuring instrument 2b based on the synchronization establishment signal c from the synchronization establishment circuit 29. A bit error of the received PN pattern signal b is detected, the error type is determined, and the determination result is written to the common memory 10 as error data together with the current time _DT read from the clock circuit 18.

The measuring section 15 of the other measuring instrument 2b has substantially the same configuration as the measuring section 15 of the measuring instrument 2a. Further, the control device 3 in FIG. 2 collects error data of each measuring unit 15 of each measuring device 2a, 2b via each control CPU 4.

The bit error test operation of each measuring unit 15 of each of the measuring devices 2a and 2b in the bit error test apparatus for a communication network having such a configuration will be described with reference to the flowchart of FIG. 4 and the sequence diagram of FIG. .

First, the control device 3 first sets the measuring devices 2a,
The caller and the receiver are designated for 2b. Each measuring device 2
The control CPUs 4a and 2b set in the control unit 31 of the measuring unit 15 whether they are the calling side or the called side.

Control unit 3 of measuring unit 15 of measuring devices 2a and 2b
1 executes a bit error test process according to the flowchart of FIG. In P (program step) 1, it is determined whether the caller is designated as a calling side or a called side, and in the case of a calling side,
As shown in the sequence diagram of FIG. 5, at P14, the gate circuit 28 of FIG.
The control unit 17 sends the PN pattern signal a output from the control unit 7 to a communication line formed in the ISDN 1.

In P2, if the self is the receiving side, the gate circuit 28 is closed to prevent the PN pattern signal a output from the PN pattern generation circuit 27 from being transmitted to the ISDN1.

In this embodiment, the synchronization establishing circuit 29
, A PN pattern signal a output from the PN pattern generation circuit 27 and a reception PN pattern signal b received from the transmission side measuring device 2a via the communication line of the ISDN 1 and the measuring unit 17 are input.

[0034] When the synchronization establishment signal c from the synchronization establishment circuit 29 is input, is output from the synchronization establishment circuit 29 the PN pattern signal a ₁ and the received PN pattern signal b is determined that synchronization is maintained ( P3).

Note that the actual bit error rate is 10 ^-5 to
Since it is as small as 10 ^-6 , no synchronization is established due to the presence of a bit error. When synchronization is established, after a lapse of a predetermined time ΔT such as 1 ms (P4), 8 bytes of the same timing in the received reception PN pattern signal b and the exclusive OR signal d output from the exclusive OR gate 30 are obtained. Read the data. Then, define the 8 bytes data of the received PN pattern signal b and the received bit pattern D _R, defined as the exclusive bit pattern D _EX 8 bytes data of the exclusive OR signal d (P5, P6) . At the same time, the time D
Read _T (P7).

In P8, if all the bit data of the 8-byte exclusive OR bit pattern D _EX is [0], the reception of 8 bytes corresponding to the exclusive OR bit pattern D _EX is performed. the bit pattern D _R is the bit error has not occurred, the process returns to P4, a predetermined time (delta
After T), each bit pattern D _R and D _EX of the next 8 bytes is read.

Further, 1 at P8, the bit data of the even one [1] to the exclusive-OR bit pattern D _EX is present, the received bit pattern D _R of the corresponding 8 bytes
It can be determined that more than one bit error has occurred. In this case, the exclusive OR bit pattern D _EX is defined as an error pattern _DE .

[0038] FIG. 6 is a diagram showing the relationship between the 8-byte pattern of the PN Bataan signals a ₁ to synchronize the received bit pattern D _R of the received bit pattern D _R Toko reading was 8 bytes. In this case, since they do not match, the obtained exclusive OR bit pattern D _EX becomes an error pattern _DE .

[0039] Then, examines each bit data of the received bit pattern D _R read earlier corresponding to the error pattern D _E, when all bit data 64 is [0] (P9), this error It is determined that [0] is a continuous error type, and the error data incorporating the previously read time _DT and the type information of [0 continuous] is stored in the common memory 10.
(P13).

Further, when all 64-bit data of the received bit pattern D _R is [1] (P10), this error is determined as an error type successive [1], read previously The error data incorporating the time _DT and the type information of [1 consecutive] is written to the common memory 10 (P1
2).

Further, although not described in this flow chart, when all 64-bit data constituting the error pattern D _E is [1], the received bit pattern D _R is one bit for correct bit pattern It is determined that the error type is shifted bit by bit, and the error data incorporating the previously read time _DT and the type information of [bit slip] is written to the common memory 10.

In other cases, error data incorporating the previously read time _DT and error pattern _DE are written to the common memory 10 (P11). This received bit pattern D
_When the bit error measurement for _R is completed, the process returns to P4,
After a lapse of a predetermined time (ΔT), the bit patterns D _R and D _EX for the next 8 bytes are read.

FIG. 7 is a format showing error information including a time _DT written to the common memory 10 and an error pattern _DE . [0 continuous] [1 continuous]
When an error type such as [bit slip] is specified, this error type is set in the area of the error pattern _DE .

Thus, the fixed time ΔT every 1 ms
Each time elapses, the received determine the presence or absence of bit errors in the received bit pattern pattern D _R of 8 bytes in PN pattern signal b, and if there is a hit error errors common and the the occurrence time error type memory 10 Are written in order.

When a predetermined test end time comes, the bit error test process is terminated and the control CP
Send a test end notification to U4. Each control CPU 4 that has received the test end notification from its own measurement unit 15
As shown in the sequence diagram of FIG.
Sends a line disconnection command to the LAPD 26 via the. As a result, the LAPD 26 cuts off the communication line formed between the measuring devices 2a and 2b according to a predetermined call protocol.

Next, the control device 3 forms a communication line between the receiving side and the designated measuring instrument 2b, and collects each error data stored and held in the common memory 10 via the control CPU 4. .

The control device 3 executes an error analysis process based on the error data collected from the measuring device 2b on the receiving side. In the bit error test apparatus of the communication network configured as described above, the received PN pattern signal b as digital data transmitted through the communication line formed in the ISDN 1 is transmitted at a predetermined time interval ΔT, for example, a predetermined length of 8 bytes or the like. identify the received bit pattern D _R formed of the number of bits, error pattern D _E of the received bit pattern D _R
Seeking.

Therefore, when a bit error occurs, the number of occurrences of the bit error and the bit error occurrence rate can be calculated as in a normal bit error test apparatus, and [0 consecutive] when a bit error occurs. [1
A specific error type such as [continuous] or [bit slip] is grasped.

As described above, when the type of the error is determined, it is easy to specify the cause and the position of the occurrence of the bit error, and the trouble countermeasure can be taken promptly. In addition, since not only the specific error type but also the error pattern _DE can be grasped, it is possible to support the estimation of the error cause from the common bit error information.

Further, the occurrence time D _T is added to each bit error. Therefore, it is possible to obtain information on which time zone a bit error frequently occurs, information on what period a bit error occurs, and the like, and more detailed error analysis.

[0051]

As described above, in the bit error test apparatus for a communication network according to the present invention, a bit pattern consisting of a predetermined number of bits of a PN pattern signal received from a communication line is used as one unit for error measurement. When an error bit is found in the pattern, not only the error bit but also the error pattern of the entire bit pattern is detected.

Therefore, not only the detection of a bit error but also the state before and after an error bit is detected, so that the generation process of the bit error, [0 continuous], [1 continuous]
Etc., it is possible to detect a detailed bit error characteristic, and to investigate the cause of the abnormality and take an appropriate response to the occurrence of the abnormality at an early stage.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a measuring instrument in a bit error test device of a communication network according to an embodiment of the present invention.

FIG. 2 is a schematic view showing the entire apparatus of the embodiment.

FIG. 3 is a book diagram showing a schematic configuration of a measuring unit in the measuring device of the apparatus of the embodiment.

FIG. 4 is a flowchart showing a test operation of a measuring instrument in the apparatus of the embodiment.

FIG. 5 is a sequence diagram showing the operation of the apparatus of the embodiment.

FIG. 6 is a diagram showing a relationship between an error pattern and a received bit pattern in the device of the embodiment.

FIG. 7 is a format diagram showing error information in the apparatus of the embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... ISDN, 2a, 2b ... Measuring device, 3 ... Control device, 4
... Control CPU, 11 ... Call control CPU, 12 ... LAPB
₁ (packet communication control unit), 13: LAPB ₂ (data communication control unit), 14, 15, 16, 17: measuring unit, 18: clock circuit, 21: layer 1 circuit, 22, 23: time division switch circuit, 24 ... Monitor layer 1 circuit. 26 ... LAP
D (call control unit), 27 ... PN pattern generation circuit, 28 ...
Gate circuit, 29 synchronization establishment circuit, 30 exclusive OR gate, 31 control unit

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Naoki Yokoyama 1-6-1, Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Shoichi Yamakawa 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Japan (56) References JP-A-64-64430 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 1/00 H04L 12/26 H04L 29/14

Claims (1)

(57) [Claims] 1. A transmitting side measuring device (2) is connected to a communication network (1).
a) and a receiving-side measuring instrument (2b), forming a communication line between the measuring instruments via the communication network, and measuring a bit error of digital data transmitted through the communication line. In the bit error test device, the transmitting side measuring device (2a) includes a PN pattern signal transmitting unit (27, P1) for transmitting a PN pattern signal to the communication line.
The receiving side measuring device (2b) includes a PN pattern generating circuit (27) that outputs the same PN pattern signal as the transmitting side, and a PN pattern signal output from the PN pattern generating circuit. Synchronization establishing means (29) for synchronizing with the received PN pattern signal received via the communication line; exclusive OR means for obtaining an exclusive OR signal of the synchronized PN pattern signal and the received PN pattern signal (3
0), and at regular intervals, a bit pattern consisting of a predetermined number of continuous bit data included in the exclusive OR signal output from the exclusive OR means is extracted. Error determination means for determining this bit pattern as an error pattern when bit data is included (P8)
Error data output means (P11) for adding the time information read from the clock circuit to the determined error pattern and outputting it as error data; and outputting the error pattern and the reception PN pattern signal corresponding to the error pattern. A bit error test apparatus for a communication network, comprising: an error type determination unit (P9, P10) for determining an error type based on a bit pattern.