JPH0646105A - Equipment for adding disturbance of digital signal - Google Patents

Abstract

PURPOSE:To improve the reliability of an error detection test by setting a measuring period set for a frequency divider in accordance with the disturbance bit length without uniformly setting it to a normal bit length to equally add a bit error to all the pieces of bit data included in a disturbance object bit length. CONSTITUTION:In a controller 11, when an operator operates a condition setting part 13 to specify the normal bit length L and the disturbance object bit length A to input an experimental start command, respective frequency dividing ratios C1 and C2 corresponding to the combination are retrieved from a division ratio allotment table 12 formed in the internal storage part of the control part 11. Then, the frequency dividing ratio C1 is set to a frequency dividing circuit 4a in a first fixed period and the frequency dividing ratio C2 is set in a next fixed period. Besides, the value of a measurement bit length L1 (=C1) is set so that the value and the disturbance object bit length A are mutually prime and the value is less than the normal bit length L and the nearest to it. Besides, a measurement bit length L2 (=C2) is also set to be equal to the normal bit length L or to be not less than it and the nearest to it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal disturbance adding device for adding a disturbance bit to a digital signal at a constant bit period.

[0002]

2. Description of the Related Art The signal quality of various digital signals used in a data transmission system is statistically evaluated by, for example, the number of bit errors existing in a predetermined number of bits, that is, the error occurrence rate. PC, which is a typical digital signal
For the M signal, the error occurrence limit (SE) is specified in the G.821 standard of CCITT (International Telegraph and Telephone Consultative Committee).
As S; Severely Errered Seconds), the minimum quality level is determined to be that no more than one bit error is detected in an average of 1000 bit length (specified bit length L) in 1 second.

Therefore, in various devices including a digital exchange that handles such digital signals, it is necessary to test whether the error occurrence rate of the digital signals output from this device satisfies the above-mentioned standard. In addition, in devices that input and output digital signals, including the digital exchanges described above, monitor the bit errors of the input digital signals, and if the error occurrence rate exceeds the standards specified above, determine that the input signal is abnormal. Some have a function to warn a monitor or an operator.

Therefore, when testing whether or not the error detection function of such a device operates normally, a bit is intentionally added to a test digital signal input to this device in order to test various functions of the device. An error is generated to check whether the device under test normally detects this bit error.

FIG. 4 is a schematic diagram showing a test system for checking whether or not the device under test correctly detects a bit error.

The test signal generating circuit 1 sends a test digital signal a having a predetermined transmission format to the disturbance adding circuit 3 in the next disturbance adding device 2. Further, the test signal generating circuit 1 sends the clock signal b used to create the output digital signal a to the frequency dividing circuit 4 in the disturbance adding device 2. Therefore, the clock signal b has a frequency f equal to the bit rate (code rate) of the digital signal a and is synchronized with each bit data of the digital signal a. The frequency dividing circuit 4 divides the frequency f of the clock signal b by a preset frequency dividing ratio C, and sends the divided clock signal d having the frequency (f / C) to the disturbance adding circuit 3.

The frequency dividing ratio C of the frequency dividing circuit 4 is G.8.
1 defined by the error occurrence limit (SES) of 21 standards
A value C2 (= L) equal to the prescribed bit length L such as 000 and a value C1 (= L-1) shorter by 1 bit are selected and used alternately. According to this standard, C2 = 1000, C
1 = 999.

The disturbance adding circuit 3 sends the digital signal a input from the test signal generating circuit 1 to the device under test 5 as it is, unless the divided clock signal d is input. Then, when the divided clock signal d is input, the value of the bit data which is synchronized with the input of the divided clock signal d among the bit data forming the digital signal a is inverted.
That is, the pseudo bit error is added to the digital signal a every constant bit period (1 / C) determined by the frequency division ratio C.

As a result, the digital signal a1 to which the pseudo bit error is added is input to the device under test 5. The device under test 5 performs the original data processing of the input digital signal a1 and checks whether or not there is a bit error in the specific data in the digital signal a1 to check the bit error for one second. If the average is detected and the ratio is shorter than the specified bit length L, the error detection signal e is sent to the next error measuring device 6. The error measuring device 6 statistically processes the error detection signal e to evaluate the error detection capability of the device under test 5.

Here, when the frequency division ratio C of the frequency divider 4 is set to a value C2 (= L2 = L) equal to the specified bit length L, the error detection signal e is not output and the frequency divider 4 The division ratio C of 4 is a value C1 (= L
When 1 = L-1) is set, when the error detection signal e is output, it can be determined that the device under test 5 has a normal error detection capability.

[0011]

However, the disturbance adding device 2 shown in FIG. 4 still has the following problems to be improved.

That is, in the device under test 5 incorporated in the digital data transmission system, in a normal operating state, the digital signals input to the device under test 5 generally have many periodic signals as shown in FIG. As the test digital signal a to be input to the device under test 5, not only one bit error is added for each of the specified bit lengths L (L1, L2) described above, but also a fixed period. It is required that a bit error be added to each bit data that is repeated.

Specifically, when the digital signal a as shown in FIG. 5 is used, each bit data A1 and A2 included in the periodic disturbance target bit length A which must be added with a bit error. , ... It is desirable that a bit error is always added to AA. For example, when only a test in which no bit error is added to only a specific bit data An can be executed, when a bit error occurs in the corresponding bit data An during actual operation, that bit error is surely detected. I can't get any proof.

However, in the disturbance adding device 2 shown in FIG. 4, a bit error is not always added to each bit data A1, A2, ..., AA contained in one disturbance target bit length A.

FIG. 6 shows that there is bit data to which a bit error is not added in the disturbance target bit length A.
This will be described using the actual digital signal shown in. Figure 6 is C
ISDN [2 specified in CITT I ・ 430
Each terminal (NT) in the signal line composed of B + D]
It is a figure which shows the transmission format of the digital signal a transmitted on the T line and R line which connect with a network termination (NT).

Here, a total of 9 bits of the information bits B1 of the 8-bit structure and the control bits D, which are open to the user, are set as a disturbance target bit length A to which a disturbance bit is intentionally added. Then, each bit data included in the disturbance target bit length A is set to A1, A2, ..., A8, A9. When the prescribed bit length L is 1000, the frequency division ratio C set in the frequency divider 4 is C1 = L1 = 999 and C2 = L2 = 1000.

When the frequency division ratio C is C2 (= 1000), the disturbance target bit length A in the first measurement cycle L2.
When an error bit is added to the first bit data A1 included in the above, in the next measurement cycle L2, the minimum value X = 112, which is 9 · X ≧ 1000, due to its periodicity.
From (1000 = 9 × 111 + 1), the second bit data A2
An error bit is added to. Furthermore, the next measurement cycle L
In 2, an error bit is added to the third bit data A3. Thus, each time the measurement period L1 arrives, each bit data A included in the disturbance target bit length A is
Bit errors are added in order from 1 to A9, so
Bit errors are evenly added to all the bit data A1 to A9.

However, when the frequency division ratio C is C1 (= 999), the disturbance target bit length A is obtained in the first measurement cycle L1.
When a bit error is added to the first bit data A1 included in, in the next measurement cycle L1, due to its periodicity, the minimum value X = 111 that satisfies 9 · X ≧ 999 (999 = 9 × 111 +0), similarly, a bit error is added to the leading bit data A1. Similarly, also in the next measurement cycle L1, a bit error is added to the leading bit data A1. That is, even if a new measurement cycle L
Even if 1 comes, a bit error is always added only to the first bit data A1.

As described above, depending on the value of the disturbance target bit length A, the bit data A1, A2, ..., A9 included in the disturbance target bit length A may include bit data to which no bit error is added. become. This means that no error has occurred when only the D bit is monitored, for example.

The present invention has been made in view of the above circumstances. Instead of uniformly setting the actual measurement cycle indicated by the frequency division ratio set in the frequency divider to the specified bit length,
Depending on the bit length to be disturbed, by moving it to a value close to the specified bit length, all bit data included in the bit length to be disturbed are added bit errors evenly. It is an object of the present invention to provide a device for adding disturbance to a digital signal, which can improve the reliability of the error detection test of.

[0021]

In order to solve the above problems, the present invention provides a frequency dividing means for dividing a clock signal of a digital signal by a predetermined frequency dividing ratio, and a frequency dividing obtained by the frequency dividing means. In a digital signal disturbance adding device provided with a disturbance generating means for generating a disturbance bit at every constant bit period determined by a dividing ratio in a digital signal in synchronization with a clock signal, the dividing ratio of the dividing means is set to a digital signal. The bit length has a disjoint relationship with the disturbance target bit length that causes the disturbance bit in (1) and is set to a value equal to or closest to the specified bit length for error evaluation in the digital signal.

[0022]

In the digital signal disturbance adding device configured as described above, the frequency division ratio of the frequency dividing means for determining the timing for driving the disturbance generating means for generating the disturbance bit in the digital signal at every constant bit period is set to a digital value. It has a disjoint relation to the disturbance target bit length that causes the disturbance bit in the signal, and is set to a value equal to or closest to the specified bit length for error evaluation in the digital signal.

That is, assuming that the disturbance target bit length is A, the prescribed bit length is L, and the actual measurement bit length determined by the obtained frequency division ratio C is Lq, this measurement bit length Lq
And the disturbance target bit length A have a prime relationship with each other, and therefore have no common divisor other than 1. This means that A
In the case of <Lq, X = (Lq / A) is not an integer. Therefore, if K and E are integers, the measurement bit length Lq can be expressed by the equation (1).

Lq = K · A + E (1) Therefore, in the first measurement bit length Lq, when a bit error is added to the arbitrary bit data An included in the disturbance target bit length A, the next measurement bit is added. At the length Lq, no bit error is added to the corresponding bit data An of the disturbance target bit length A. A bit error is added to the bit data An + E, which is E bits after the corresponding bit data An. Thus, each time the measured bit length Lq arrives, the bit data to which the bit error is added is shifted backward by E bits.

In the equation (1), since E cannot be divided by A, bit data to which a bit error is added even when the integer number of measurement bit length Lq exceeding (A / E) arrives, for example. Does not match the bit data An in the first measurement bit length Lq. That is, (A
Only when the +1) th measurement bit length Lq arrives, a bit error is added to the very first bit data An.

Therefore, when the measurement bit length Lq of A times is completed, the bit error is evenly added once to all the bit data A1 to AA included in the disturbance target bit length A.

Then, among a large number of measurement bit lengths Lq satisfying such a relation with respect to the disturbance target bit length A, if a value that is equal to or closest to the specified bit length L is selected, for example, CCITT Standard error limit (S
A digital signal is obtained which is used to test whether ES) is satisfied.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a test system in which the digital signal disturbance adding device of the embodiment is incorporated.
The same parts as those of the test system shown in FIG. 4 are designated by the same reference numerals. Therefore, detailed description of the overlapping portions is omitted.

The test signal generating circuit 1 sends a test digital signal a consisting of a PCM signal as shown in FIG. 5 to the disturbance adding circuit 3 in the next disturbance adding device 10. In addition, the test signal generating circuit 1 uses the clock signal b used to create the output digital signal a as the disturbance adding device 10
It is sent to the internal frequency dividing circuit 4a. The frequency dividing circuit 4a is the control unit 1.
The frequency f of the clock signal b with the division ratio C specified from 1
And frequency-divided clock signal d having a frequency (f / C) is sent to the disturbance addition circuit 3. The pulse width of the divided clock signal d is set equal to the duration of each bit data of the digital signal a, that is, the pulse width of the clock signal b.

The disturbance adding circuit 3 is constructed, for example, as shown in FIG. P input from the test signal generation circuit 1
The digital signal a composed of the CM signal is input to one input terminal of the AND gate 3a, and is also input to another AND gate 3c via the inverter 3b. On the other hand, the divided clock signal d input from the frequency dividing circuit 4a is input to the other input terminal of the AND gate 3a via the inverter 3d and the other input terminal of the AND gate 3c via another inverter 3e. Is applied to. The output signals of the AND gates 3a and 3c are combined by the OR gate 3f to form a new digital signal a1 as the next device under test 5.
Sent to.

In the disturbance adding circuit 3 having such a configuration, the AND gate 3a is in the conducting state and the AND gate 3c is in the shut-off state while the divided clock signal d from the dividing circuit 4a is in the low (L) level period. Therefore,
The input digital signal a is the digital signal a1 as it is.
Is output as. Conversely, while the divided clock signal d from the frequency dividing circuit 4a is in the high (H) level period, the AND gate 3a is in the cutoff state and the AND gate 3c is in the conductive state, so that the input digital signal a is The sign is inverted by the inverter 3b and output as a digital signal a1.

That is, the disturbance adding circuit 3 sends the digital signal a input from the test signal generating circuit 1 to the device under test 5 as it is, unless the divided clock signal d of H level is input. Then, when the H-level divided clock signal d is input, the value of the bit data that is synchronized with the input of the divided clock signal d among the bit data forming the digital signal a is inverted. That is, the pseudo bit error is added to the digital signal a for each constant measurement bit length (bit period) Lq (= 1 / C) determined by the frequency division ratio C.

As a result, the digital signal a1 to which the pseudo bit error is added is input to the device under test 5. The device under test 5 performs the original data processing of the input digital signal a1 and checks whether or not there is a bit error in the digital signal a1 to detect a pit error of 1 second, When the ratio is on average shorter than the specified bit length L, the error detection signal e is sent to the next error measuring device 6. The error measuring device 6 statistically processes the error detection signal e to evaluate the error detection capability of the device under test 5.

The control unit 11 is composed of a kind of microcomputer, and a division ratio allocation table 12 is formed in the internal storage unit. This division ratio allocation table 12
For example, the frequency division ratio C1 corresponding to the actual measured bit lengths L1 and L2 for each combination of the prescribed bit length L defined in the error occurrence limit (SES) standard of CCITT and the disturbance target bit length A (= L1) and C2 (= L2) are stored.

As described above, the measured bit length L1 (= C1) is set to a value that is relatively prime to the disturbance target bit length A, and is less than the prescribed bit length L and closest to the prescribed bit length L. There is. The measurement bit length L2 (= C2) is
As described above, the bit length A is disjoint with respect to the disturbance target bit length A, and is equal to or greater than the prescribed bit length L when the prescribed bit length L is exceeded or equal to or greater than the prescribed bit length L.
Is set to the value closest to.

Specifically, the specified bit length L is 1
000 and the bit length A of the disturbance target is 9, the frequency division ratios C1 (= L1) and C2 (= L2) are 998 and 1000, respectively.
Becomes Further, when the prescribed bit length L is 1000 and the disturbance target bit length A is 256, the frequency division ratios C1 and C2 are 999 and 1001, respectively.

The case where the perturbation target bit length A = 9 will be described more specifically. Since 9 = 3 ^2, it is sufficient that the prime number 3 is not included when L 1 and L 2 are factored. Then, a value equal to or closest to the specified bit length L = 1000 may be selected. Since 1000 does not break at 3, L2 = 1000. Also, since the maximum number that is less than 1,000 and does not break at 3 is 998, L1 = 998.

In addition, since 256 = 2 ⁸ in the case of the disturbance target bit length A = 256, it is sufficient that the prime number 2 is not included in the factorization of L1 and L2. Then, a value equal to or closest to the specified bit length L = 1000 may be selected. 1001 does not break at 2, so L2
= 1001. Also, since the maximum number less than 1,000 and not broken by 2 is 999, L1 = 999.

A condition setting unit 13 such as a keyboard is connected to the control unit 11. Then, when the operator operates the condition setting unit 13 to specify the specified bit length L and the disturbance target bit length A and input the experiment start command, the control unit 11 inputs the bit lengths L and A.
Each division ratio C1. C2 is retrieved from the division ratio allocation table 12. Then, one frequency division ratio C1 is set in the frequency dividing circuit 4a for the first constant period T1, and the other frequency division ratio C2 is set in the frequency dividing circuit 4a for the next constant period T2.

In the digital signal disturbance adding device configured as described above, the prescribed bit length L = 1000 and the disturbance target bit length A = 9 are set, the test signal generating circuit 1 is activated, and the digital signal a is output. When you start, first, divide ratio C
Is set to C1 (= 998).

In this case, when a bit error is added to the first bit data A1 included in the disturbance target bit length A in the first measurement cycle (measurement bit length L1), the bit error is added in the next measurement cycle. From periodicity, 9 · X
From the minimum value X = 110 where ≧ 998 (998 = 9 × 110 +
8), a bit error is added to the 9th bit data A9. Similarly, in the next measurement cycle, a bit error is added to the eighth bit data A8. Thus, every time the measurement cycle arrives, bit errors are sequentially added to the respective bit data A9 to A1 included in the disturbance target bit length A, so that all the bit data A1 to A9 are added.
The bit error is evenly added to.

Next, when the fixed period T1 has elapsed, the frequency division ratio C is set to C2 (= 1000). In this case, if an error bit is added to the first bit data A1 included in the disturbance target bit length A in the first measurement cycle (measurement bit length L2), then in the next measurement cycle, due to its periodicity, , 9 · X ≧ 1000, the minimum value X = 112
From (1000 = 9 × 111 + 1), the second bit data A
An error bit is added to 2. Further, in the next measurement cycle, an error bit is added to the third bit data A3. In this way, each time the measurement cycle arrives,
Each bit data A1 to A included in the disturbance target bit length A
Since the bit errors are sequentially added to 9, the bit errors are evenly added to all the bit data A1 to A9.

In this way, when the specified bit length L and the disturbance target bit length A are determined, a value close to the specified bit length L and relatively prime to the disturbance target bit length A is actually measured bit length L1. It is set to L2, and this value is set to the frequency divider 4a. Therefore, bit errors are always added uniformly to each bit data A, ..., AA included in the disturbance target bit length A. As a result, it becomes possible to carry out a test for a more complete error detection function for the device under test 5.

In the embodiment, the relationship between the prescribed bit length L and the disturbance target bit length A is L = 1000, A = 9.
Although only the case of L = 1000 and A = 256 has been described, for example, in the PCM communication in the actual ISDN, the frequency (transmission speed) f of the clock signal b is 1.544 M.
Hz and 2.048 MHz, and the bit length of one frame in a digital signal (disturbance target bit length A) is 193
, 256. Then, the specified bit length L is 1000 and 1
When set to 000000, the measurement periods L1 and L2 under the above conditions are as shown in the table below.

[0046]

[Table 1] As described above, since the specified bit length L is a large value in actual operation, the difference between the actual measured bit lengths L1 and L2 and the specified bit length L is used when evaluating the error detection performance for the device under test 5. It doesn't matter at all.

FIG. 3 is a block diagram showing the schematic arrangement of a digital signal disturbance adding device according to another embodiment of the present invention. The same parts as those of the embodiment shown in FIG. 1 are designated by the same reference numerals. Therefore, detailed description of the overlapping portions is omitted.

In this embodiment, the disturbance adding device 10 of the embodiment is provided in the signal path of the digital signal a sent from the normal data transmitting device 21 and input to the data receiving device 22. Therefore, in this embodiment, the digital signal a is directly converted into the clock signal b in the device.
There is provided a clock signal reproducing circuit 23 for reproducing. Then, the clock signal b reproduced by the clock signal reproducing circuit 23 is input to the frequency dividing circuit 4a.

Even in the disturbance adding device 10 configured as described above, since the disturbance bit is added to the digital signal a1 input to the data receiving device 22 as the device under test under the above-mentioned conditions, the disturbance adding device of FIG. It is possible to obtain almost the same effect as the embodiment.

[0050]

As described above, according to the digital signal disturbance adding device of the present invention, the actual measurement cycle indicated by the frequency division ratio set in the frequency divider is not uniformly set to the specified bit length. Instead, it is set so as to have a disjoint relation with the measurement target bit according to the disturbance target bit length and be equal to or close to the specified bit length.
Therefore, bit errors are always evenly added to all bit data included in the disturbance target bit length, and the reliability of various error detection tests using this digital signal can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a measurement system incorporating a digital signal disturbance adding device according to an embodiment of the present invention;

FIG. 2 is a circuit diagram showing a disturbance adding circuit of the apparatus of the embodiment,

FIG. 3 is a block diagram showing a measurement system incorporating a digital signal disturbance adding device according to another embodiment of the present invention;

FIG. 4 is a block diagram showing a measurement system in which a conventional disturbance adding device is incorporated.

FIG. 5 is a frame configuration diagram showing a general digital signal,

FIG. 6 is a frame configuration diagram showing a digital signal in an ISDN line.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Test signal generating circuit, 3 ... Disturbance addition circuit, 4a ... Dividing circuit, 5 ... Device under test, 6 ... Error measuring device, 10 ... Disturbance adding device, 11 ... Control part, 12 ... Division ratio allocation table,
13 ... Condition setting section.

Claims (1)

[Claims] 1. A frequency dividing means (4a) for dividing a clock signal (b) of a digital signal (a) by a predetermined dividing ratio and a divided clock signal (d) obtained by this dividing means. In the disturbance adding device for a digital signal, which is provided with a disturbance generating means (3) for generating a disturbance bit at every constant bit period which is synchronously determined in the digital signal by the division ratio, the division ratio is the digital signal. A digital signal having a disjoint relation to a disturbance target bit length that causes a disturbance bit in and a value equal to or closest to a specified bit length for error evaluation in the digital signal. Disturbance addition device.