JPH10276176A - Error measurement device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To insert an error to a parallel data signal without losing random performance in the case that the data signal used for measuring a bit error produced in a digital communication line or the like is transmitted in parallel. SOLUTION: The device is provided with a counter circuit 3a whose number of stages is the same as parallel number of parallel data signals D1 -D16 , the error signal is given to the counter circuit 3a and the error is inserted to each parallel data signal from outputs of each stage of the counter circuit. Or the output of each stage of the counter circuit is given to a matrix circuit that changes input sequence and provides an output and the error is inserted to each parallel data signal by the output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error measuring device for inserting a bit error into a data signal used for measuring a bit error occurring in a digital communication line or the like, and more particularly, to a parallel data signal without impairing randomness. The present invention relates to an error measuring device that inserts an error into an error.

[0002]

2. Description of the Related Art First, a bit error measuring device will be described with reference to FIG.

FIG. 7 is a block diagram showing the principle of a bit error measuring device.

[0004] A pattern generation circuit 24 provided in the transmission section 21 generates a pseudo random pattern signal of bits of a predetermined length. The system under test 23 includes the transmission line 9 and the digital exchange 8, and transmits the pseudo-random pattern signal from the pattern generation circuit 24. The receiving unit 22
In response to the pattern signal, an error of the pattern signal generated in the system under test 23 is detected, and the configuration is as follows.

The reference pattern generation circuit 12 includes nine shift registers (SR1,..., SR9) and one EX-
The switch 14 is located on the A side, and a pattern signal passed through the system under test 23 is input. The error detection circuit 18 is an EX-OR circuit 1
7 and a shift register 13, and an EX-OR circuit (also called a coincidence circuit) 17 compares the output of the shift register 13 with the output of the reference pattern generation circuit 12,
Detects a match or mismatch between the two. Error counting circuit 1
5 is a mismatch (error) output from the error detection circuit 18
And coincidence are counted respectively. When it is confirmed that all bits of the pattern signal generated by the pattern generation circuit 24 have no error continuously, the synchronization circuit 16 operates the switch 14 to connect to the B side. As a result, the reference pattern generation circuit 12 runs on its own,
The same signal as the pattern signal of the pattern generation circuit 24 at that time is repeatedly generated as a reference pattern signal regardless of the input pattern to the input. This state is called a self-propelled state.

[0006] Upon receiving the reference pattern signal in the self-running state and the input pattern signal via the system under test 23, the error detector 18 and the error counting circuit 15 count errors.

The pattern generator 24 used in the bit error measuring device will be further described. The pattern generation circuit 24 has a PRBS system and a PRGM system.
The PRBS method is an acronym of Pseudo-Random Binaly Sequence, and corresponds to, for example, the reference pattern generation circuit 12 in a self-running state.

In this example, nine shift registers (same as binary) are used.
^A pseudo-random pulse pattern signal in which 1 and 0 are sets of substantially the same number can be generated with a period of ³¹ -1. The PRGM method generates a random pattern signal by using a programmable memory, and writes a pattern to be generated in a memory and sequentially reads the pattern to generate a random pattern signal. Both of these types are built in, and they are switched and used when necessary.
However, in this case, the reference pattern generation circuit 12 includes:
Instead of the configuration shown in FIG. 7, a device that outputs a pattern arbitrarily stored in a memory is generally used in the PRGM system, similarly to the pattern generation circuit 24.

In order to test the accuracy of bit error detection of such a bit error measuring device, a pattern generation circuit 2
It is necessary to check the system to be measured by intentionally inserting an error signal into the output signal of step No. 4. This pattern generation circuit 24 may be a plurality of parallel data signals.

Next, a conventional error measuring device for inserting an error signal into parallel data will be described with reference to FIGS. 8 and 9. FIG. FIG. 8 is a block diagram showing a conventional error measuring device.
FIG. 9 is a diagram showing conventional error insertion data for each channel.

The number of parallel data generating units 1 is n (16 in the figure).
) Data generating units 1-1 to 1-16. The n data generators 1-1 to 1-16 are equivalent to channels of a real line, for example, input to a digital exchange (system under test) 8 instead of data from each terminal of 16 channels. Things. Exchange 8
Multiplexes this and outputs it.

The first data generator 1-1 has a function equivalent to that of the pattern generator 24 of FIG.
Or PRGM pattern. 16th data generators 1-2 to 1-1 after the second data generator
6 has a function equivalent to that of the first data generator 1-1. For simplicity of description, the data to be generated is converted from the first data generator 1-1 to the sixteenth data generator 1. -16
It is assumed that the same data is generated in parallel at the same timing.

The error insertion section 6 is composed of 16 EX-OR circuits (6-1 to 6-16), and the EX-OR circuits (1-1 to 1-16) have respective data generation sections (1 to 1-16). −
When 1～1-16) is connected to an error signal (S _E), the data is inverted, i.e. outputs the inserted errors. The error generator 2 outputs an error signal (S _E ) for inserting an error into each data of the parallel data generator 1.

The operation of the conventional error measuring device thus configured will be described with reference to FIG.

In FIG. 9, numbers (1, 2, 3,...)
, 28,...) Indicate the order of the data output by the parallel data generator 1 and DATA · S indicates the content of the data output by the parallel data generator 1. This data is part of the 2 ⁹ -1 PRBS. As described above, the first data generator 1-1 to the sixteenth data generator 1
-16 indicates that the same data is generated at the same timing. DATA ・ 1, DATA ・ 2, DATA ・
3, ..., DATA.15 and DATA.16 are EX-OR circuits 6-1, 6-2, 6 of the error insertion unit 6, respectively.
-3,..., 6-15, 6-16 are output. The square frame indicates the error signal (S
_E ) indicates where the error was inserted.

In FIG. 9, the cycle of the error signal (S _E ) is set to be 10 times the cycle of the data (DATA1 to 16). For example, while the frequency of the data (DATA1 to 16) is 200 MHz, the error signal (S
The frequency of _E ) is 20 MHz, which is the rate at which one error is inserted for 10 data.

The parallel data (DATA1 to 16) is
Although not shown, multiplexed in a time division multiplexing method
The signal is converted to Hz signal and sent to the system under test.

As described above, in the conventional error measuring device, since the error signal is inserted into all data at the same time, the error is inserted in a biased manner, and the randomness of the error is impaired. .

In other words, when each data having an error shown in FIG. 9 is multiplexed by an exchange included in the system under test, the multiplexed data is data having an error that occurs regularly. there is a possibility.

In this case, the error factor generally occurring in the signal line system is a random factor such as the influence of the temperature or the natural environment. Hateful. Also,
In general, many exchanges have a function of correcting an error. However, if the error is a regular one, there is a risk that the original data may be misinterpreted and the error correction function may not function as intended. In order to test the function of the switch, it is desirable to input data having random errors.

[0021]

SUMMARY OF THE INVENTION An object of the present invention is to provide an error measuring apparatus for randomly generating errors in data input in parallel without impairing randomness.

[0022]

An error measuring device according to the present invention has a plurality (n) of data generators, outputs a plurality of data output by the data generator to a device under test, and In the error measuring device for measuring the error of the data output from the measuring device, the parallel signals (D _{1 to} D ₁ ) from the plurality of (n) data generators 1-1 to 1-n each outputting a predetermined signal are provided. _n ) and an error signal (S _{E1 to} S _En )
Error insertion portion when but entered with error insertion circuit 4-1 to 4-n of a plurality (n) to cause an error in the whole or in part different positions of each of the parallel signals (D ₁ ~D _n) 4, an error signal generator 2 for generating an error signal (S _E ) for inserting an error into the parallel signals (D _{1 to} D _n ), and the error insertion circuit for each of the plurality (n) of error insertion circuits. The error signal (S
_E ) is distributed to all or some of the plurality (n) of different positions, and is input to the error insertion unit as error signals (S _{E1 to} S _En ).

Further, in the error measuring device according to the present invention, the error insertion control section 3 sequentially transmits the error signals (S _E ) output from the error signal generation section 2 to the error signals (S _{E1 to} S _En). ) Are output, and the error signals (S _{E1 to} S _En ) output from the respective stages of the counter circuit are output from the plurality of (n) error insertion circuits 4-1 to 4-1. 4-n and input to the error insertion unit.

Further, in the error measuring device according to the present invention, the error insertion control section 3 sequentially transmits the error signals (S _E ) output from the error signal generation section 2 to the error signals (S _{E1 to} S _En). ) And the order of the error signals (S _{E1 to} S _En ) output by the respective stages of the counter circuit are changed to change the order of the plurality of error insertion circuits 4-1 to 4-4. And a matrix circuit 3b for distributing the signal to -n and inputting it to the error insertion unit.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention relates to an error measuring device for inserting an error into a parallel signal. The error signal is extracted at each stage while the error signal is sequentially transferred by a counter. An error is inserted into each of the parallel signals by the error signal at each stage.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the error measuring device according to the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram showing a first embodiment of an error measuring device according to the present invention, FIG. 2 is a time chart showing an output signal of an error insertion control section, and FIG. 3 is an error insertion data for each channel. FIG.

First, the configuration of the first embodiment of the error measuring device of the present invention will be described with reference to FIG.

The parallel data generator 1 generates a parallel signal. From the first data generator 1-1 to the sixteenth data generator 1-16, each of the 16 parallel data generators 1 to 16 generates a predetermined signal. It consists of a data generator. The error signal generator 2 generates an error signal (S _E ) for generating an error in each of the parallel data output from the parallel data generator 1.
Generate.

The error insertion unit 4 is composed of 16 EX-OR circuits (error insertion circuits) 4-1 to 4-16. One end of each of the EX-OR circuits 4-1 to 4-16 is the first.
Data generator 1-1 to the sixteenth data generator 1-1
6 and the other end is connected to each of 16 outputs of the error insertion control unit 3 described later.
The EX-OR circuits 4-1 to 4-16 provide 16 error signals (S _{E1 to} S _E1 ) output from the error insertion control unit 3.
_{According to E16} ), the signal from the parallel data generator 1 is inverted and output as an error.

The error insertion control unit 3 is a 16-stage counter, and outputs an error signal (S
_E ) while sequentially shifting the 16 error signals (S _E1 to S _E1 ).
S _E16 ) are output. This error signal (S _E1 to
S _E16 ) are input to the EX-OR circuits 4-1 to 4-16, respectively, and invert the data to generate an error (insert an error). Note that DATA1 to DATA16 are output signals into which an error has been inserted.

Next, the operation of this embodiment will be described with reference to FIGS.

The first data generator 1-1 of the parallel data generator 1 converts the data indicated by DATA0 in FIG.
Occurs at the speed of

The numbers at the top of FIG. 3 indicate the order in which data is output. This data is a part of the 2 ⁹ -1 cycle M-sequence PRBS signal generated by using nine binary circuits, but the present invention does not care about the content of the data.

For simplicity of explanation, it is assumed that the second data generator 1-2 to the sixteenth data generator 1-16 all output the same data (DATA0).

The error signal generator 2 generates a signal indicated by the error signal (S _E ) in FIG. The upper numbers in FIG.
It has the same meaning as the number in FIG. 3 and indicates the order in which data is output. Error signal (S _E) is, 200MHz
1/10 or 20 MHz for data speed of
It has become.

The error signal (S _E ) output from the error signal generator 2 is input to a 16-stage counter of the error insertion controller 3. FIG. 2 shows error signals (S _{E1 to} S _E16 ) output from each stage of the counter. The clocks are output with a delay of one clock in order with 200 MHz as a clock cycle. When the next error signal (S _E ) is output at number 11, the error signals (S _E1 to S _E1 to
S _E16 ) is output. EX-OR circuits 4-1 to 4-1
When the output of this counter (the output of the error insertion control unit 3) is input, the counter 6 outputs an error whose data is inverted at that timing.

As can be seen by superimposing FIG. 2 and FIG. 3, the parallel data is inverted at the positions where the error signals (S _{E1 to} S _E16 ) are output, that is, errors are detected at different positions. Has been inserted.

The part where the error is inserted is indicated by enclosing it.

As shown in FIG. 3, in the case of the present invention, there is no temporal correlation since the location where an error occurs differs for each data. In other words, it comes with randomness.

Next, another embodiment of the error insertion control section 3 will be described with reference to FIGS.

FIG. 4 is a block diagram showing another embodiment of the error insertion control unit 3 of the present invention, and FIG. 5 is a time chart showing output signals of another embodiment of the error insertion control unit 3 of the present invention. is there.

In this embodiment, the error insertion control unit 3 shown in FIG.
Is added with a matrix circuit 3b to provide more randomness for error insertion.

The matrix circuit 3b receives the 16 error signals (S _{E1 to} S _E16 ) output from the 16-stage counter as inputs and, for example, switches the lines (wirings) by a switcher gate circuit or the like, thereby obtaining the error signals. (S
_{E1 to} S _E16 ) are output to the terminals E _{1 to} E ₁₆ by changing the order.

An example in which the order is changed by the matrix circuit 3b will be described with reference to FIG. FIG. 5 shows that in this example, the third input is changed to the fifth output by the matrix circuit 3b,
The input is changed to the third output, the eighth input is changed to the eleventh output, and the eleventh output is changed to the eighth output. The order of the error signals output from the sixteen terminals of the matrix circuit 3b is changed. the first and second from the terminal E ₁ in order,
5,4,3,6,7,11,9,10,8,12,1
3, 14, 15, and 16.

Since this signal is input to each of the EX-OR circuits 4-1 to 4-16 as an error signal (S _{E1 to} S _E16 ), each parallel data is error-corrected in the order changed by the matrix circuit 3b. Is inserted.

Next, a second embodiment of the error measuring device according to the present invention will be described with reference to FIG. FIG. 6 is a block diagram showing a second embodiment of the error measuring device of the present invention.

The structure and operation of the second embodiment are the same as those shown in FIG.
Is essentially the same as the first embodiment described with reference to FIG.

First, comparing FIG. 6 with FIG. 1, the first to sixteenth data generators 1-1 to 1-16, the error signal generator 2, and the EX-OR circuit (error insertion circuit) 4
Since -1 to 4-16 are the same as those in FIG. 1, the description is omitted.

The 16-stage (n-stage) counter 3a in FIG.
The first counter 3-1 and the second counter 3-
.., The sixteenth counter 3-16, but the operation does not change at all. That is,
These sixteen counter 3 - 1 to 3 - are in each stage of the error signal S _E output from the error signal generation unit 2,
Each of the error signals (S _{E1 to} S _E16 ) is shifted to the next stage while being shifted by one stage, and the shifted error signals (S _{E1 to} S _E16 ) are EX.
-Output to the OR circuits 4-1 to 4-16 to insert errors into the data output by the data generators 1-1 to 1-16, respectively. The output signals of the counters 3-1 to 3-16 at each stage are error signals (S _{E1 to} S _E16 ), which are the same as those shown in FIG.

In the second embodiment, a one-stage counter and one
Since the error data insertion unit 5 is composed of the EX-OR circuits and the first error data insertion unit 5-1 to the sixteenth error data insertion unit 5-16 have the same configuration,
There are advantages such as easy design and manufacturing.

[0052]

The error measuring apparatus according to the present invention has a plurality (n) of data generators, outputs a plurality of data output from the data generator to the device under test, and outputs the data from the device under test. In the error measuring device for measuring the data error, the parallel signals (D ₁ ) from a plurality (n) of data generators (1-1 to 1-n) each outputting a predetermined signal.
ＤD _n ) and when the error signals (S _E1 ＳS _En ) are input, a plurality (n) of all or some of the parallel signals (D ₁ ＤD _n ) cause errors at different positions. An error insertion unit 4 having error insertion circuits 4-1 to 4-n; and an error signal generation unit 2 for generating an error signal (S _E ) for causing an error in the parallel signals (D _{1 to} D _n ). The error signal (S _E ) output by the error signal generator to each of the plurality of (n) error insertion circuits is distributed to all or some different positions of the plurality (n) of the error signals (S _E1 to S _E1 ). S _En ) is provided with the error insertion control unit 3 for inputting the error to the error insertion unit, so that an error can be randomly inserted into the parallel signal.

Further, in the error measuring device according to the present invention, the error insertion control section 3 sequentially transmits the error signal (S _E ) output from the error signal generation section 2 to the error signals (S _{E1 to} S _En). ), And outputs the error signals (S _{E1 to} S _En ) output from the respective stages of the counter circuit to the plurality of (n) error insertion circuits (4-1). ... 4-n) and input to the error insertion unit, errors can be inserted into the parallel signals in a predetermined order.

Further, the error measuring device according to the present invention comprises:
The error insertion control unit 3 includes a plurality (n) of counter circuits 3a that output error signals (S _{E1 to} S _En ) while sequentially transmitting the error signals (S _E ) output from the error signal generation unit 2, The order of the error signals (S _{E1 to} S _En ) output from the respective stages of the counter circuit is changed, distributed to the plurality of error insertion circuits (4-1 to 4-n), and input to the error insertion unit. Since the matrix circuit 3b is provided, error insertion for parallel signals can be arbitrarily set.

Generally, an error factor occurring in a signal line system is a random factor such as an effect of temperature or natural environment. Therefore, an error having low randomness makes it difficult to obtain a desired test result. In general, there are many devices which have a function of correcting an error, so that a device having a regular error may be mistaken for original data and an error correction function may not function as intended. The present invention can generate data having a random error for testing the function of the exchange so as not to cause such a problem.

Since a random error can be inserted into the data, the test can be performed in a state close to the actual line.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of an error measuring device according to the present invention.

FIG. 2 is a time chart illustrating an output signal of an error insertion control unit according to the present invention.

FIG. 3 is a diagram showing error insertion data for each channel according to the present invention.

FIG. 4 is a block diagram showing another embodiment of the error insertion control unit of the present invention.

FIG. 5 is a time chart showing output signals of another embodiment of the error insertion control unit of the present invention.

FIG. 6 is a block diagram showing a second embodiment of the error measuring device of the present invention.

FIG. 7 is a block diagram showing a conventional bit error measuring device.

FIG. 8 is a block diagram showing a conventional error measuring device.

FIG. 9 is a diagram showing conventional error insertion data for each channel.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Parallel data generation part 2 Error signal generation part 3 Error insertion control part 3a Counter circuit 3b Matrix circuit 4 Error insertion part 4-1 to 4-n Error insertion circuit 5 Error data insertion part

Claims (3)

[Claims] An apparatus has a plurality of (n) data generators, outputs a plurality of data output from the data generator to a device under test, and measures errors in the data output from the device under test. In the error measuring device, the parallel signals (D _{1 to} D ₁ ) from the plurality of (n) data generators (1-1 to 1-n) each outputting a predetermined signal are provided.
_n ) and when error signals (S _{E1 to} S _En ) are input, a plurality (n) of error insertions in which all or some of the parallel signals (D _{1 to} D _n ) cause errors at different positions. error insertion portion having a circuit (4-1~4-n) (4) and the parallel signal (D ₁ ~D _n) to the error signal generator for generating an error signal (S _E) for causing the error (2)
And distributing the error signal (S _E ) output by the error signal generator to each of the plurality of (n) error insertion circuits to all or some different positions of the plurality (n) of the error signals (S _E1). .. S _En ), and an error insertion control unit (3) for inputting the error to the error insertion unit. 2. The error insertion control unit (3) outputs error signals (S _{E1 to} S _En ) while sequentially transmitting the error signals (S _E ) output from the error signal generation unit (2). (N) stages of counter circuits (3a), and each stage of the counter circuits outputs an error signal (S _E1 .
S _En ) to the plurality of (n) error insertion circuits (4-1 to 4).
2. The error measuring apparatus according to claim 1, wherein the error is input to the error insertion unit after being assigned to -n). 3. The error insertion control section (3) outputs error signals (S _{E1 to} S _En ) while sequentially transmitting the error signals (S _E ) output from the error signal generation section (2). (N) the counter circuit (3a) and error signals (S _{E1 to} S _En ) output from the respective stages of the counter circuit.
Of the plurality of error insertion circuits (4-1 to 4-1).
The error measuring device according to claim 1, further comprising a matrix circuit (3b) for inputting the error signal to the error insertion unit after the input signal is input to the error insertion unit.