JP2011077709A - Apparatus and method for detection of signal generation - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus and method for detection of signal generation, capable of testing objects to be measured whose multiplication and separation can not be properly performed. <P>SOLUTION: The signal generation detection apparatus 101 and the signal generation detection method sequentially convert signals from a plurality of lanes into serial signals, and convert the serial signals into parallel signals of the same number as that of the lanes starting from an arbitrary position of the serial signals, to output each of the parallel signals to different lanes for testing the objects 91 to be measured. The apparatus 101 includes: a parallel signal output unit 11 which outputs specific continuation signals in which the same data stream repeats in a fixed period with different initial values from the plurality of lanes to the objects 91 to be measured, respectively; and a parallel signal detection unit 12 which receives and detects the parallel signals from the objects 91 to be measured for every lane. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a signal generation detection apparatus and a signal generation detection method, and more particularly to a signal generation detection apparatus and a signal generation detection method for testing an object to be measured that performs high-speed data communication.

  There has been proposed a signal generation detection device for testing an object to be measured for data communication (for example, see Patent Document 1). In the signal generation detection device described in Patent Document 1, an error is intentionally introduced into a digital data signal to generate a test signal, and the output of the system in response to the test signal is compared with a known digital data signal. Determine what kind of degradation has occurred due to the introduced error.

  On the other hand, in data communication, multiplexing for sequentially converting signals from a plurality of lanes into serial signals and separation for converting to parallel signals starting from an arbitrary position of the serial signals are performed.

Japanese Patent Application No. 2002-330192

  If the data communication speeds up, the data between the lanes may be skewed, or the order of the lanes separating the data may be shifted, so that multiplexing and separation may not be performed properly.

  The signal generation detection device described in Patent Document 1 does not consider the case where multiplexing or separation cannot be appropriately performed on the object to be measured. For this reason, it is impossible to appropriately determine what kind of deterioration has occurred due to the introduced error.

  Therefore, an object of the present invention is to provide a signal generation detection apparatus and a signal generation detection method capable of testing an object to be measured that cannot be multiplexed or separated appropriately.

  In order to achieve the above object, the signal generation detection apparatus and the signal generation detection method of the present invention output a specific continuous signal in which the same data string repeats at a constant cycle from a plurality of lanes to the device under test with different initial values. The parallel signal from the device under test is received and detected for each lane.

  Specifically, the signal generation detection device of the present invention sequentially converts signals from a plurality of lanes into serial signals, and converts the serial signals into the same number of parallel signals as the lanes starting from an arbitrary position of the serial signals. Is a signal generation detection device (101) for testing a device under test (91) that outputs to a different lane, and a specific continuous signal in which the same data string repeats at a constant cycle is transmitted from a plurality of lanes with different initial values. A parallel signal output unit (11) that outputs to the device under test and a parallel signal detection unit (12) that receives and detects the parallel signal from the device under test for each lane.

  The signal generation detection apparatus according to the present invention transmits and receives a specific continuous signal in which the same data string repeats at a constant period. In the case of an object to be measured that cannot be multiplexed or separated appropriately, the transmitted specific continuous signal is detected in any lane. At this time, since the detected signals are the same data string, an error can be detected if the transmitted data string and the received data string are synchronized even if the transmitted lane and the received lane are different. Therefore, it is possible to provide a signal generation detection device capable of testing an object to be measured that cannot be multiplexed or separated appropriately.

  In the signal generation detection device according to the present invention, the parallel signal output unit may further include an error addition circuit (24-2) for adding an error to a signal of an arbitrary lane among the plurality of lanes.

  In the signal generation detection device according to the present invention, the parallel signal output unit includes a plurality of signal generation circuits (31-1, 31-2,... 31-m () that generate a continuous signal in which the same data string repeats at a constant period. Wherein m is a positive integer greater than or equal to 2)) and a multiplexing circuit (32-1) for multiplexing the continuous signals generated by the signal generation circuit and outputting the specific continuous signal, The signal detection unit converts the parallel signals input to the lanes into the same number of parallel signals as the signal generation circuit, and outputs the parallel signals to different lanes; There may be provided the same number of separated signal detection circuits (34-1, 34-2,..., 34-m) as the signal generation circuits that receive and detect parallel signals for each lane.

  In the signal generation detection device of the present invention, the parallel signal output unit outputs a plurality of signal output circuits (21-1, 21-2,... 21) that output the specific continuous signal with different initial values for each lane. -N (where n is a positive integer greater than or equal to 2)).

  In the signal generation detection apparatus according to the present invention, the parallel signal output unit includes a signal output circuit (21-1) for outputting the specific continuous signal and a delay amount different from each other for the specific continuous signal from the signal output circuit. And the same number of delay circuits (22-1, 22-2,... 22-n (where n is a positive integer equal to or greater than 2)).

  The signal generation detection apparatus according to the present invention may include an error detection unit (13) that detects a code error included in the parallel signal detected by the parallel signal detection unit.

  Specifically, in the signal generation detection method of the present invention, signals from a plurality of lanes are sequentially converted into serial signals, converted to the same number of parallel signals as the lanes starting from an arbitrary position of the serial signal, Is a signal generation detection method for testing an object to be measured (91) that outputs a signal to different lanes, and a specific continuous signal in which the same data string repeats at a constant period is transmitted from a plurality of lanes with different initial values. And a parallel signal detection procedure for receiving and detecting a parallel signal from the device under test for each lane.

  The signal generation detection method of the present invention transmits and receives a specific continuous signal in which the same data string repeats at a constant period. In the case of an object to be measured that cannot be multiplexed or separated appropriately, the transmitted specific continuous signal is detected in any lane. At this time, since the detected signals are the same data string, an error can be detected if the transmitted data string and the received data string are synchronized even if the transmitted lane and the received lane are different. Therefore, it is possible to provide a signal generation detection method capable of testing an object to be measured that cannot be multiplexed or separated appropriately.

  In the signal generation detection method of the present invention, an error may be added to a signal in an arbitrary lane among the plurality of lanes in the parallel signal output procedure.

  In the signal generation detection method of the present invention, in the parallel signal output procedure, a continuous signal in which the same data string is repeated at a constant period is converted into a plurality of signal generation circuits (31-1, 31-2,... 31-m (however, m is a positive integer greater than or equal to 2)) and is generated at different periods, and the continuous signal generated by the signal generation circuit is multiplexed to output the specific continuous signal. In the parallel signal detection procedure, The input parallel signals may be converted into the same number of parallel signals as the signal generation circuit, output to different lanes, and the parallel signals may be received and detected for each lane.

  In the signal generation detection method of the present invention, in the parallel signal output procedure, a plurality of signal output circuits (21-1, 21-2,... 21-n (n is 2) that outputs the specific continuous signal. From the above positive integers)), the lanes may be output with different initial values.

  In the signal generation detection method of the present invention, in the parallel signal output procedure, the specific continuous signal from the signal output circuit (21-1) that outputs the specific continuous signal may be delayed by different delay amounts. .

  In the signal generation detection method according to the present invention, a code error included in the detected parallel signal may be detected in the parallel signal detection procedure.

  The above inventions can be combined as much as possible.

  ADVANTAGE OF THE INVENTION According to this invention, the signal generation detection apparatus and signal generation detection method which can test the to-be-measured object which cannot be multiplexed and isolate | separated appropriately can be provided.

It is a schematic block diagram which shows an example of the signal generation detection apparatus which concerns on Embodiment 1. FIG. 2 shows a first specific example of a parallel signal output unit according to the first embodiment. 2 shows a second specific example of a parallel signal output unit according to the first embodiment. The specific example of the parallel signal detection part which concerns on Embodiment 1 is shown. It is a schematic block diagram which shows an example of the signal generation detection apparatus which concerns on Embodiment 2. The 1st specific example of the parallel signal output part which concerns on Embodiment 2 is shown. 6 shows a second specific example of a parallel signal output unit according to the second embodiment. The specific example of the parallel signal detection part and error detection part which concern on Embodiment 2 is shown. An example of the signal output circuit which concerns on Embodiment 3 is shown. An example of the signal detection circuit which concerns on Embodiment 3 is shown.

  Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments described below are examples of the present invention, and the present invention is not limited to the following embodiments. In the present specification and drawings, the same reference numerals denote the same components.

(Embodiment 1)
FIG. 1 is a schematic configuration diagram illustrating an example of a signal generation detection device according to the present embodiment. The signal generation detection apparatus 101 according to the present embodiment includes a parallel signal output unit 11 and a parallel signal detection unit 12, and executes the signal generation detection method according to the present embodiment. Thereby, the signal generation detection apparatus 101 and the signal generation detection method according to the present embodiment test the device under test 91.

  The parallel signal output unit 11 outputs a specific continuous signal in which the same data string repeats at a constant cycle to the device under test 91 with different initial values from a plurality of lanes. The continuous signal is, for example, a PRBS (Pseudo Random Binary (bit) Sequence) signal. The number of lanes is not limited. For example, it may be 10 lanes or 20 lanes.

  If the initial value is 6 bits, the specific continuous signal is, for example, “... 101100101100101100. In this case, the parallel signal output unit 11 outputs a specific continuous signal S-1 “101100101100...” Having “101100” as an initial value from the first lane, and initially “010110” from the second lane. A specific continuous signal S-2 “010110100110...” As a value is output, and a specific continuous signal Sn “001011001011...” Having “001011” as an initial value from the nth lane is output. Output. In this manner, the parallel signal output unit 11 outputs a specific continuous signal “... 101100101100101100. In this embodiment, the initial value is 6 bits, but the initial value can be any number of bits.

  FIG. 2 shows a first specific example of the parallel signal output unit according to the present embodiment. The parallel signal output unit 11 includes, for example, n signal output circuits 21-1, 21-2,... 21-n as many as the lanes (n is a positive integer of 2 or more). The signal output circuits 21-1, 21-2, ... 21-n output specific continuous signals "... 101100101100101100 ..." with different initial values for each lane. For example, the signal output circuit 21-1 outputs a specific continuous signal S-1 “101100...”, The signal output circuit 21-3 outputs a specific continuous signal S-2 “010110. ... The signal output circuit 21-n outputs a specific continuous signal Sn “001011. As a result, the parallel signal output unit 11 can output a continuous signal in which the same data string repeats at a constant cycle from a plurality of lanes with different initial values.

  FIG. 3 shows a second specific example of the parallel signal output unit according to the present embodiment. The parallel signal output unit 11 includes, for example, the signal output circuit 21-1, and n delay circuits 22-1, 22-2,... Is provided. The signal output circuit 21-1 outputs a specific continuous signal “... 101100101100101100. The delay circuits 22-1, 22-2,... 22-n delay specific continuous signals from the signal output circuit 21-1 by different delay amounts. For example, the delay circuit 22-1 outputs a specific continuous signal S-1 “101100...”, The delay circuit 22-2 outputs a specific continuous signal S-2 “010110. The delay circuit 22-n outputs a specific continuous signal Sn “001011. As a result, the parallel signal output unit 11 can output data equivalent to outputting a continuous signal in which the same data string repeats at a constant period from a plurality of lanes with different initial values.

  The device under test 91 shown in FIG. 1 includes a multiplexing unit 81, an EO conversion unit 82, an OE conversion unit 83, and a separation unit 84. The multiplexing unit 81 sequentially converts signals from a plurality of lanes into serial signals. For example, a specific continuous signal S-1 from the first lane, a specific continuous signal S-2 from the second lane, and a specific continuous signal Sn from the nth lane are multiplexed. Convert to serial signal. The EO converter 82 converts the electrical signal from the multiplexer 81 into an optical signal and outputs it to the optical transmission line.

  Here, if the specific continuous signals S-1, S-2,... Sn are not high speed, the multiplexing unit 81 determines that the specific continuous signal S-1 from the first lane, the second A specific continuous signal S-2 from the lane,..., And a specific continuous signal Sn from the nth lane are converted into serial signals in this order. The EO conversion unit 82 outputs optical signals arranged in the order of a specific continuous signal S-1, a specific continuous signal S-2,... A specific continuous signal Sn to the optical transmission line.

  However, if the specific continuous signals S-1, S-2,... Sn are high speed, there may be a skew in the data between the lanes. In this case, the order of the lanes is shifted. For example, the multiplexing unit 81 performs a specific continuous signal S-2 from the second lane, a specific continuous signal S-1, from the first lane,. There are cases where a specific continuous signal S-n from n lanes is converted into a serial signal in order. Then, the EO conversion unit 82, when the specific continuous signals S-1, S-2,... Sn are high speed, as described above, the serial signal is the specific continuous signal S-2, the specific Continuous signals S-1,... Optical signals arranged in the order of specific continuous signals Sn are output to the optical transmission line.

  The OE conversion unit 83 converts an optical signal from the optical transmission path into an electrical signal and outputs a serial signal. The separation unit 84 converts the serial signal from the OE conversion unit 83 into a parallel signal. At this time, the separation unit 84 converts an arbitrary position of the serial signal into the same number of parallel signals as the lane, and outputs each to a different lane.

  Here, the separation unit 84 sends the specific continuous signal S-1 to the second lane, the specific continuous signal S-2 to the first lane,... The specific continuous signal Sn to the nth. May output to lane.

  Further, as described above, when the specific continuous signals S-1, S-2,... Sn are high speed, the OE conversion unit 83 specifies the specific continuous signal S-2, the specific continuous signal S-. In some cases, optical signals arranged in the order of specific continuous signals Sn are converted into electrical signals and serial signals are output. In this case, the separation unit 84 sends the specific continuous signal S-2 to the first lane, the specific continuous signal S-1 to the second lane,. Will be output to the lane.

  The parallel signal detector 12 receives and detects the parallel signal from the device under test 91 for each lane.

  FIG. 4 shows a specific example of the parallel signal detection unit according to the present embodiment. The parallel signal detection unit 12 includes n (n is a positive integer of 2 or more) signal detection circuits 23-1, 23-2,... 23-n. The signal detection circuit 23-1 receives and detects the parallel signal input to the first lane. The signal detection circuit 23-2 receives and detects the parallel signal input to the second lane. The signal detection circuit 23-n receives and detects the parallel signal input to the nth lane. Thereby, the parallel signal detection part 12 can receive and detect the parallel signal from the to-be-measured object 91 in a different lane.

  Here, the separation unit 84 sends the specific continuous signal S-2 to the first lane, the specific continuous signal S-1 to the second lane,..., The specific continuous signal Sn to the nth. May be output to the lane. In this case, the parallel signal detector 12 receives and detects the specific continuous signal S-2 in the first lane, receives and detects the specific continuous signal S-1 in the second lane, A specific continuous signal Sn is received and detected in the nth lane.

  In this embodiment, the specific continuous signal S-1 “101100...” And the specific continuous signal S-2 “010110...” Are continuous signals in which the same data string “101100” is repeated at a constant period. For this reason, even if the specific continuous signal S-2 is output to the first lane, the data string detected in the first lane is the specific continuous signal S-1 “101100. The same data string is different. Even if the specific continuous signal S-1 is output to the second lane, the data string detected in the second lane is the same data having a different initial value from the specific continuous signal S-2 “010110. Is a column.

  As described above, even if the data between the lanes is skewed or the order of the lanes of the data separated by the separation unit 84 is shifted, the specific continuous signal S-1, the specific continuous signal S-2, ..., each of the specific continuous signals Sn can be detected by any one of the signal detection circuits 23-1, 23-2, ... 23-n. Therefore, the parallel signal detection unit 12 can receive and detect a specific continuous signal S-1, a specific continuous signal S-2, ..., and a specific continuous signal Sn.

(Embodiment 2)
FIG. 5 is a schematic configuration diagram illustrating an example of a signal generation detection device according to the present embodiment. The signal generation detection device 102 and the signal generation detection method thereof according to the present embodiment are the same as those of the signal generation detection device 101 and the signal generation detection method according to the first embodiment. An error is added to an arbitrary signal among 1, S-2,..., And Sn, and an error is detected from a specific continuous signal received by the parallel signal detector 12. For this purpose, the signal generation detection apparatus 102 further includes an error detection unit 13, and the parallel signal output unit 11 includes an error addition circuit 24-2.

  The error addition circuit 24-2 adds an error to a signal in an arbitrary lane. The arbitrary lane is, for example, the second lane. The error is, for example, a code error. In the present embodiment, the case where the arbitrary lane is the second lane will be described. However, any lane from the first lane to the n-th lane may be used. By adding an error to an arbitrary lane, an error addition test can be performed on the DUT 91.

  FIG. 6 shows a first specific example of the parallel signal output unit according to the present embodiment. The parallel signal output unit 11 further includes an error addition circuit 24-2 in addition to the first form of the parallel signal output unit according to the first embodiment. The error addition circuit 24-2 adds an error to the specific continuous signal S-2 output from the signal output circuit 21-2 and outputs the added signal.

  FIG. 7 shows a second specific example of the parallel signal output unit according to this embodiment. The parallel signal output unit 11 further includes an error addition circuit 24-2 in addition to the second form of the parallel signal output unit according to the first embodiment. The error addition circuit 24-2 adds an error to the specific continuous signal S-2 delayed by the delay circuit 22-2 and outputs the added signal. At this time, the parallel signal output unit 11 outputs a continuous signal Sx having an arbitrary initial value to the error detection unit 13, which is a continuous signal in which the same data string is repeated at a constant period. For example, a specific continuous signal S-1 is output. As a result, the error detector 13 can detect a code error.

  As in the first embodiment, the DUT 91 shown in FIG. 5 sequentially converts signals from a plurality of lanes into serial signals, and converts the serial signals into the same number of parallel signals as the lanes starting from an arbitrary position of the serial signals. And output each to a different lane.

  The parallel signal detector 12 receives and detects the parallel signal from the device under test 91 for each lane. The error detection unit 13 detects a code error included in the parallel signal detected by the parallel signal detection unit 12. Thus, in the parallel signal detection procedure for receiving and detecting the parallel signal from the device under test 91 for each lane, a code error included in the detected parallel signal is detected.

  FIG. 8 shows a specific example of the parallel signal detection unit and the error detection unit according to the present embodiment. As in the first embodiment, each of the signal detection circuits 23-1, 23-2,... 23-n receives and detects the parallel signal input to each lane. The error detection unit 13 includes n (n is a positive integer of 2 or more) error detection circuits 25-1, 25-2,... Is detected.

  For example, the error detection circuit 25-1 acquires the signal detected by the signal detection circuit 23-1 and the specific continuous signal S-x output from the parallel signal output unit, and compares the two signals. The signal detected by the signal detection circuit 23-1 and the specific continuous signal S-x are continuous signals in which the same data string is repeated at a constant cycle, and are signals having different initial values. For this reason, a code error can be detected by comparing both signals in synchronization.

  Similarly to the error detection circuit 25-1, the error detection circuits 25-2,..., 25-n and the signals detected by the signal detection circuits 23-2,. The signal S-x is acquired and the two signals are compared. Thereby, the error detection circuits 25-2,..., 25-n can also detect code errors.

  By adopting the configuration according to the present embodiment, it is possible to perform a code error test even if the device under test 91 cannot be multiplexed or separated appropriately.

(Embodiment 3)
In the signal generation detection device and the signal generation detection method according to the present embodiment, the parallel signal output unit 11 described in the first embodiment or the second embodiment uses a plurality of signal generation circuits to generate specific continuous signals S-1, S. -2, ..., Sn are output. And the parallel signal detection part 12 demonstrated in Embodiment 1 or Embodiment 2 uses the same number of separation signal detection circuits as the signal generation circuit, and is used for specific continuous signals S-1, S-2,. Is received and detected.

  FIG. 9 shows an example of a signal output circuit according to this embodiment. The signal output circuit 21-x according to the present embodiment is an arbitrary signal output circuit among the signal output circuits 21-1, 21-2, ... 21-n. If the signal output circuit 21-x is the signal output circuit 21-1, the signal output circuit 21-x outputs a specific continuous signal S-1.

  The signal output circuit 21-x includes m (m is a positive integer greater than or equal to 2) signal generation circuits 31-1, 31-2, ... 31-m, and a multiplexing circuit 32-1. Each of the signal generation circuits 31-1, 31-2, ... 31-m generates a signal having a different initial value, which is a continuous signal in which the same data string is repeated at a constant period. The multiplexing circuit 32-1 multiplexes signals generated by the signal generation circuits 31-1, 31-2, ... 31-m, and outputs a specific continuous signal Sx. Thereby, a specific continuous signal S-x having an arbitrary initial value can be output.

  In the present embodiment, since the specific continuous signal Sx is generated using the m signal generation circuits 31-1, 31-2, ... 31-m, 1 / of the specific continuous signal Sx. It is possible to use signal generation circuits 31-1, 31-2, ... 31-m having a data rate of m. Thereby, the specific continuous signal Sx can be easily increased in speed.

  FIG. 10 shows an example of a signal detection circuit according to this embodiment. The signal detection circuit 23-x according to the present embodiment is an arbitrary signal detection circuit among the signal detection circuits 23-1, 23-2,... 23-n. If the signal detection circuit 23-x is the signal output circuit 23-1, the parallel signal from the device under test 91 is received and detected in the first lane.

The signal detection circuit 23-x includes the separation circuit 33-1 and the same number of separation signal detection circuits 34-1, 34-2, ... as the signal generation circuits 31-1, 31-2, ... 31-m. 34-m.
The separation circuit 33-1 converts the parallel signal input to one of the lanes of the parallel signal detection unit (reference numeral 12 shown in FIGS. 1 and 5) into signal generation circuits 31-1, 31-2,... Convert to the same number of parallel signals as -m and output each to different lanes. For example, the parallel signal input to the first lane is converted into m parallel signals and further output from the first lane to each of the mth lanes.

  The separation signal detection circuits 34-1, 34-2, ... 34-m receive and detect the parallel signal from the separation circuit 33-1 for each lane. For example, the separation signal detection circuit 34-1 receives and detects the parallel signal output from the separation circuit 33-1 to the first lane. Similarly to the separation signal detection circuit 34-1, the separation signal detection circuit 34-2, ... 34-m receives and detects the parallel signal output from the separation circuit 33-1 to each lane. As a result, the separation signal detection circuits 34-1, 34-2, ... 34-m receive and detect the continuous signals generated by the signal generation circuits 31-1, 31-2, ... 31-m. can do.

  In the present embodiment, since the specific continuous signal Sx is received and detected using the m separated signal detection circuits 34-1, 34-2, ... 34-m, the specific continuous signal S- The separation signal detection circuits 34-1 34-2,..., 34-m having a data rate of 1 / m of x can be used. Thereby, it is possible to easily increase the speed of the specific continuous signal Sx.

  When the signal detection circuit 23-x according to the present embodiment is applied to the signal detection circuits 23-1, 23-2,... 23-n according to the second embodiment, the error detection unit 13 illustrated in FIG. .., 34 -m detect code errors included in the parallel signals detected by the separated signal detection circuits 34-1, 34-2,. In this case, the error detection unit 13 acquires the parallel signal detected by the separation signal detection circuit 34-1 and the signal from the signal generation circuit 31-1, and compares the two signals. The same applies to the parallel signals detected by the separation signal detection circuits 34-2,..., 34-m and the signals from the signal generation circuits 31-2,. Thereby, a code error can be detected.

  The signal generation detection apparatus of the present invention can be applied to the information communication industry.

11: parallel signal output unit 12: parallel signal detection unit 13: error detection units 21-1, 21-2, 21-n, 21-x: signal output circuits 22-1, 22-2, 22-n: delay circuits 23-1, 23-2, 23-n, 23-x: signal detection circuit 24-2: error addition circuit 25-1, 25-2, 25-n: error detection circuit 31-1, 31-2, 31 -M: signal generation circuit 32-1: multiplexing circuit 33-1: separation circuits 34-1, 34-2, 34-m: separation signal detection circuit 81: multiplexing unit 82: EO conversion unit 83: OE conversion unit 84: Separation unit 91: Device under test 101, 102: Signal generation detection device

Claims (12)

A test of a device under test (91) that converts signals from a plurality of lanes into serial signals in sequence, converts the serial signals to the same number of parallel signals as the lanes starting from an arbitrary position, and outputs them to different lanes. A signal generation detection device (101) for performing
A parallel signal output unit (11) for outputting a specific continuous signal in which the same data string repeats at a constant period to the device under test with different initial values from a plurality of lanes;
A parallel signal detector (12) for receiving and detecting a parallel signal from the device under test for each lane;
A signal generation detection device comprising: The parallel signal output unit is
The signal generation detection device according to claim 1, further comprising an error addition circuit (24-2) for adding an error to a signal of an arbitrary lane among the plurality of lanes. The parallel signal output unit is
A plurality of signal generation circuits (31-1, 31-2,... 31-m (where m is a positive integer of 2 or more)) that generates continuous signals in which the same data string repeats at a constant period;
A multiplexing circuit (32-1) that multiplexes continuous signals generated by the signal generation circuit and outputs the specific continuous signal;
The parallel signal detector is
A separation circuit (33-1) that converts parallel signals input to the lanes into the same number of parallel signals as the signal generation circuit and outputs the parallel signals to different lanes;
The same number of separation signal detection circuits (34-1, 34-2, ... 34-m) as the signal generation circuits that receive and detect parallel signals from the separation circuit for each lane;
The signal generation detection device according to claim 1 or 2. The parallel signal output unit is
A plurality of signal output circuits (21-1, 21-2,... 21-n (where n is a positive integer of 2 or more)) that outputs the specific continuous signal with different initial values for each lane. The signal generation detection apparatus according to any one of claims 1 to 3. The parallel signal output unit is
A signal output circuit (21-1) for outputting the specific continuous signal;
The same number of delay circuits (22-1, 22-2,..., 22-n as the lanes for delaying the specific continuous signal from the signal output circuit by different delay amounts (where n is a positive number of 2 or more) Integer)), and
The signal generation detection apparatus according to claim 1, further comprising:   The signal generation detection device according to any one of claims 1 to 5, further comprising an error detection unit (13) that detects a code error included in a parallel signal detected by the parallel signal detection unit. A test of the device under test (91) that converts signals from a plurality of lanes into serial signals in order, converts the serial signals into the same number of parallel signals as the starting lane, and outputs them to different lanes. A signal generation detection method for performing
A parallel signal output procedure for outputting a specific continuous signal in which the same data string repeats at a constant period from a plurality of lanes to the DUT with different initial values;
A parallel signal detection procedure for receiving and detecting a parallel signal from the device under test for each lane;
The signal generation detection method which has these in order. In the parallel signal output procedure,
The signal generation detection method according to claim 7, wherein an error is added to a signal of an arbitrary lane among the plurality of lanes. In the parallel signal output procedure,
Continuous signals that repeat the same data string at a constant cycle are generated from a plurality of signal generation circuits (31-1, 31-2, ... 31-m (where m is a positive integer greater than or equal to 2)) at different cycles. And
Multiplex the continuous signal generated by the signal generation circuit to output the specific continuous signal,
In the parallel signal detection procedure,
The parallel signal input to the lane is converted into the same number of parallel signals as the signal generation circuit, and each is output to a different lane,
Receiving and detecting the parallel signal for each lane;
The signal generation detection method according to claim 7 or 8. In the parallel signal output procedure,
From the plurality of signal output circuits (21-1, 21-2,... 21-n (where n is a positive integer equal to or greater than 2)) that outputs the specific continuous signal, different initial values for each lane 10. The signal generation detection method according to claim 7, wherein the signal generation detection method outputs the signal. In the parallel signal output procedure,
The signal generation detection method according to claim 7, wherein the specific continuous signal from the signal output circuit (21-1) that outputs the specific continuous signal is delayed by different delay amounts.   The signal generation detection method according to claim 7, wherein a code error included in the detected parallel signal is detected in the parallel signal detection procedure.

Images