JP2000092028A - Random error generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a bit error at a desired position in a PN pattern signal by inserting an error signal to a bit location of the PN pattern signal specified by the output of a 1st decode section. SOLUTION: The random error generating circuit is provided with a decode circuit 34 that decodes an optional m-bit output of an exclusive OR combination circuit 33 into a pattern output in a corresponding n-bit. A pattern output in n-bits from the decode circuit 34 is given to an AND circuit 35, where the pattern output is ANDed with an error generating signal 37 and an error signal 38 is generated. The error signal 38 is given to an exclusive OR circuit 39, where the signal 38 is exclusively ORed with an n-parallel PN pattern signal 36 from the exclusive OR combination circuit 33 and an n-parallel PN pattern signal 36 including the error signal 38 whose bit location is not fixed is obtained. That is, a logic of a bit of the n-parallel PN pattern signal 36 at a bit location corresponding to the logic of the n-bit error signal 38 is inverted in the exclusive OR combination circuit 33.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PN used in a communication device or a measuring device for performing digital processing.
The present invention relates to a pattern (pseudo-random pattern) generating circuit, a parallel data transmission path, and a random error generating circuit used for a data assurance test and a quality assurance test of a storage element such as a RAM (random access memory).

[0002]

2. Description of the Related Art Conventionally, a circuit for forcibly generating an error in a test for confirming the normality of a transmission line has been used. In this test, the normality of the target device is tested by outputting the generated PN pattern to the transmission path, intentionally generating a bit error, and confirming the detection. In some cases, an error is forcibly generated in transmission data as a deterioration test of a transmission path.

FIG. 11 shows a basic configuration diagram of a conventional PN pattern generation circuit. The PN pattern generation circuit shown in FIG. 11 has 15 flip-flops 11 (FF1 to FF1).
5) and one exclusive OR gate (EOR) 12. The pseudo-random pattern output of this PN pattern generation circuit is supplied to a fifteenth stage flip-flop (FF1).
5) is obtained from the output terminal.

In such a serial processing PN pattern generation circuit, the speed of an output signal is controlled by an input clock (
CLK1), and when this clock (CLK1) is very fast, it is difficult to generate a normal PN pattern due to various conditions around the clock.

[0005] Therefore, the P of serial processing as shown in FIG.
A PN pattern generation circuit by parallel processing is known for the N pattern generation circuit. FIG. 12 shows an example of the basic configuration. This is an n-parallel version of the PN pattern generation circuit having a plurality of serial stages in FIG. In FIG.
Each of the flip-flop circuits 21 and 22 has eight flip-flops connected in parallel.

Further, the exclusive OR combination circuit 23
From the output signal of the flip-flop circuit 22, n parallel P
An N pattern signal 25 is generated and output. Arbitrary 8 bits of the n parallel are input to the flip-flop circuits 21 and 22. The flip-flop circuit 21 receives the clock CLK 40 and 7 bits out of the 8 bits, and the output thereof is connected to the flip-flop circuit 22.

The output signal of the flip-flop circuit 21 and the remaining one of the eight bits are input to the flip-flop circuit 22, and the output is connected to the exclusive-OR combination circuit 23.

Further, since only one bit in the PN pattern generated by the above circuit is arbitrarily used as an error signal,
The exclusive OR circuit 24 inverts any one bit of the PN pattern signal 25 according to an external error occurrence signal 37 to generate a bit error.

However, the PN by the parallel processing shown in FIG.
In the pattern generation circuit, a bit error always occurs only in the same bit, so that it is not suitable for a case where an error needs to be generated in an arbitrary place, such as in a quality deterioration test of a transmission line.

Therefore, a method is conceivable in which the error occurrence interval is arbitrarily changed using the generated PN pattern signal to make it appear as if the error insertion position is arbitrarily generated.

This method is effective when PN pattern signals are continuously inserted. However, for example, when the insertion position of the PN pattern signal is limited to only a part of a certain data string, an error may occur in a portion where the PN pattern signal is not inserted.

[0012]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a random error generating circuit capable of generating a bit error in a PN pattern signal at an arbitrary position in order to solve the above-mentioned problems. It is in.

Further, the present invention relates to a PN pattern (pseudo random pattern) generating circuit used in a communication apparatus for performing digital processing, a measuring instrument, or the like.
An object of the present invention is to provide a random error generating circuit capable of generating a bit error at an arbitrary position in a pattern signal.

Another object of the present invention is to provide a PN pattern (pseudo random pattern) generating circuit used for a data assurance test and a quality assurance test of a parallel data transmission path and a storage element such as a RAM (random access memory). The present invention is to provide a random error generating circuit capable of generating a bit error in an arbitrary position in a PN pattern signal.

[0015]

The basic structure of a random error generating circuit for achieving the above object of the present invention is as follows: a generating section for generating an n-bit parallel PN pattern signal; and an m-bit in the generated PN pattern signal. And a PN specified by an output of the first decoding unit.
An error insertion unit for inserting an error signal into a bit position of the pattern signal is provided.

Further, as one aspect, a counter is provided in which an initial value can be arbitrarily set, and a counting timing of a clock signal is controlled by an error generating signal for enabling counting. The error signal is inserted into the bit position of the PN pattern signal specified by the output of the first decoding unit at the timing of the carry signal.

In another aspect, the apparatus further comprises a second decoding section for decoding (nm) bits in the n-bit parallel PN pattern signal.
A comparing unit that detects a match of the output of the second decoding unit, wherein the error insertion unit is specified by the output of the first decoding unit at a timing at which the comparing unit detects a match;
An error signal is inserted into a bit position of the PN pattern signal.

As another configuration, a generator for generating an n-bit parallel PN pattern signal, a first counter whose initial value can be set arbitrarily, the PN pattern signal, and a count value of the first counter The comparison unit includes a comparison unit that detects a matching bit, and an error insertion unit that inserts an error signal at a bit position of the PN pattern signal at which the comparison unit detects a match.

As one aspect, the above-mentioned configuration further comprises a second counter whose initial value can be arbitrarily set and whose count timing of a clock signal is controlled by an error generation signal that enables counting. The error insertion unit inserts an error signal at a bit position of the PN pattern signal where a match is detected by the comparison unit at a timing of the carry signal of the second counter.

Further features of the present invention will become apparent from the following description of embodiments.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or similar components will be described with the same reference numerals or reference symbols.

FIG. 1 is a conceptual diagram of an embodiment of the present invention. In FIG. 1, the PN pattern generation unit 30
Flip-flop circuits 21 and 22 in the configuration shown in FIG.
And, it is the same as the part configured by the exclusive OR combination circuit 23.

Therefore, similarly to the configuration of FIG. 12, the flip-flop circuits 31 and 32 are respectively composed of seven and eight flip-flops connected in parallel. The exclusive OR combination circuit 33 includes a flip-flop circuit 3
The outputs of the eight flip-flops 2 are input.

The exclusive OR combination circuit 33 combines the eight inputs from the flip-flop circuit 32 to generate an n-bit pattern output as an n-parallel PN pattern signal 36. Next, as a feature of the present invention, there is provided a decoding circuit 34 for decoding an arbitrary m-bit output of the n-bit pattern output of the exclusive OR combination circuit 33 into a corresponding n-bit pattern output.

The logical product of the n-bit pattern output of the decode circuit 34 and the error occurrence signal 37 is taken in the logical product circuit 35, and an error signal 38 is generated. The error signal 38 is input to the exclusive OR circuit 39, and the exclusive OR with the n parallel PN pattern signal 36 from the exclusive OR combination circuit 33 is obtained.

That is, in the exclusive OR combination circuit 33, the logic of the bit of the n parallel PN pattern signal 36 at the bit position corresponding to the logic "1" of the n bit error signal 38 is inverted.

Here, in the configuration of FIG.
The input of 4 is a part of the n-parallel PN pattern signal 36 and changes according to the n-parallel PN pattern signal 36. For this reason, the pattern of the error signal 38 obtained from the AND circuit 35 at the timing of the error generation signal 37 is not constant due to the n-parallel PN pattern signal 36. Therefore, it is possible to obtain the n-parallel PN pattern signal 36 including the error signal whose bit position is not fixed from the exclusive OR circuit 39.

FIG. 2 is a detailed configuration example of the embodiment of the basic configuration block diagram of FIG. FIG. 3 is an operation time chart corresponding to FIG. 3 correspond to the numbers of the corresponding parts in FIG.

In the embodiment shown in FIG. 2, each of the flip-flop circuit 31 having seven flip-flops and the flip-flop circuit 32 having eight flip-flops are the flip-flop circuits 31 and 32 of the PN pattern generator 30 in FIG. Corresponding to The exclusive OR combination circuit 3 corresponding to the exclusive OR combination circuit 33 of the PN pattern generation unit 30 in FIG.
3 has eight exclusive OR gates (EOR).

The exclusive OR combination circuit 33 receives an arbitrary one of the seven outputs of the flip-flop circuit 31 and the output of the flip-flop circuit 32. An exclusive OR is calculated between adjacent outputs of the flip-flop circuit 32, and an 8-bit parallel PN pattern signal 36 is output.

7 bits of the PN pattern signal 36 are fed back to the flip-flop 31. The output of the flip-flop 31 is connected to the input of the flip-flop 32 together with the remaining one bit of the PN pattern signal 36.

Further, any three bits of the PN pattern signal 36 are input to a decoding circuit 34. An 8-bit decode signal 411 is obtained from the decode circuit 34.
That is, the decoding circuit 34 outputs the PN pattern signal 36
Out of eight patterns corresponding to an arbitrary combination of three bits as a decoded signal 411,
A table is stored in a ROM as an embodiment.

The differential circuit 400 receives the clock CLK 40 and an externally generated error signal 37. And
The differentiating circuit 400 outputs a differentiated signal 410 in which the timing of the error occurrence signal 37 is accurately synchronized with the clock CLK40. This differential signal 410 is calculated by the logical product combination circuit 3
5 is input.

The AND combination circuit 35 outputs the decode signal 4
A bit that causes an error in the PN signal 36 is determined from the logical product of 11 and the differential signal 410. That is,
The logical product combination circuit 35 has an AND gate corresponding to the number of bits of the decode signal 411.

In the circuit shown in FIG. 2, the logical product combination circuit 35 has eight AND gates, and one of the eight AND gates has one input terminal to which each of the eight bits of the decode signal 411 is input. The differential signal 410 is commonly input to the other input terminals of the eight AND gates.

Therefore, from the logical product combination circuit 35,
At the timing of the differential signal 410, a pattern output of the decode signal 411 is obtained. The output of the AND combination circuit 411 is input to the exclusive OR combination circuit 39 together with the PN pattern signal 36. Therefore, the bit of the PN pattern signal 36 at the bit position corresponding to the logic “1” of the decode signal 411 is inverted, inserted as an error signal, and output from the exclusive OR combination circuit 39.

Here, in the configuration of the embodiment shown in FIG.
The insertion timing of the error signal inserted into the N pattern signal is only the timing at which the error occurrence signal 37 is input. However, if an error signal can be periodically inserted during generation of the PN pattern signal, the applicable range of the device can be expanded.

FIG. 4 is a block diagram showing the configuration of an embodiment based on the configuration of FIG. 2 corresponding to such a demand. In FIG. 4, for simplicity, flip-flop circuits 31 and 32 and an exclusive OR circuit 33 are composed of PN
This is shown as a pattern generator 30.

As a feature of the embodiment of FIG. 4, a circuit corresponding to the differentiating circuit 400 of FIG. 2 is replaced by a circuit composed of an n-stage counter 401 for performing counting up to 2n and an OR circuit 402. The n-stage counter 401
When the error generation signal 37 is loaded by the R circuit 402 at the timing when the enable signal ENB is added,
The counter is counted from the initial value 500 to 2n. A carry signal is output when counting up to 2n, and at this timing, counting is performed from the counter initial value 500 to 2n.

Therefore, according to the embodiment of FIG. 4, the position of the error bit can be made arbitrary based on the principle of the embodiment of FIG.
From the n-stage counter 511, the clock C
Every time the LK 407 counts up to 2n, an error timing signal 411 corresponding to the differential signal 410 is sent to the AND circuit 35, and the insertion timing of the error signal can be repeated periodically, for example, once a second.

Further, by setting the counter initial value 500 from outside, it is possible to arbitrarily set an error occurrence interval.

FIG. 5 is a time chart showing the insertion timing of an error signal that is periodically repeated at such an arbitrary bit position and at an arbitrary error occurrence interval in FIG. A state where an error bit is inserted at the timing of the counter carry 411 is shown.

FIG. 6 shows still another embodiment. In the embodiment of FIG. 4, the interval at which the insertion is repeated is periodic, whereas the error signal can be inserted at an irregular, that is, at an arbitrary period. FIG.

In FIG. 6, a separate decoding circuit 341 is added to the configuration of FIG. As an example, the decoding circuit 34 decodes the upper three bits of the PN pattern signal from the PN generator 30. The decoded output is sent to the logical product combination circuit 35. Therefore, such processing is as described in FIG. Further, FIG.
In, the added decoding circuit 341 decodes the lower 5 (8-3) bits of the PN pattern signal from the PN generator 30. On the other hand, an external error occurrence signal 3
7, n-stage counter 401, n = 5 as an embodiment
Starts counting the clock CLK40.

The decode output of the decode circuit 341 and n
The count value of the stage counter 401 is input to the comparison circuit 342. These are compared in a comparison circuit 342,
When they match, the error timing signal 41 in FIG.
1 is output.

The coincidence signal, that is, the error timing signal 411 is input to the logical product combination circuit 35. Subsequent operations are the same as in the embodiment of FIG. 6, the timing at which the decode output of the decode circuit 341 matches the count value of the n-stage counter 401 is irregular. Therefore, it is possible to randomly insert an error signal into the PN pattern signal as compared with the embodiment of FIG.

FIG. 7 is a block diagram showing the configuration of still another embodiment. It comprises a PN generator 30, an eight-stage counter 401, a comparator 343, an AND combination circuit 35, and an exclusive OR combination circuit 39.

The comparator 343 receives the output from the PN generator 30 and the output of the eight-stage counter and compares them for each corresponding bit. The error occurrence signal 37 converted into a pulse signal by the differentiating circuit 400 and the output of the comparator 343 are input to the logical product combination circuit 35.

In the logical product combination circuit 35, an error signal is output in accordance with the bit for which both have become logical "1". Therefore, in the exclusive OR combination circuit 39, the PN from the PN generation block diagram 30 corresponding to the bit in which both of the inputs of the comparator 343 become logic "1" are obtained.
An error is generated by inverting the bit at the bit position of the pattern signal. This makes it possible to cause an error to occur in a plurality of bits of the PN pattern signal of the same bit string. The generation of an error in a plurality of bits of the PN pattern signal is the same in the embodiments of FIGS. 2, 4, and 6 described above.

The feature of the embodiment of FIG. 7 is that by changing the counter initial value 500 from the outside, it is possible to arbitrarily change the frequency of occurrence of a plurality of errors that occur simultaneously. That is, by changing the counter initial value 500, it is possible to change the probability of the number of bits matching the PN pattern signal from the PN pattern generation unit 30 in the comparator 43. Thereby, the frequency of occurrence of a plurality of errors that occur simultaneously can be changed.

FIG. 8 shows an embodiment in which the embodiment of FIG. 7 is further improved so that the number of times of occurrence of a plurality of errors can be changed. That is, an n-stage counter 402 is provided instead of the differentiating circuit 400 in FIG.

Further, the error generation signal 37 from the outside is used as the enable signal ENB, and the carry output of the n-stage counter 402 to which the counter initial value 501 is input from the outside, and the error generation timing to be input to the logical product combination circuit 35 Signal. By changing the counter initial value 501, the carry output interval is changed, so that the error occurrence interval can be arbitrarily changed.

FIG. 9 is an operation time chart of FIG. 8 showing how the error occurrence interval is arbitrarily changed. The state where error bits are inserted at arbitrary intervals and at arbitrary bit positions is shown.

FIG. 10 is a block diagram showing a configuration example applied to a parity circuit as an application example of the present invention. This configuration is different from the configuration of the embodiment of FIG.
Is omitted and PN pattern data is replaced with parallel signals DI0 to DI7 from outside.

That is, in FIG. 10, an exclusive-OR combination circuit 39 is provided by combining parallel signals DO0 to DO7 obtained by inserting error signals at predetermined intervals into parallel signals DI0 to DI7.
Output from At the same time, an exclusive OR circuit 600 is provided, and the exclusive OR of the parallel signals DI0 to DI7 is obtained and output as a parity signal 601.

The parallel signal DO into which the error signal has been inserted
0 to DO7 and the parity signal 601 are transmitted to the transmission path,
Alternatively, write to memory. By receiving this on the receiving side of the transmission path, or reading from the memory and testing, the normality of the transmission path or the memory can be measured together with the normality of the test apparatus.

[0057]

As described above with reference to the drawings, the present invention can generate a bit error in a PN pattern signal at any position and at any interval. Thereby, the parallel data transmission path and RA
More preferable data assurance tests and quality assurance tests can be performed on storage elements such as M (random access memory).

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of an embodiment of the present invention.

FIG. 2 is a detailed configuration example of an embodiment of the basic configuration block diagram of FIG. 1;

FIG. 3 is an operation time chart corresponding to FIG. 2;

FIG. 4 is a block diagram of an embodiment based on the configuration of FIG. 2;

FIG. 5 is a time chart showing an insertion timing of an error signal that is periodically repeated at an arbitrary bit position and at an arbitrary error occurrence interval in FIG. 4;

FIG. 6 is a configuration diagram of still another embodiment, in which an error signal can be inserted at an arbitrary cycle.

FIG. 7 is a block diagram of a configuration of still another embodiment.

8 is an embodiment in which the embodiment of FIG. 7 is further improved so that the number of times of occurrence of a plurality of errors occurring simultaneously can be changed.

FIG. 9 is an operation time chart of FIG. 8 showing how an error occurrence interval is arbitrarily changed.

FIG. 10 is a block diagram of a configuration example applied to a parity circuit as an application example of the present invention.

FIG. 11 is a basic configuration diagram of a conventional PN pattern generation circuit.

FIG. 12 is a basic configuration diagram of a PN pattern generation circuit by parallel processing.

[Explanation of symbols]

 Reference Signs List 30 PN generator 31, 32 n parallel flip-flop 33, 39 exclusive OR combination circuit 34 decoding circuit 35 logical product combination circuit 400 differentiating circuit 401 counter 402 OR circuit

Continued on the front page (72) Inventor Kazuhiko Omura 3-22-8 Hakata Ekimae, Hakata-ku, Fukuoka-shi, Fukuoka F-term in Fujitsu Kyushu Digital Technology Co., Ltd. F-term (reference) 2G032 AA01 AA04 AG07 5J039 AB02 GG06 KK09 KK11 KK23 MM11 5J049 AA07 AA17 AA22 CA00 5K014 AA05 BA00 EA01 EA04 EA07 GA04 5K047 AA03 AA05 GG34 KK04 MM28 MM56

Claims (6)

[Claims] 1. A generator for generating an n-bit parallel PN pattern signal, a first decoder for decoding m bits in the generated PN pattern signal, and an output specified by the output of the first decoder. A random error generating circuit, characterized by having an error insertion section for inserting an error signal at a bit position of the PN pattern signal. 2. The error insertion unit according to claim 1, further comprising a counter whose initial value can be set arbitrarily and whose count timing of a clock signal is controlled by an error occurrence signal that enables counting. A random error generating circuit, wherein an error signal is inserted into a bit position of the PN pattern signal specified by an output of the first decoding unit at a timing of a carry signal of the counter. 3. The apparatus according to claim 2, further comprising a second decoding unit for decoding (nm) bits in the n-bit parallel PN pattern signal, wherein the count value of the counter and the second A comparison unit that detects a match in the output of the decoding unit, and the error insertion unit includes a bit of the PN pattern signal specified by the output of the first decoding unit at a timing when the comparison unit detects a match. A random error generation circuit characterized by inserting an error signal at a position. 4. A generator for generating an n-bit parallel PN pattern signal, a first counter whose initial value can be arbitrarily set, and a coincidence between the PN pattern signal and the count value of the first counter. A random error generation circuit, comprising: a comparison unit for detecting a bit; and an error insertion unit for inserting an error signal at a bit position of the PN pattern signal, where a match is detected by the comparison unit. 5. The error insertion device according to claim 4, further comprising a second counter whose initial value can be arbitrarily set and whose count timing of a clock signal is controlled by an error occurrence signal that enables counting. A random error generating circuit that inserts an error signal at a bit position of the PN pattern signal at which a match is detected by the comparing unit at a timing of a carry signal of the second counter. 6. A decoding unit for decoding m bits in an n-bit parallel PN pattern signal, an error insertion unit for inserting an error signal at a bit position of the PN pattern signal specified by an output of the decoding unit, The n-bit parallel PN
A random error generation circuit having a circuit for outputting a parity signal of a pattern signal, and outputting a PN pattern signal into which an error from the error insertion unit has been inserted, and the parity signal.