JP3685419B2 - Testability circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a test facilitating circuit capable of realizing a test mode designating function in a semiconductor integrated circuit (IC) without assigning a test dedicated pin.
[0002]
[Prior art]
Conventionally, for the purpose of determining the quality of an IC or analyzing its failure, a test vector for making an IC perform a predetermined operation is created, and an IC tester or the like is used to test an IC using this test vector. Has been done.
However, as the circuit scale of an IC increases, the number of test vectors necessary for testing increases, so that the test vector development period increases and the IC test time and cost increase. .
[0003]
For this reason, conventionally, a test circuit is provided in the IC in advance, a test dedicated pin is allocated, and the IC is tested by shifting the IC to the test mode using the test dedicated pin.
However, in the above test method, in addition to the input / output pins for the normal operation mode of the IC, a plurality of test-dedicated pins for the test mode must be allocated, which is particularly serious in an IC that tends to have a shortage of input / output pins. It was a serious problem.
[0004]
As one solution to such a problem, for example, in Japanese Patent Laid-Open No. 60-4232, a decoder for decoding a combination signal of a plurality of specific input pins is provided in an LSI, and the output of this decoder is output. Among them, there is an LSI test mode designation method that can arbitrarily set multiple types of test modes without assigning dedicated test pins by using a decode output that does not occur in normal operation as a test mode designation signal. Proposed.
[0005]
Here, FIG. 4 shows a conceptual diagram of an example of a test circuit to which the LSI test mode designating system disclosed in Japanese Patent Laid-Open No. 60-4232 is applied.
In the test circuit 40 shown in the figure, the decoder 42 receives input signals IN1, IN2, and IN3 from the input pins, and part of the output of the decoder 42 is input to the test mode detection circuit 44 to detect the test mode. The circuit 44 outputs test mode designation signals TEST_MODE 1, 2, and 3.
[0006]
In the illustrated test circuit 40, the decoder 42 decodes the input signals IN1, IN2, and IN3 from the input pins, and the test mode detection circuit 44 performs normal operation in the input bit patterns of the input signals IN1, IN2, and IN3. An input bit pattern that cannot be a mode is detected, and a decoded output corresponding to an input bit pattern that cannot be a normal operation mode is used as a test mode designating signal TEST_MODE 1, 2, 3 among decoded signals. is there.
[0007]
According to the above-mentioned LSI test mode designation method, it is possible to realize an arbitrary test mode designation function without requiring any assignment of a test-dedicated pin, thereby enabling the internal functions to be expanded by effectively using input / output pins. .
[0008]
However, it is very difficult to obtain a plurality of input pins having an input bit pattern that cannot be in the normal operation mode, and there is a problem that the configuration of a circuit related to the input pins is remarkably limited. Even if an input bit pattern that cannot be in the normal operation mode is obtained, many input pins are required to obtain the input bit pattern. Therefore, the input signals from many input pins are decoded and There is a problem that the circuit scale of the test circuit for detecting the bit pattern increases.
[0009]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION An object of the present invention is to provide a test facilitating circuit that can realize a test mode designating function with a small circuit configuration without having to allocate a test dedicated pin in view of the problems based on the prior art. It is in.
[0010]
[Means for Solving the Problems]
To achieve the above object, according to the present invention, in the normal operation mode, at least two inputs that are input at different input timings via a plurality of input pins to which each input signal is input at the same input timing. A pulse generator that generates a clock signal having a frequency higher than the operating frequency in the normal operation mode, and a start of change of the input signal that changes first among the at least two input signals; A delay circuit that generates a preset signal having a pulse width corresponding to a predetermined delay time that is set; and an operation state that is set to an operation state for a predetermined fixed time by the preset signal; A counter that counts the clock signal while it is in a state and outputs a count signal that is the count number; No. If becomes a preset value, and a determination circuit for outputting a test mode detection signal for shifting to the test mode,
Each of the at least two input signals has a predetermined width, a shift width of each input timing is equal to or less than the predetermined width, and a delay time by the delay circuit changes first among the at least two input signals. It is an object of the present invention to provide a test facilitating circuit characterized in that the time is from the start of the change of the input signal to the end of the change of the input signal that changes last.
[0011]
Here, at least two input signals supplied via the input pins in the normal operation mode use signals that change at the same input timing in the normal operation mode, and change at input timings shifted from each other in the test mode. It is preferable to do so.
The counter preferably holds the value of the count signal when the count signal reaches a preset value.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
The test facilitating circuit of the present invention will be described in detail below based on a preferred embodiment shown in the accompanying drawings.
[0013]
FIG. 1 is a conceptual diagram of an embodiment of a test facilitating circuit according to the present invention.
The test facilitating circuit 10 shown in the figure provides a predetermined input signal at a predetermined input timing from a plurality of input pins in the normal operation mode without assigning a test dedicated pin to the semiconductor integrated circuit (IC). The IC is shifted to the test mode, and includes a pulse generator 12, a delay circuit 14, a counter 16, and a determination circuit 18.
[0014]
A plurality of input signals IN1, IN2,..., INn supplied from a plurality of predetermined input pins are input to the pulse generator 12 and the delay circuit 14, and the clock signal CK and the delay output from the pulse generator 12 are input. Both the preset signals PRE output from the circuit 14 are input to the counter 16. The count signal Qn output from the counter 16 is input to the determination circuit 18, and a test mode designation signal OUT is output from the determination circuit 18.
[0015]
In the illustrated test facilitating circuit 10, first, the pulse generator 12 is supplied from a plurality (two or more) of input signals IN1, IN2,..., INn supplied via a plurality of input pins in the normal operation mode. The clock signal CK input to the counter 16 is generated.
[0016]
In the pulse generator 12, when the IC is shifted to the test mode, for example, the input timings of the input signals IN1, IN2,..., INn are shifted from each other, and the logic of these input signals IN1, IN2,. As a result, the clock signal CK having a frequency higher than the operating frequency in the normal operation mode is generated. At this time, as the input pins, for example, those input at the same input timing in the normal operation mode are preferably used.
[0017]
The delay circuit 14 generates a preset signal PRE to be input to the counter 16 from a plurality of input signals IN1, IN2,..., INn supplied via a plurality of input pins in the normal operation mode. In the delay circuit 14, for example, after detecting a change in the input signals IN 1, IN 2,..., INn, the counter 16 is set in an operating state for a predetermined period of time, and the counter 16 is in an initial state (initial value) for other periods. A preset signal PRE is generated.
[0018]
As described above, when the IC is shifted to the test mode, the same plurality of input signals IN1, IN2,..., INn are input to the pulse generator 12 and the delay circuit 14, and the input pins are in the normal operation mode inside the IC. By generating a preset signal PRE having a predetermined pulse width and a high-frequency clock signal that is not directly input from (cannot be) input, it is possible to prevent erroneous transition to the test mode during the normal operation mode. it can.
[0019]
Note that the pulse width of the preset signal PRE, that is, the time during which the counter 16 is in the operating state, is determined by the predetermined number of clock signals CK required for shifting to the test mode at the operating frequency and input timing in the normal operation mode. What is necessary is just to determine suitably according to the operating frequency at the time of normal operation mode, the frequency of the clock signal CK produced | generated by the pulse generator 12, the number of clocks for shifting to test mode, etc. so that it may not be input into the counter 16.
[0020]
The counter 16 is a counter that is set in an operating state for a predetermined period of time by a preset signal PRE output from the delay circuit 14 and is in an initial state (predetermined value) during other periods, and is a pulse generator. 12 counts the number of clocks of the clock signal CK output from 12, and outputs a count signal Qn which is the count number.
[0021]
The determination circuit 18 detects that the count signal Qn has reached a preset value, that is, that a preset number of clock signals CK have been input to the counter 16, and shifts to the test mode. The test mode detection signal OUT is output.
[0022]
The counter 16 is basically in an operating state for a predetermined period of time by the preset signal PRE, and is returned to the initial state during other periods, so that the test mode detection signal OUT is in the active state. For example, the configuration is such that the value of the count signal Qn is held, or the active state level of the test mode detection signal OUT is held, for example, by providing a latch, a flip-flop (FF), etc. It is preferable to keep it.
[0023]
When the test facilitating circuit 10 shifts to the test mode, a pulse whose input timing is shifted by a predetermined time, for example, is input from the plurality of input signals IN1, IN2,. At this time, the delay circuit 14 generates a preset signal PRE for operating the counter 16 for a predetermined fixed time, and the pulse generator 12 generates a clock signal having a frequency higher than the operating frequency in the normal operation mode. CK is generated.
[0024]
The counter 16 is activated by the preset signal PRE, counts the number of clocks of the clock signal CK, and outputs a count signal Qn. The count signal Qn is determined by a determination circuit, and when the count signal Qn reaches a preset value, the test mode detection signal OUT is output and the IC shifts to the test mode, but the count signal Qn is preset. When the set value is not reached, the counter 16 is initialized by the preset signal PRE.
[0025]
On the other hand, in the normal operation mode, input signals IN1, IN2,..., INn are input at the input timing of the normal operation mode. At this time, even if the delay circuit 14 detects changes in the input signals IN1, IN2,..., INn, and the counter 16 is set in the operating state, the pulse generator 12 has the input timing in the normal operation mode. While the counter 16 is in the operating state, a predetermined number of clock signals CK necessary to shift the IC to the test mode are not generated.
[0026]
That is, in order for the IC to enter the test mode, it is necessary to supply a plurality of input signals IN1, IN2,..., INn at a predetermined input timing from a plurality of input pins in the normal operation mode using, for example, a tester. For example, in the normal operation mode state mounted on a printed circuit board or the like, the input signals IN1, IN2,..., INn are not input at such an input timing. There is no transition to test mode.
[0027]
The test facilitating circuit of the present invention is basically as described above.
Next, the test facilitating circuit of the present invention will be described in more detail with a specific circuit example.
[0028]
Here, FIG. 2 shows a configuration circuit diagram of an embodiment of the test facilitating circuit of the present invention. In the illustrated test facilitating circuit 10a, the clock signal CK is input three times during a predetermined time set in advance in the delay circuit 14a by the input signals supplied from the input pins IN1, IN2, IN3, and IN4. Then, the test mode detection signal TEST is set to the high level to shift the IC to the test mode, and thereafter the test mode is maintained until the power source is turned off, for example.
[0029]
In the illustrated test facilitating circuit 10a, the pulse generator 12a includes EXOR gates 20a and 20b, an OR gate 22, and inverters 24a, 24b, and 24c. Input signals IN1 and IN2 and input signals IN3 and IN4 are input to the EXOR gates 20a and 20b, respectively, and their outputs are both input to the OR gate 22. The output of the OR gate 22 is a clock signal CK that is input to the inverter 24a, and the inverters 24a, 24b, and 24c are connected in series.
[0030]
The delay circuit 14 a includes an OR gate 26, a delay element 28, an inverter 30, and an AND gate 32. Input signals IN 1, IN 2, IN 3, and IN 4 are input to the OR gate 26, and the output is input to one input terminal of the delay element 28 and the AND gate 32. The output of the delay element 28 is input to the inverter 30, the output of the inverter 30 is input to the other input terminal of the AND gate 32, and the output of the AND gate 32 is the preset signal PRE.
[0031]
The counter 16a has FFs 34a and 34b. The clock signal CK is input to the inverted clock input terminal of the FF 34a, and the data input terminal D and the inverted data output terminal QB are short-circuited. The output of the data output terminal Q of the FF 34a is input to the clock input terminal of the FF 34b, and the data input terminal D and the inverted data output terminal QB are short-circuited. The preset signal PRE is input to the preset terminals PR of the FFs 34a and 34b, and the outputs of the data output terminals Q are counter signals Q1 and Q2, respectively.
[0032]
The determination circuit 18a includes a NAND gate 36 and an inverter 38. The NAND gate 36 receives the inverted signals of the counter signals Q1 and Q2, its output is input to the clear terminals CR of the FFs 34a and 34b and the inverter 38, and the output of the inverter 38 is the test mode designating signal TEST. .
Thus, the test facilitating circuit of the present invention has a circuit configuration with an extremely small circuit scale.
[0033]
Next, the operation of the test facilitating circuit 10a will be described with reference to the timing chart shown in FIG.
Note that the FFs 34a and 34b of the counter 16a, for example, when the low level is input to both the preset terminal PR and the clear terminal CR, the clear terminal CR has priority over the preset terminal PR, and the data output terminal Q receives the low level. The level shall be output.
[0034]
As shown in the timing chart of FIG. 3, first, the input signals IN1, IN2, IN3, and IN4 are all set to a low level.
At this time, since the output of the OR gate 26 becomes low level, the preset signal PRE which is the output of the AND gate 32 also becomes low level, the counter 16a is preset, and the count signals Q1 and Q2 become high level. The detection signal TEST is at a low level.
[0035]
Next, the input signals IN1, IN2, IN3, and IN4 are input at input timings shifted from each other by a predetermined time.
[0036]
At this time, first, in the pulse generator 12a, the exclusive OR of the input signals IN1 and IN2 is taken by the EXOR gate 20a, and similarly, the exclusive OR of the input signals IN3 and IN4 is taken by the EXOR gate 20b. The outputs of these EXOR gates 20a and 20b are logically ORed by the OR gate 22 to become the clock signal CK, and then inverted by the inverters 24a, 24b and 24c, respectively, to become the inverted clock signal of the counter 16a.
[0037]
In the delay circuit 14a, a logical sum of the input signals IN1, IN2, IN3, IN4 is taken by the OR gate 26. The output of the OR gate 26 is delayed for a predetermined time by the delay element 28 and then inverted by the inverter 30, and the AND of the output of the OR gate 26 and the output of the inverter 30 is taken by the AND gate 32. The AND gate 32 outputs a high-level preset signal PRE having a pulse width corresponding to the delay time of the delay element 28.
[0038]
The counter 16a is in an operating state only while the precharge signal PRE is at a high level, and is counted down every time the clock signal CK is input.
[0039]
In the determination circuit 18a, when both the count signals Q1 and Q2 become low level, in other words, when the third clock signal CK is input to the counter 16a, the low level is output from the NAND gate 36. Is output and fed back to the clear terminal of the counter 16a, the count signals Q1 and Q2 are both held at a low level, and the test mode detection signal TEST, which is the output of the inverter 38, is at a high level. It is transferred to.
[0040]
【The invention's effect】
As described above in detail, the test facilitating circuit of the present invention not only has the advantage that the circuit scale is extremely small, but also allows the IC to be shifted to the test mode without assigning a test dedicated pin. Therefore, there is an effect that the input / output pins of the IC can be effectively used in the normal operation mode.
[Brief description of the drawings]
FIG. 1 is a conceptual diagram of an embodiment of a test facilitating circuit according to the present invention.
FIG. 2 is a configuration circuit diagram of an embodiment of a test facilitating circuit according to the present invention.
FIG. 3 is a timing chart of an embodiment illustrating the operation of the test facilitating circuit of the present invention.
FIG. 4 is a conceptual diagram of an example of a conventional test circuit.
[Explanation of symbols]
10, 10a Test facilitating circuit 12, 12a Pulse generator 14, 14a Delay circuit 16, 16a Counter 18, 18a Determination circuit 20a, 20b EXOR gate 22, 26 OR gate 24a, 24b, 24c, 30, 38 Inverter 28 Delay element 32 AND gates 34a and 34b Flip-flop (FF)
36 NAND gate

Claims (1)

In the normal operation mode, each input signal is input from a plurality of input pins that are input at the same input timing, from at least two input signals that are input while shifting each input timing, from the operation frequency in the normal operation mode. A pulse generator that generates a high-frequency clock signal, and a pulse width corresponding to a predetermined delay time set in advance after detecting the start of the change of the input signal that changes first among the at least two input signals. A delay circuit that generates a preset signal having an operating state, and is in an operating state for a predetermined period of time by the preset signal, and is in an initial state during other periods, and counts the clock signal during the operating state. A counter that outputs a count signal corresponding to the count number, and a test signal when the count signal reaches a preset value. And a judging circuit for outputting a test mode detection signal for shifting to a mode,
Each of the at least two input signals has a predetermined width, a shift width of each input timing is equal to or less than the predetermined width, and a delay time by the delay circuit changes first among the at least two input signals. A test facilitating circuit, characterized in that it is the time from the start of the change of the input signal to the end of the change of the input signal that changes last.

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