KR100844485B1 - Test mode entry/decision circuit for semiconductor device, semiconductor device having the same, and method of entering test mode and determining test mode of semiconductor - Google Patents

Abstract

A test mode entry / decision circuit of a semiconductor device capable of testing a semiconductor device while miniaturizing a chip size, and a semiconductor device having the same are disclosed. The test mode entry determiner generates an internal reset signal based on an external reset signal applied through the reset pin from the outside of the semiconductor device, and generates a test mode decision signal by shifting the low voltage detection signal generated inside the semiconductor device. The test mode decoding unit decodes the test mode determination signal to generate a test mode signal. Therefore, it is possible to enter the test mode and determine the test mode of the semiconductor device without having a separate pin for entering the test mode and determining the test mode.

Description

TEST MODE ENTRY / DECISION CIRCUIT FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE HAVING THE SAME, AND METHOD OF ENTERING TEST MODE AND DETERMINING TEST MODE OF SEMICONDUCTOR}

1 is a block diagram illustrating a configuration of a test mode entry / decision circuit of a semiconductor device according to an embodiment of the present invention.

2 illustrates a detailed configuration of the reset signal generator shown in FIG. 1.

3 illustrates a detailed configuration of a test mode determiner and a test mode decoder shown in FIG. 1.

4 is a timing diagram of a test mode entry / decision circuit of a semiconductor device according to an embodiment of the present invention.

5 illustrates a semiconductor device having a test mode entry / decision circuit of the semiconductor device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

80: delay unit 90: OR gate

100: reset signal generator 200: test mode determiner

210: AND gate 250: shift register

300: test mode entry / decision unit 400: test mode decoding unit

510: low voltage detector 520: clock generator

530: Initial reset signal generator

The present invention relates to a semiconductor device, and more particularly, to a test mode entry / decision circuit of a semiconductor device for entering and determining a test mode of a semiconductor device, a semiconductor device having the same, and a test mode entry / decision method of a semiconductor device. .

In general, semiconductor devices such as a micro control unit (MCU, hereinafter abbreviated as "MCU") have various tests to verify the operation of each functional block included in a chip state or a packaged state. Has a mode.

In addition, a general semiconductor device includes a low voltage detector (LVD) to prevent a malfunction that may occur when the power supply voltage is out of the normal operating range so that the semiconductor device is reset when a voltage lower than a preset reference voltage is applied. do.

The semiconductor device includes a separate test pin to enter various test modes as described above, and when a predetermined value is input to each test pin, the semiconductor device executes a test mode corresponding to the input value.

However, the conventional semiconductor device has a disadvantage in that the overall chip size is increased and the manufacturing cost is increased by additionally providing a plurality of test pins necessary for entering and determining the test mode to perform the various test modes as described above.

Korean Patent Laid-Open Publication No. 2002-17812 includes edge detecting and pulse generating means, condition circuit portion, first AND product, and S / R latch portion, and a reset signal, a first pin signal, and a second pin signal are forcibly applied from the outside. When the test mode is finally determined, a test enable signal generator for outputting a test enable signal is disclosed.

However, Korean Patent Laid-Open Publication No. 2002-17812 discloses only a device for generating a test mode (Test_enable, FIG. 3) for entering a test mode, and does not disclose a device for mode determination of a test. Therefore, Korean Patent Laid-Open Publication No. 2002-17812 has a disadvantage in that a pin for determining a test mode, such as a first pin and a second pin, must still exist.

Accordingly, a first object of the present invention is to provide a test mode entry / decision circuit of a semiconductor device capable of testing the semiconductor device while miniaturizing the chip size.

Further, a second object of the present invention is to provide a semiconductor device having the test mode entry / decision circuit.

Further, a third object of the present invention is to provide a test mode entry / decision method of a semiconductor device.

A test mode entry / decision circuit of a semiconductor device according to an aspect of the present invention for achieving the first object of the present invention described above is an internal reset signal based on an external reset signal applied through a reset pin from the outside of the semiconductor device. And a test mode entry determiner configured to generate a test mode decision signal by shifting a low voltage detection signal generated in the semiconductor device, and a test mode decoder to decode the test mode decision signal to generate a test mode signal. . The test mode entry determiner may generate a gated clock signal by gating the internal reset signal and a clock signal, and generate a test mode determination signal by shifting the low voltage detection signal in synchronization with the gated clock signal. The test mode decoding unit may generate a test mode signal by decoding the test mode determination signal in response to the internal reset signal.

The internal reset signal may be generated by ORing the delayed external reset signal delaying the external reset signal and the low voltage detection signal.

The test mode entry determiner is configured to perform a logical multiplication on the clock signal and the internal reset signal to generate a gated clock signal, and to receive and shift the low voltage detection signal to a serial input in synchronization with the gated clock signal. It may include a shift register for outputting the test mode decision signal in parallel. The shift register may be initialized by an initial reset signal generated inside the semiconductor device. The test mode decoding unit may be a decoder having ^N inputs (N being a natural number) and 2 ^N outputs. The internal reset signal may transition on the falling edge of the clock signal.

In addition, a semiconductor device having a test mode entry / decision circuit according to an aspect of the present invention for achieving the second object of the present invention compares the power supply voltage with a predetermined reference voltage and generates a low voltage detection signal corresponding to the comparison result. A low voltage detector, a clock generator for generating a clock signal having a predetermined frequency, an initial reset generator for generating an initial reset signal when the power is applied, and an external reset signal applied through a reset pin from the outside of the semiconductor device. And a test mode entry determination circuit configured to generate an internal reset signal, generate a test mode decision signal by shifting the low voltage detection signal generated by the low voltage detector, and generate a test mode signal by decoding the test mode decision signal. . The test mode entry determination circuit may generate a gated clock signal by gating the internal reset signal and the clock signal, and generate a test mode determination signal by shifting the low voltage detection signal in synchronization with the gated clock signal.

The test mode decoding unit may generate a test mode signal by decoding the test mode determination signal in response to the internal reset signal.

The internal reset signal may be generated by ORing the delayed external reset signal delaying the external reset signal and the low voltage detection signal. The test mode entry determination circuit receives and shifts the low voltage detection signal to a serial input in synchronization with the gated gate and the gated clock signal to generate a gated clock signal by ANDing the clock signal and the internal reset signal. It may include a shift register for outputting the test mode decision signal in parallel. The shift register may be initialized by the initial reset signal. The test mode entry decision circuit may include a decoder having ^N inputs (N is a natural number) and 2 ^N outputs for decoding the test mode decision signal. The internal reset signal may transition on the falling edge of the clock signal.

In addition, the test mode entry determination method of the semiconductor device according to an aspect of the present invention for achieving the third object of the present invention predetermined external reset signal based on the external reset signal applied through the reset pin from the outside of the semiconductor device Generating an internal reset signal delayed by a time, generating a gated second clock signal by gating the internal reset signal and a first clock signal, and shifting a low voltage detection signal in synchronization with the second clock signal And generating the test mode decision signal and decoding the test mode decision signal in response to the internal reset signal to generate a test mode signal.

The test mode entry determination method of the semiconductor device may further include initializing a test mode determination signal.

The initializing of the test mode decision signal may include generating an initial reset signal and initializing the test mode decision signal based on the initial reset signal. Generating the gated second clock signal may generate the gated second clock signal by performing an AND operation on the internal reset signal and the first clock signal. The generating of the test mode determination signal may include generating a low voltage detection signal by setting a power supply voltage to be equal to or less than a predetermined reference voltage and shifting the low voltage detection signal in synchronization with the gated second clock signal to determine the test mode. Generating a signal. The generating of the test mode signal may include maintaining the test mode decision signal unchanged in response to the internal reset signal, and decoding the test mode decision signal in response to the internal reset signal to generate the test mode signal. It may include a step.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description.

However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. Hereinafter, the same reference numerals are used for the same components in the drawings, and duplicate descriptions of the same components are omitted.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term and / or includes a combination of a plurality of related items or any item of a plurality of related items.

1 is a block diagram illustrating a configuration of a test mode entry / decision circuit of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, a test mode entry / decision circuit according to an embodiment of the present invention includes a test mode entry / decision unit 300 and a test mode decoding unit 400.

The test mode entry / determination unit 300 receives an LVD signal (LVD, Low Voltage Detect), an external reset signal (O_rst, Output reset), or an initial reset signal (POR, Power On Reset) and based on the internal reset signal. (I_rst, Internal reset) occurs.

The LVD signal LVD may be generated by, for example, a low voltage detector (LVD) provided inside the semiconductor device. For example, the LVD signal LVD may be generated when the power supply voltage supplied to the semiconductor device is lower than or equal to a preset reference voltage. 1 'and has a logic value' 0 'when the power supply voltage is above the reference voltage.

The external reset signal O_rst is a signal for initializing the semiconductor device and may be generated by an inspector of the semiconductor device applying an external reset signal through a reset pin (not shown) provided outside the semiconductor device.

The initial reset signal POR is a signal for initializing the semiconductor device as soon as power is applied to the semiconductor device and may be generated by the initial reset signal generator provided in the semiconductor device. For example, the initial reset signal generator may be a power on reset (POR) unit.

The test mode entry / determination unit 300 generates a test mode decision signal TD based on the LVD signal LVD, the initial reset signal POR, the clock signal CLK, and the internal reset signal I_rst. The test mode determination signal TD is a signal for determining one test mode among a plurality of preset test modes.

The test mode decoding unit 400 receives the test mode determination signal TD from the test mode entry / determination unit 300 in response to the internal reset signal I_rst provided from the test mode entry / determination unit 300. The received test mode decision signal TD is decoded to generate a test mode signal TM corresponding to the test mode decision signal TD among a plurality of preset test modes.

The test mode decoding unit 400 may be implemented as a decoder having ^N inputs (N being a natural number) and 2 ^N outputs.

In another embodiment of the present invention, the test mode entry / determination unit 300 may include a reset signal generator 100 and a test mode determiner 200.

The reset signal generator 100 receives the LVD signal LVD, the external reset signal O_rst, or the initial reset signal POR, and generates an internal reset signal I_rst based on the LVD signal LVD.

The test mode determiner 200 may generate a test mode decision signal based on the LVD signal LVD, the initial reset signal POR, the clock signal CLK, and the internal reset signal I_rst provided from the reset signal generator 100. TD).

2 illustrates a detailed configuration of the reset signal generator shown in FIG. 1.

Referring to FIG. 2, the reset signal generator 100 includes a delay unit 80 and an OR gate 90 (hereinafter, referred to as an “OR gate”).

The delay unit 80 delays and outputs the external reset signal O_rst for a predetermined time when the external reset signal O_rst is input to prevent the external reset signal O_rst from being activated due to the influence of external noise. . The delay unit 80 may be configured as a counter circuit that counts a predetermined time or a predetermined clock.

The OR gate 90 receives the LVD signal LVD, the delayed external reset signal DO_rst, and the initial reset signal POR, performs an OR operation, and outputs the result. The output of the OR gate 90 becomes an internal reset signal I_rst. That is, the OR gate 90 has a logic value '1' when any one or more signals of the LVD signal LVD, the delayed external reset signal DO_rst, and the initial reset signal POR have a logic value '1'. Is output as an internal reset signal I_rst.

3 illustrates a detailed configuration of a test mode determiner and a test mode decoder shown in FIG. 1.

Referring to FIG. 3, the test mode determiner 200 includes an AND gate 210 and a shift register 250.

The AND gate 210 receives the clock signal CLK and the internal reset signal I_rst and performs an AND operation to output the AND signal 210. The output of the AND gate 210 is used as a clock signal for the shift operation of the shift register 250.

For example, the AND gate 210 outputs the clock signal CLK as it is when the internal reset signal I_rst has a logic value of '1', and when the internal reset signal I_rst has a logic value of '0'. Outputs a logic value of '0' regardless of the clock signal CLK.

The shift register 250 receives the LVD signal LVD in series for each rising edge of the logically multiplied clock signal G_clk, performs a shift operation, and outputs the test mode decision signal TD in parallel. .

To this end, the shift register 250 is composed of a plurality of D flip-flops (251 to 259) connected in series. Each of the D flip-flops 251 to 259 constituting the shift register 250 is synchronized in common with a clock signal G_clk, which is an output of one clock, that is, the output of the AND gate 210. Perform. In addition, each of the D flip-flops 251 to 259 is commonly connected to the initial reset signal POR, and is simultaneously reset when the initial reset signal POR has a logic value '1'.

For example, when the initial reset signal POR is activated to have a logic value of '1', the shift register 250 resets all of the D flip-flops 251 to 259 to convert the logic value '00000' into a test mode decision signal ( TD). In addition, when the initial reset signal POR is inactivated and the internal reset signal I_rst is activated while the logic value is '0' to have the logic value '1', the AND gate 210 performs a logic multiplication of the clock signal G_clk. ), And the shift register 250 receives the LVD signal LVD in series for each rising edge of the AND signal clocked signal G_clk, shifts by one bit, and outputs the test mode decision signal TD in parallel. do.

The test mode decoding unit 400 is enabled or disabled according to the internal reset signal I_rst. For example, when the internal reset signal I_rst has a logic value '0', it is activated, and when the internal reset signal I_rst has a logic value '1', it is inactivated.

When the test mode decoding unit 400 is activated by the internal reset signal I_rst, the test mode decoding unit 400 receives the test mode decision signal TD from the shift register 250 and decodes the test mode signal TM to output the test mode signal TM.

As shown in FIG. 3, in an exemplary embodiment of the present invention, the internal reset signal I_rst and the clock signal CLK are logically operated to output a logically multiplied clock signal G_clk, and the output logically multiplied clock signal. (G_clk) is used as a clock for the operation of the shift register 250. Therefore, the test mode can be set only when the internal reset signal I_rst is activated (logical value '1'), thereby preventing a test mode setting error.

 In the embodiment of the present invention illustrated in FIG. 3, the shift register 250 is illustrated as five flip-flops 251 to 259, that is, 5 bits. However, the embodiment of the present invention is limited to the embodiment of FIG. 3. It may be composed of more flip-flops or fewer flip-flops depending on the number of test modes.

4 is a timing diagram of a test mode entry / decision circuit of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 4, first, when a power supply voltage Vdd is supplied to a semiconductor device in a time T0 period, the initial reset signal POR for initializing the semiconductor device has a logic value of '1'. The initial reset signal POR is provided to the shift register 250 so that the shift register 250 is reset and outputs a logic value '00000' as the test mode decision signal TD.

After that, when the external reset signal O_rst has a logic value '1' in the time T1 section, the external reset signal O_rst is delayed by a predetermined time by the delay unit 80 included in the reset signal generator 100. After that, the internal reset signal I_rst is output in synchronization with the falling edge of the clock signal CLK in the period T2.

In addition, the AND gate 210 included in the test mode determiner 200 outputs a logically multiplied clock signal G_clk by performing an AND operation on the internal reset signal I_rst and the clock signal CLK, and shift shift 250. The shift operation is performed in synchronization with the rising edge of the AND multiplied clock signal G_clk output from the AND gate 210.

When the power supply voltage Vdd becomes less than or equal to the predetermined reference voltage Vref in the time period T3, the LVD signal LVD has a logic value '1'. In the period T4, the shift register 250 receives the LVD signal LVD, that is, the logic value '1', on the rising edge of the logically multiplied clock signal G_clk, and receives the logic value '00001' as the test mode decision signal TD. Outputs

In the period T5, the shift register 250 receives the LVD signal LVD, that is, the logic value '0', on the rising edge of the AND-clocked clock signal G_clk, performs a shift by 1 bit, and then performs a test mode decision signal. Output the logical value '00010' to (TD).

When the power supply voltage Vdd becomes less than or equal to the reference voltage Vref again in the period T6, the LVD signal LVD has a logic value '1'. The shift register 250 receives the LVD signal LVD, that is, the logic value '0', at the rising edge of the logically multiplied clock signal G_clk, performs a shift by 1 bit, and then performs a test mode decision signal TD. Outputs the logical value '00100'.

In the period T7, the shift register 250 receives the LVD signal LVD, that is, the logic value '1', on the rising edge of the AND-clocked clock signal G_clk, performs a shift by 1 bit, and then performs a test mode decision signal. Outputs the logical value '01001' to (TD).

In the time period T8, the shift register 250 receives the LVD signal LVD, that is, the logic value '0' on the rising edge of the logically multiplied clock signal G_clk, performs a shift by 1 bit, and then performs a logic value '10010'. Output ' When the internal reset signal I_rst transitions to the logic value '0' at the falling edge of the clock signal CLK, the AND gate 210 outputs the logic value '0' as the logically multiplied clock signal G_clk. Accordingly, the shift register 250 maintains the current value '10010'.

When the internal reset signal I_rst transitions to the logic value '0' at the falling edge of the clock signal CLK, the test mode decoding unit 400 generates an internal reset signal I_rst, that is, the logic value '0'. A test mode decision signal TD which is activated and has a logic value '10010' from the shift register 250 is received, decoded, and outputs a test mode signal TM.

In an exemplary embodiment of the present invention, the internal reset signal I_rst at the falling edge of the clock signal CLK so that an abnormal glitch does not occur in the logically multiplied clock signal G_clk during the transition period of the internal reset signal I_rst. ) To make a transition.

As shown in FIG. 4, in the test mode entry / decision circuit according to the embodiment of the present invention, an internal reset signal I_rst is generated according to the external reset signal O_rst, and the internal reset signal I_rst and the power supply voltage ( The test mode is determined by Vdd) to test the semiconductor device. Therefore, a separate pin for entering and determining a test mode of the semiconductor device is not required.

5 illustrates a semiconductor device having a test mode entry / decision circuit of the semiconductor device according to an embodiment of the present invention.

Referring to FIG. 5, a semiconductor device having a test mode entry / decision circuit according to an exemplary embodiment of the present invention may include a test mode entry / decision unit 300, a test mode decoding unit 400, a low voltage detection unit 510, and a clock. A generator 520 and an initial reset signal generator 530 are included.

Since the test mode entry / determination unit 300 and the test mode decoding unit 400 have the same functions and configurations as those of the same reference numerals shown in FIGS. 1 to 4, descriptions thereof will be omitted to avoid duplication.

The low voltage detector 510 compares the power supply voltage Vdd supplied to the semiconductor device with a preset reference voltage Vref and generates a corresponding LVD signal LVD when the power supply voltage Vdd is less than or equal to the reference voltage Vref. Let's do it.

For example, when the power supply voltage Vdd is greater than the reference voltage Vref, the low voltage detector 510 outputs a logic value '0' so that the semiconductor device operates normally, and the power supply voltage Vdd is the reference voltage Vref. Or less), a logic value '1' is outputted to reset the semiconductor device to prevent malfunction of the semiconductor device.

The clock generator 520 generates a clock signal CLK having a predetermined frequency and provides the clock signal CLK to the test mode entry / determination unit 300.

The initial reset signal generator 530 generates an initial reset signal POR to initialize all components of the semiconductor device when power is applied to the semiconductor device. The initial reset signal POR generated by the initial reset signal generator 530 is provided to the test mode entry / determination unit 300 to initialize the shift register 250 included in the test mode entry / determination unit 300. . For example, the initial reset signal generator may be a power on reset (POR) unit.

According to the test mode entry / decision circuit of the semiconductor device and the semiconductor device having the same, an internal reset signal is output after delaying the external reset signal by a predetermined time, and a logically multiplied clock obtained by logically multiplying the output internal reset signal by a clock signal. The signal is used as a clock signal for the shift operation of the shift register. The LVD signal is generated by adjusting the power supply voltage below the reference voltage, and the generated LVD signal is input to the shift register in series and then output in parallel as a test mode decision signal. The test mode decoding unit decodes the test mode decision signal output from the shift register according to the internal reset signal and outputs a test mode signal.

Therefore, it is possible to enter the test mode and determine the test mode of the semiconductor device without having a separate pin for entering the test mode and determining the test mode.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. I will be able.

Claims (22)

The test mode entry determination circuit for entering the test mode of the semiconductor device, A test mode entry decision to generate an internal reset signal based on an external reset signal applied through a reset pin from the outside of the semiconductor device, and to generate a test mode decision signal by shifting a low voltage detection signal generated inside the semiconductor device. part; And And a test mode decoding unit configured to decode the test mode determination signal to generate a test mode signal. 2. The test mode determination signal of claim 1, wherein the test mode entry determiner generates a gated clock signal by gating the internal reset signal and a clock signal, and shifts the low voltage detection signal in synchronization with the gated clock signal to generate a test mode determination signal. And a test mode entry determination circuit of the semiconductor device. The method of claim 1, wherein the test mode decoding unit And a test mode signal is generated by decoding the test mode decision signal in response to the internal reset signal. The test mode entry decision circuit of claim 1, wherein the internal reset signal is generated by performing an OR operation on the delayed external reset signal delaying the external reset signal and the low voltage detection signal. The method of claim 1, wherein the test mode entry determiner An AND gate for performing an AND operation on the clock signal and the internal reset signal to generate a gated clock signal; And And a shift register configured to output the test mode decision signal in parallel after receiving and shifting the low voltage detection signal through a serial input in synchronization with the gated clock signal. Claim 6 was abandoned when the registration fee was paid. The method of claim 5, wherein the shift register And a test mode entry determining circuit of the semiconductor device, characterized in that it is initialized by an initial reset signal generated inside the semiconductor device. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1, wherein the test mode decoding unit A test mode entry determining circuit of a semiconductor device, wherein the decoder has ^N inputs (N is a natural number) and an output of 2 ^N. Claim 8 was abandoned when the registration fee was paid. The test mode entry decision circuit of claim 1, wherein the internal reset signal transitions at a falling edge of a clock signal. A low voltage detection unit comparing the power supply voltage with a preset reference voltage and generating a low voltage detection signal corresponding to the comparison result; A clock generator for generating a clock signal having a predetermined frequency; An initial reset generator for generating an initial reset signal when power is applied; And An internal reset signal is generated based on at least one of an external reset signal and an initial reset signal applied through a reset pin from the outside of the semiconductor device, and a low voltage detection signal generated by the low voltage detector is generated based on the clock signal. And a test mode entry determination circuit configured to shift to generate a test mode decision signal and to decode the test mode decision signal to generate a test mode signal. The low voltage of claim 9, wherein the test mode entry decision circuit is initialized based on the initial reset signal and gates the internal reset signal and the clock signal to generate a gated clock signal, and is synchronized with the gated clock signal. And shifting the detection signal to generate a test mode decision signal. Claim 11 was abandoned upon payment of a setup registration fee. The semiconductor device of claim 9, wherein the test mode entry determination circuit is activated based on the internal reset signal to decode the test mode determination signal to generate a test mode signal. Claim 12 was abandoned upon payment of a registration fee. 10. The semiconductor device according to claim 9, wherein the internal reset signal is generated by ORing the delayed external reset signal, which delays the external reset signal, the low voltage detection signal, and the initial reset signal. Claim 13 was abandoned upon payment of a registration fee. The circuit of claim 9, wherein the test mode entry decision circuit An AND gate for performing an AND operation on the clock signal and the internal reset signal to generate a gated clock signal; And And a shift register initialized based on the initial reset signal and synchronized with the gated clock signal to receive and output the low voltage detection signal through a serial input and output the test mode decision signal in parallel. . Claim 14 was abandoned when the registration fee was paid. The semiconductor device of claim 13, wherein the shift register is initialized by the initial reset signal. Claim 15 was abandoned upon payment of a registration fee. 10. The apparatus of claim 9, wherein the test mode entry decision circuit includes a decoder having ^N inputs (N is a natural number) and 2 ^N outputs for decoding the test mode decision signal, the decoder being activated based on the internal reset signal. A semiconductor device, characterized in that. Claim 16 was abandoned upon payment of a setup registration fee. 10. The method of claim 9, wherein the internal reset signal is generated by ORing the initial reset signal, the low voltage detection signal, and the delayed external reset signal delaying the external reset signal, and transitioning on the falling edge of the clock signal. Semiconductor device. Test mode entry determination method for entering the test mode of the semiconductor device, Generating an internal reset signal that delays the external reset signal by a predetermined time based on an external reset signal applied through a reset pin from the outside of the semiconductor device; Gating the internal reset signal and a first clock signal to generate a gated second clock signal; Generating a test mode determination signal by shifting a low voltage detection signal in synchronization with the second clock signal; And And decoding the test mode decision signal in response to the internal reset signal to generate a test mode signal. Claim 18 was abandoned upon payment of a set-up fee. 18. The method of claim 17, wherein the test mode entry determination method of the semiconductor device further comprises initializing a test mode determination signal. Claim 19 was abandoned upon payment of a registration fee. 19. The method of claim 18, wherein initializing the test mode decision signal comprises: Generating an initial reset signal; And And initializing the test mode decision signal on the basis of the initial reset signal. Claim 20 was abandoned upon payment of a registration fee. 18. The method of claim 17, wherein generating the gated second clock signal And performing a logical AND operation on the internal reset signal and the first clock signal to generate the gated second clock signal. 18. The method of claim 17, wherein generating the test mode decision signal comprises: Generating a low voltage detection signal by lowering the power supply voltage to a predetermined reference voltage or less; And And shifting the low voltage detection signal in synchronization with the gated second clock signal to generate the test mode determination signal. 18. The method of claim 17, wherein generating the test mode signal Maintaining the test mode determination signal unchanged in response to the internal reset signal; And And decoding the test mode decision signal in response to the internal reset signal to generate the test mode signal.

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