JPH11219226A - Clock input circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption in an object by controlling an operation reference clock to be supplied to the object. SOLUTION: Two OR gates 31 and 32 supplied with the operation reference clock CK0 and call signals SC respectively supply the clock CK0 to the logic circuits 41 and 42 of the object when the call signal SC is 'L' and stop the supply when the call signal SC is 'H'. By the supply stoppage of the clock CK0 , the power consumption of the logic circuits 41 and 42 is reduced. In the meantime, the clock CK0 and the clock CK1 are supplied to the OR gate 33. For the clock pulse of the clock CK1 , a cycle is longer and a pulse width is longer than the clock CK0 . The OR gate 33 supplies the clock CK0 to the logic circuit 43 while the clock pulse of the clock CK1 is supplied. Thus, since the logic circuit 43 is intermittently operated, the power consumption is little.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a clock input circuit for applying a clock to a semiconductor integrated circuit and other logic circuits.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram of a conventional clock input circuit. In recent years, semiconductor integrated circuits have not only been required to have high integration and high functionality, but also to have low power consumption. In particular, in a portable terminal or the like using a battery as a power source, reduction in power consumption when not busy (in a standby state) is required. The clock input circuit 10 of FIG. 2 has a function of stopping the operation reference clock CK ₀ supplied to each unit of the mobile terminal in a standby state.
It comprises two input OR gates 11 and 12. These OR gates 11 and 12 are in parallel, and the operation reference clock CK ₀ is commonly input to one input terminal of each of the OR gates 11 and 12. Each OR gate 11, 1
2 has a call signal S indicating a call
c has been entered. Output terminals of the OR gates 11 and 12 are respectively connected to the logic circuits 20 and 21 for performing an operation based on the operation reference clock CK _0.

In the clock input circuit 10, when the call signal Sc becomes valid "L", the OR gate 11,
12 supplies the operation reference clock CK ₀ to the logic circuits 20 and 21, and when the call signal Sc is invalid “H”, the operation reference clock CK ₀ is not supplied to the logic circuits 20 and 21, and the fixed “H” is logic. Output to circuits 20 and 21. Therefore, when the call signal Sc is “H”, the logic circuit 2
The operations of 0 and 21 are stopped, and the power consumption of the logic circuits 20 and 21 is reduced.

[0004]

However, the following problems have been encountered in a conventional portable terminal or the like which uses the clock input circuit of FIG. 2 to reduce power consumption. When the logic level of the call signal Sc from the outside is "H", the logic circuits 20 and 21 stop and enter a standby state, and the power consumption can be reduced accordingly. However, in a portable terminal or the like, in addition to a circuit whose operation can be completely stopped, such as the logic circuits 20 and 21, an interrupt monitoring circuit which must be constantly operated and a subsequent circuit connected thereto Etc. are incorporated. The interrupt monitoring circuit confirms that the call signal Sc has become valid "L" in order to return from the standby state to the operation state.
A logic circuit for detecting in synchronization with a clock pulse of the operation reference clock CK _0, the subsequent circuit operation reference clock C
K is a circuit which operates at a frequency of _0. The interrupt monitoring circuit and a subsequent stage circuit, so always be necessary to provide an operating reference clock CK _0, could not be performed to reduce the substantial power consumption for such a portable terminal.

[0005]

According to a first aspect of the present invention, there is provided a clock input circuit for supplying a clock formed by periodic clock pulses to an arbitrary number of target circuits. , The first and second gates are as follows. The first gate receives an interrupt signal having a complementary first logic level or a second logic level and an operation reference clock in which a clock pulse is formed in a first cycle, and receives the first logic level. Is supplied, the operation reference clock is supplied to the first target circuit of the arbitrary number of target circuits, and when the interrupt signal of the second logic level is supplied, the operation reference clock of the operation reference clock is supplied. This is to stop the supply. The second gate
A first clock having a cycle longer than the first cycle and a pulse width longer than a clock pulse width of the operation reference clock, and the operation reference clock; and an arbitrary number of target circuits. The operation reference clock is supplied to a second target circuit different from the first target circuit only during a period in which the clock pulse of the first clock is being input.

According to a second aspect, in the clock input circuit according to the first aspect, a first signal switching unit and a second signal switching unit as described below are provided. The first signal switching unit is connected to the first gate, receives the output signal of the first gate, the operation reference clock, and the switching signal, and outputs the output of the first gate by selection based on the switching signal. This is a circuit that switches between a signal and an operation reference clock and supplies it to a first target circuit. The second signal switching unit is connected to the second gate, receives the output signal of the second gate, the operation reference clock, and the switching signal, and outputs the output of the second gate by selection based on the switching signal. Signal and operation reference clock to switch to the second
Circuit to be supplied to the target circuit. The third invention is the first invention
In the clock input circuit according to the invention, the following frequency divider and signal switching unit are provided. The frequency divider divides the frequency of the operation reference clock. The signal switching unit is connected to the output side of the frequency divider, inputs the output signal of the frequency divider, the operation reference clock, and the switching signal, and based on the switching signal, operates the operation reference clock, the output signal of the frequency divider, Is given to the first gate and the second gate.

According to the first to third aspects of the present invention, since the clock input circuit is configured as described above, when the interrupt signal is at the first logical level, the operation reference clock is set to the first gate by the first gate. , And the first target circuit operates at a speed based on the operation reference clock. When the interrupt signal is at the second logic level, the supply of the operation reference clock is stopped. If the first target circuit is, for example, a circuit that can be stopped during standby, the operation can be stopped by setting the interrupt signal to the second logic level. on the other hand,
By the second gate, the operation reference clock is set to the second clock only during the period in which the clock pulse of the first clock is input.
To the target circuit. Assuming that the second target circuit needs to be constantly operated, an operation reference clock is intermittently applied to the second target circuit, and the operation is maintained. Therefore, the above problem can be solved.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram of a clock input circuit showing a first embodiment of the present invention. The clock input circuit 30 is provided in a portable terminal or the like, and operates the operation reference clock CK ₀ for two logic circuits 41 and 42 as a first target circuit and a logic circuit 43 as a second target circuit. And a two-input OR gate 31, which is a first gate.
32, and a two-input OR gate 33 as a second gate. One input terminal of each OR gate 31 to 33 has a configuration in which the operation reference clock CK ₀ is commonly inputted. The OR gate 31 and 32 the other input terminal of the call signal Sc is an interrupt signal is input to the other input terminal of the OR gate 33, the operation reference clock CK ₀ width of the period is long clock pulse than , The first clock CK ₁ having a longer length is input. The output terminal O31 of the OR gate 31 is connected to the logic circuit 41, the output terminal O32 of the OR gate 32 is connected to the logic circuit 42, and the output terminal O3 of the OR gate 33
3 is connected to the logic circuit 43. OR gate 31-
33 is provided to each of the logic circuits 41 to 43.

FIG. 3 is a block diagram showing a main part of the logic circuit 43 in FIG. 1. The functions of the logic circuits 41 to 43 in FIG. 1 will be supplementarily described with reference to FIG. Logic circuits 41, 4
2 is to reduce power consumption in mobile terminals, etc.
The waiting is a good circuit also stops supplying the operation reference clock CK _0. On the other hand, the logic circuit 43 includes, for example, a latch circuit 43 for holding a call signal Sc which is an interrupt signal.
-1 and has a flip-flop 43-2 is connected to the output terminal of the latch circuit 43-1, and interrupt monitoring circuit that monitors the logical level of the call signal Sc using the operation reference clock CK _0, it This circuit is composed of a connected subsequent circuit (not shown) and cannot stop its operation even during standby. FIG. 4 shows the clock input circuit 3 of FIG.
5 is a time chart showing an operation waveform of the logic circuit 43 of FIG. 3. The operation of the clock input circuit of FIG. 1 will be described with reference to FIGS.

[0010] a normal operating state when the call signal Sc is valid first logical level "L", as shown in FIG. 4, OR gates 31 and 32 operates the reference clock CK ₀ the output terminal O 31, O32 Output from each. The logic circuits 41 and 42 to which the operation reference clock CK ₀ has been input from the OR gates 31 and 32 perform operations based on the operation reference clock CK ₀ . Call signal Sc is at the "H" of the second logic level, OR gate 31 and 32 without passing through the operation reference clock CK _0, and outputs a fixed "H" level. As a result, the logic circuits 41 and 42 enter a standby state and stop operating. Meanwhile, OR gate 33, both in time when the logic level "L" of the call signal Sc and "H", the period during which the clock pulse of the clock CK ₁ is given, intermittently, the operation reference clock CK
Pass ₀ . The interrupt monitoring circuit supplied with the intermittent operation reference clock CK ₀ from the output terminal O 3 of the OR gate 33
The said operating reference clock CK ₀ flip-flop 43-2
Clock terminal. Flip-flop 43
-2, as shown in FIG. 5, in synchronization with the rising edge of the operation reference clock CK _0, and outputs to the subsequent stage by captures and output signal of the latch circuit 43-1. That is, the interrupt monitoring circuit of the logic circuit 43 monitors the logical level of the interrupt signal Sc perform sampling during a period in which the given operation reference clock CK _0, give the monitoring result to the subsequent circuit. For example, a frequency dividing counter is prepared in the subsequent circuit, and the internal timer value of the frequency dividing counter is increased according to the output signal of “H” of the flip-flop 43-2 which is the monitoring result of the interrupt signal Sc. If this is done, the operating speed of the subsequent circuit will be slow.

As described above, in the first embodiment,
Supplying an operation reference clock CK ₀ to the logic circuit 41 when the logic level "L" of the call signal Sc, said operating reference clock C when the call signal Sc is "H" level
Including logic gates 31 and 32 for blocking K ₀ ,
An OR gate 33 for intermittently supplying the operation reference clock CK ₀ to the logic circuit 43 is provided. Here, the logic circuit 4
The current consumption of normal logic circuits including 1 to 43 greatly depends on the number of gates, frequency, power supply voltage and the like. In the standby state, the logic circuits 41, 4
2 is not supplied with the operation reference clock CK _0, so that the logic circuits 41 and 42 do not consume a frequency-dependent current. In addition, since the operation reference clock CK ₀ is only intermittently supplied to the logic circuit 43 by the OR gate 33, the average clock frequency in the logic circuit 43 becomes extremely small, and the current consumption is reduced. Flip-flop 43-2 in the interrupt monitoring circuit of the logic circuit 43, so may be detected that the call signal Sc is changed, the operation reference clock CK ₀ is the function given intermittently is ensured, there is no problem.

Second Embodiment FIG. 6 is a circuit diagram of a clock input circuit according to a second embodiment of the present invention. This clock input circuit 50 is the same as the OR gates 31 and 32 of the first embodiment for inputting the operation reference clock CK ₀ and the call signal Sc, respectively.
R gates 51 and 52 and an OR gate 53 similar to the OR gate 33 for inputting the operation reference clock CK ₀ and the clock CK ₁ are provided. Output terminals O51 to O53 of the OR gates 51 to 53 are connected to signal switching units 54, 55 and 56, respectively, to which the switching signal Ss1 is input. Output terminals of the signal switching units 54, 55, and 56 are connected to the logic circuits 61 to 63, respectively.

FIG. 7 is a circuit diagram showing the signal switching section 54 in FIG. The signal switching unit 54 includes a two-input OR gate 54-1 in which the output terminal O51 of each OR gate 51 is connected to one input terminal and the switching signal Ss1 is input to the other input terminal, and the switching signal Ss1 To inverter 54-
And inputs the one input terminal via a 2, and a two-input OR gate 54-3 of connection for inputting an operation reference clock CK ₀ to the other input terminal. OR gate 54
-1 and 54-3 are output terminals of a two-input AND gate 5
4-4 are connected to the respective input terminals. AND
The output terminal of the gate 54-4 is connected to the logic circuit 61. Each of the signal switching units 55 and 56 is also
It has the same configuration as. Signal switching units 54 to 56
Are OR gates 51 to 53 based on the switching signal Ss1.
And it has a function of outputting to the logic circuit 61 to 63 to switch the output signal or operation reference clock CK ₀ of. The logic circuits 61 to 63 are the logic circuits 41 according to the first embodiment.
Although the circuits respectively correspond to .about.43, a full scan design method for improving fault detection is applied.
That is, a multiplexer is provided at a stage preceding all the flip-flops in each of the logic circuits 61 to 63, and these flip-flops are appropriately connected to the serial scanning flip-flops when the test mode is set. Has become.

FIG. 8 is a time chart showing the operation waveforms of FIG. Call signal Sc and operation reference clock CK
₀ , or the operation reference clock CK ₀ and the clock CK
OR gate 51 to 53 Type ₁ operates similarly to the OR gate 31 to 33 of the first embodiment, outputs an operation reference clock CK _0. That is, the OR gates 51 and 52
Outputs the operation reference clock CK ₀ when the call signal Sc is at the “L” level, and stops its supply when it is at the “H” level. OR gate 53 outputs the intermittent operation reference clock CK _0. When the switching signal Ss1 is “L”, the OR gate 54-1 in each of the signal switching units 54 to 56
Respectively pass the output signals of the OR gates 51 to 53 to the AND gate 54-4,
3 gives "H" to the AND gate 54-4. Therefore, the AND gate 54 in each of the signal switching units 54 to 56
-4 give respectively an operation reference clock CK ₀ to the output of OR gate 51 to 53 to the logic circuit 61 to 63. Logic circuit 61 to 63, based on the operation reference clock CK _0, operates similarly to the first embodiment.

On the other hand, when the switching signal Ss1 is input as "H" to set the logic circuits 61 to 63 to the test mode, the OR gates 54 in the signal switching units 54 to 56 are set.
-1 gives "H" to the AND gate 54-4 without passing the output signals of the OR gates 51 to 53,
4-3 AND the operation reference clock CK ₀ gate 54 -
Give to 4. Therefore, the AND gate 54-4 in each signal switching unit 54 to 56, regardless of the output signal of the OR gate 51 to 53, giving each an operation reference clock CK ₀ to the logic circuit 61 to 63. In this case, all flip-flops in the logic circuits 61 to 63, performed so are appropriately connected in series has a flip-flop for scan, the shift register operation in which all the flip-flop is synchronized with the operation reference clock CK _0, respectively . Test data is held in the flip-flops by the shift register operation. By checking the correctness of each test data held in the flip-flop, each logic circuit 6
Scan inspections 1 to 63 are performed.

As described above, in the second embodiment,
Between the OR gates 51 to 53 and the logic circuits 61 to 63, based on the switching signal Ss1, the OR gates 51 to 53
Is provided with the signal switching unit 54 to 56 which respectively output selects the output signal or operation reference clock CK ₀ of when the switching signal Ss1 is "L", as in the first embodiment, a mobile terminal or the like it is possible to reduce the power consumption of the in the switching signal Ss1 "H" to set the test mode for the logic circuits 61 to 63 full-scan design is performed, the same timing an operation reference clock CK ₀ fast The scan inspection can be performed with high accuracy without causing a malfunction due to clock skew.

Third Embodiment FIG. 9 is a circuit diagram of a clock input circuit according to a third embodiment of the present invention. The clock input circuit 70 receives the operation reference clock CK ₀ and inputs the operation reference clock CK ₀
128 divider counter 7 which is a divider for dividing ₀ by 128
It includes 1, and a signal switching unit 72 for inputting the output signal of the 128 frequency-dividing counter 71 and the operation reference clock CK ₀ and switching signal Ss2. Signal switching unit 72, and outputs switches the output signal of the divider counter 71 and the operation reference clock CK _0. On the output side of the signal switching unit 72, the first
Corresponding to the OR gates 31 to 33 in the embodiment of FIG.
Two two-input OR gates 73 to 75 are connected. The output terminal of the signal switching unit 72 is connected to one input terminal of each of the OR gates 73 to 75. The other input terminals of the OR gates 73 and 74 have a call signal Sc
Is input, and the clock CK ₁ is input to the other input terminal of the OR gate 75. The output terminals O73 to O75 of the respective OR gates 73 to 75 are connected to the same logic circuits 81 to 83 as the logic circuits 41 to 43 of the first embodiment.
Connected to each other.

FIG. 10 is a time chart showing operation waveforms of the clock input circuit of FIG. In a normal operation state, an “L” level switching signal Ss2 is applied to the signal switching unit 72, and an “L” level call signal Sc is applied to the OR gates 73 and 74. In this state, the signal switching unit 7
2 selects the operation reference clock CK ₀ , and each OR gate 7
Output to 3-75. From the output terminal O73, O 74 of the OR gates 73 and 74, the operation reference clock CK ₀ is supplied is output to the logic circuit 81. The operation reference clock CK ₀ is output intermittently from the output terminal O 75 of each OR gate 75 and supplied to the logic circuit 83.
The "H" level call signal Sc is supplied to the OR gates 73 and 74.
To the logic circuit 8 as in the first embodiment.
The supply of the operation reference clock CK ₀ to the logic circuits 1 and 82 is stopped, the operation of the logic circuits 81 and 82 is stopped, and the apparatus enters a standby state.

Here, it will be described that the clock input circuit of FIG. 9 can set not only a standby state in which the operations of the logic circuits 81 and 82 are completely stopped, but also a quasi-standby state different from this standby state. The frequency division counter 71 divides the frequency of the operation reference clock CK ₀ by 128 and outputs it to the signal switching unit 72. When the call signal Sc applied to the OR gates 73 and 74 is at the "L" level and the switching signal Ss2 applied to the signal switching unit 72 is at the "H" level, the signal switching unit 72 outputs the output signal of the frequency dividing counter 71. Is given to the OR gates 73 to 75. That is, the operation reference clock CK _0, which is divided, is supplied to the OR gate 73-75. The OR gates 73 and 74 determine that the call signal Sc is "L".
Since the level is the level, the divided operation reference clock CK ₀ is supplied to each of the logic circuits 81 and 82. Therefore, each of the logic circuits 81 and 82 operates at a low speed.

As described above, in the third embodiment,
Since the frequency dividing counter 71 and the signal switching unit 72 are provided, a quasi-standby state can be set. By setting the quasi-standby state, the following advantages can be obtained. In general, if there are many logic circuits 81 and 82 that completely stop the operation and circuits connected to them, it takes time to excite the standby state to the operation state. If it becomes possible to set the quasi-standby state in which the logic circuits 81 and 82 operate at a low speed, the time required to excite the standby state from the standby state to the operation state can be reduced.

Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications. (1) OR gates 31 to 33, 51 to 53, 73 to 7
Reference numeral 5 may be constituted by a gate other than the OR when the logic of the call signal Sc, the operation reference clock CK ₀ , the clock CK ₁ , and the output signal of the signal switching unit 72 is changed. (2) The division ratio of the 128 division counter 71 can be changed to another appropriate division ratio. (3) Since the two OR gates 31 and 32, the two OR gates 51 and 52, and the two OR gates 73 and 74 have the same output signal, they can each be configured with one OR gate. It is.

[0022]

As described above in detail, according to the first aspect, when the interrupt signal is at the first logic level, the operation reference clock is supplied to the first target circuit, and the second logic level is supplied to the first logic circuit. A first gate that stops supplying the operation reference clock when the level is high, and a second gate that supplies the operation reference clock to the second target circuit during a period in which the clock pulse of the first clock is being input. Since the clock input circuit is configured, the operation of the first target circuit can be stopped, and the operation reference clock can be intermittently applied to the second target circuit. Therefore, for example, if the first target circuit is a circuit that can be stopped during standby and the second target circuit needs to be constantly operated, not only can the power consumption of the first target circuit be reduced, The power consumption of the second target circuit can be reduced.

According to the second invention, the clock input circuit according to the first invention is provided with the first and second signal switching units for providing the operation reference clock to the first and second target circuits based on the switching signal. With this arrangement, for example, a high-speed operation reference clock can be supplied not only to the first target circuit but also to the second target circuit, so that a scan test with high accuracy can be performed. According to the third invention, a frequency divider for dividing the operation reference clock is provided to the clock input circuit of the first invention,
A signal switching unit is provided for switching between the operation reference clock and the output signal of the frequency divider based on the switching signal and switching the output to the first and second gates.
In addition to setting a standby state in which the supply of the operation reference clock to the first target circuit is stopped to completely stop the operation, a quasi-standby state in which the first target circuit operates at a low speed can be set. become. Accordingly, the time required to excite the first target circuit to the operating state can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a clock input circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional clock input circuit.

FIG. 3 is a configuration diagram showing a main part of a logic circuit 43 in FIG. 1;

FIG. 4 is a time chart showing operation waveforms of the clock input circuit of FIG. 1;

FIG. 5 is a time chart showing operation waveforms of the logic circuit of FIG. 3;

FIG. 6 is a circuit diagram of a clock input circuit according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram showing a signal switching unit in FIG. 6;

FIG. 8 is a time chart showing operation waveforms of FIG.

FIG. 9 is a circuit diagram of a clock input circuit according to a third embodiment of the present invention.

FIG. 10 is a time chart illustrating operation waveforms of the clock input circuit of FIG. 9;

[Explanation of symbols]

30, 50, 70 Clock input circuit 31, 32, 51, 52, 73, 74 OR gate (first gate) 33, 53, 55 OR gate (second gate) 41, 42, 61, 62, 81, 82 logic circuit (first target circuit) 43,63,83 logic circuit (the second target circuit) 54～56,72 signal switching unit 71 divided by 128 counter CK _o operation reference clock CK ₁ first clock Sc split Switching signal Ss1, Ss2 switching signal

Claims (3)

[Claims] 1. A clock input circuit for supplying a clock formed by a periodic clock pulse to an arbitrary number of target circuits, comprising: an interrupt signal having a complementary first logical level or a second logical level; An operation reference clock in which the clock pulse is formed in one cycle, and when the interrupt signal of the first logic level is given, the operation reference clock is supplied to a second one of the arbitrary number of target circuits. A first gate for supplying to the first target circuit and stopping the supply of the operation reference clock when the interrupt signal of the second logic level is given; a period longer than the first period and a pulse width Receives a first clock formed by a clock pulse longer than a clock pulse width of the operation reference clock and the operation reference clock, and outputs a first target circuit of the arbitrary number of target circuits A second gate for supplying the operation reference clock only to a period in which a clock pulse of the first clock is input to a different second target circuit. . 2. An output signal of the first gate, the operation reference clock, and a switching signal, which are connected to the first gate, and are selected based on the switching signal. A first signal switching unit that switches between an output signal and the operation reference clock and supplies the output signal and the operation reference clock to the first target circuit; an output signal of the second gate connected to the second gate; And the switching signal,
A second signal switching unit that switches between the output signal of the second gate and the operation reference clock and supplies the output signal to the second target circuit by selection based on the switching signal. The clock input circuit according to claim 1. 3. A frequency divider for dividing the operation reference clock, connected to an output side of the frequency divider, receiving an output signal of the frequency divider, the operation reference clock, and a switching signal, 2. A signal switching unit for switching between the operation reference clock and the output signal of the frequency divider based on a switching signal and providing the switching signal to the first gate and the second gate. Clock input circuit.