JP3258846B2 - Key input method and key input device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a key matrix circuit in which a plurality of key switches are arranged in a matrix and one of an X axis and a Y axis is used as a scan timing signal line and the other is used as a key state detection signal line. The present invention relates to a key input device and a key input method for detecting an on / off state of a key switch.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there is one described in the following literature. Documents: JP-A-59-87534 Conventionally, a scanning method of this kind is disclosed in the above-mentioned document. A plurality of keys of a keyboard device are repeatedly scanned at a constant period, and are continuously scanned at least twice. In this method, only the key that was in the on state is turned on, and the output is turned off only for the key that is in the off state in at least two scans. This method prevents erroneous ON / OFF output due to a so-called chattering phenomenon in which a key contact bounces at the time of opening and closing and repeats ON / OFF at a high speed.

[0003]

However, the conventional key input method has the following problems. (1) In the conventional method, the current consumption is large because the scanning is constantly repeated. (2) High-frequency noise generated at the time of scanning adversely affects other circuits and causes malfunction. (3) A new storage and comparison function must be added to the circuit because two scans must be performed and the two results must be compared, resulting in an increase in circuit size.

[0004]

According to a first aspect of the present invention, in order to solve the above-mentioned problems, a plurality of key switches are arranged in a matrix, one of an X axis and a Y axis is used as a scan timing signal line, and the other is used as a scan timing signal line. A key matrix circuit having a key status detection signal line, an oscillation circuit for generating an operation timing signal, a scan timing signal output to the scan timing signal line, and turning on / off of the key switch from the key status detection signal line In a key input method of a key input device including a scanner circuit for detecting a state and controlling the oscillation circuit, the scanner circuit executes the following processing. That is, if there is no input of the key switch in the ON state, an oscillation stop process for stopping the oscillation operation of the oscillation circuit, and always outputting the scan timing signal to all the scan timing signal lines, And a key-on state detection process for detecting the on-state. Further, when there is an input of the key switch in an ON state, an oscillating operation process for causing the oscillating circuit to oscillate and outputting the scan timing signal to the scan timing signal line in order to turn on / off each key switch. And a scan process for detecting the state.

[0005]

According to the first aspect of the present invention, since the key input method is configured as described above, a scan timing signal is output to the scan timing signal line and there is a key switch that is on from the key state detection signal line. Judge whether or not. If there is no key switch in the ON state, the oscillation operation of the oscillation circuit is stopped, and a scan timing signal is constantly output to all scan timing signal lines to detect the ON state of the key switch. Also, if there is an input of an on-state key switch, an oscillation operation process for causing the oscillation circuit to oscillate and a scan timing signal is sequentially output to a scan timing signal line to detect the on / off state of each key switch. . Therefore, the above problem can be solved.

[0006]

FIG. 1 is a block diagram showing the configuration of a key input device according to an embodiment of the present invention. This key input device has a horizontal (X
Axis) and the vertical (Y axis) direction in a matrix (for example, 4
× 4) a key matrix circuit 100 in which a key switch SW is disposed, a scanner circuit 200, an oscillation circuit 400,
It comprises a CPU interface circuit 500 and a central processing unit (hereinafter referred to as CPU) 600.
The four X-axis signal lines of the key matrix circuit 100 are set as key state detection signal lines, and the four Y-axis signal lines are set as scan timing signal lines. The key matrix circuit 100 provides the scanner circuit 200 with key state detection signal lines C0, C1, C2, C3. The scanner circuit 200 provides the key matrix circuit 100 with scan timing signal lines R0, R1, R2, R3. The scanner circuit 200 gives the oscillation operation / stop command signal line OSC EN to the oscillator circuit 400 receives an oscillation output signal line phi ₀ from the oscillation circuit 400. The scanner circuit 200 sends an interrupt signal line I to the CPU 600.
Give NT directly. The scanner circuit 200 supplies a scan data output line SO to the CPU interface 500.
Give UT. The CPU interface 500 is a CP
Data input / output line data I / O is given to U600.
The CPU interface 500 is connected to the scanner circuit 20.
0 is applied to the INT signal reset line INT RST. The CPU 600 supplies a clock signal line c to the scanner circuit 200 via the CPU interface 500.
lock and a load signal line LOAD.

FIG. 2 is a functional block diagram of the scanner circuit 200 in FIG. As shown in FIG. 2, the scanner circuit 200 includes an input section 210, a key-on detection circuit 22.
0, input latch circuit 230, scan / oscillation operation / stop circuit 240, 、 frequency divider 250, scanner signal generation 分 frequency divider 260, scan timing signal generation circuit 270, output circuit 280, key all-off detection Circuit 2
90, and an INT signal generation circuit 300. The key matrix circuit 100 provides the input section 210 with key state detection signal lines C0, C1, C2, and C3. The input unit 210 provides a signal line to the key-on detection circuit 220 and the input latch circuit 230 to indicate whether or not the key switch is on. The key-on detection circuit 220 supplies a scan operation request signal line SCAN REQ to the scan / oscillation operation / stop circuit 240. The input latch circuit 230 supplies a signal line indicating whether or not the key is on to the output circuit 280. The scan / oscillation operation / stop circuit 240 supplies the oscillation circuit 400 with the oscillation operation / stop command signal line OSCEN, the input latch circuit 230, and the IN
A reset timing signal is supplied to the T signal generation circuit 300, a scan operation start signal line SCAN ST is supplied to the scanner signal generation 1/4 frequency divider 260, and a scan enable signal line SCAN EN is supplied to the scan timing signal generation circuit 270.
Give each.

The oscillation circuit 400 includes a 1/4 frequency dividing circuit 250
Give the oscillation output signal line φ ₀ to. 1/4 frequency dividing circuit 2
50 includes an input latch circuit 230 to the 1/4 frequency signal line phi _1, scan oscillation operation / stop circuit 240 to the 1/4 frequency signal line phi _2, the scan timing signal generating circuit 2
70 is provided with a latch timing signal line LATCH. The scanner signal generating quarter-frequency dividing circuit 260 supplies the scan / oscillation operation / stop circuit 240 and the INT signal generating circuit 300 to the scan cycle end signal line SCAN.
By giving SYC, it also functions as a scan cycle end detection circuit. The output circuit 280 supplies a key state detection signal during a scan cycle to the key all-off detection circuit 290,
The scan data output signal SOUT is supplied to the PU interface circuit 500. Key all-off detection circuit 290
The all key switch OFF signal ALL is supplied to the INT signal generation circuit 300 and the scan / oscillation operation / stop circuit 240.
Give ZERO. The scan timing signal generation circuit 270 provides the key matrix circuit 100 with the scan timing signal lines R0, R1, R2, R3 and the output circuit 2
80, the latch signals L0, L1, L2, L3 are given. I
The NT signal generation circuit 300 includes a CPU interrupt signal line INT for the CPU 600, and a normal scan confirmation signal line NOM SCAN for the scan / oscillation operation / stop circuit 240.
give. Power-on circuit reset signal line POR
Is supplied to the scan / oscillation operation / stop circuit 240. From the CPU interface circuit 500 to the INT signal generation circuit 300, an INT signal reset signal line INT
RST is given. Output circuit 28 from CPU 600
0 is supplied with a clock signal line clock and a load signal line LOAD via the CPU interface 500.

A key input method according to an embodiment of the present invention will be described below with reference to FIG. When power-on processing power is turned on, scan / oscillation operation / stop circuit 2
The power-on reset signal is supplied to 40, and this information is supplied to the scan timing signal generation circuit 270. The scan timing signal generation circuit 270 sets the scan timing signals R0 to R3 to "L", thereby setting the key-on detection state. Key state detection processing When any key switch of the key matrix circuit 100 is pressed, the input section 210 receives an input from the key state detection signal lines C0 to C3 indicating that the key switch has been turned on. The key-on detection circuit 220 detects that any key is turned on, and notifies the scan / oscillation operation / stop circuit 240 of the fact. The oscillation operation processing scan / oscillation operation / stop circuit 240 outputs an oscillation operation command signal OSCEN to the oscillation circuit 400.
Oscillation is started by the oscillation circuit 400 and an oscillation output signal φ ₀ is supplied to the scanner circuit 200. That is, when all the key switches of the key matrix circuit 100 are in the off state, the scanning of the scanner circuit 200 and the oscillation of the oscillation circuit 400 are stopped, and when any one of the key switches is turned on, the scanner circuit 200 turns off this. Oscillation is started by detecting and instructing the oscillation circuit 400 to oscillate.

Scan Start (Scan Processing) The scanner circuit 200 starts scanning by generating a scan signal using the oscillation output signal φ ₀ as a synchronization signal. The scan signal generated by the scanner circuit 200 is supplied to the key matrix circuit 100 in the order of the scan timing signal lines R0 to R3. This allows
First, the on / off state of the key switch on the R0 line is
Hereinafter, the on / off states of the key switches on the R1, R2, and R3 lines are sequentially input to the input unit 210 of the scanner circuit 200 from the key state detection signal lines C0 to C3, and output to the output unit 280 by predetermined latch signals L0 to L3. And the on / off state of the key switch. From the start of the on / off state of the key switch on the R0 line, R3
One scan cycle is performed until the on / off state of the key switch on the line is captured. The INT signal generation circuit 300 of the chattering avoidance processing scanner circuit 200
At the start (restart) of the scan and after the end of the first scan cycle, an interrupt signal I is output to prevent chattering.
NT is not given to CPU 600. Thereby, the CPU 6
00 ignores data (hereinafter referred to as scan data) input from the key state detection signal lines C0 to C3. This scan cycle is called a dummy scan.

Scan Data Import Processing The INT signal generation circuit 300 of the scanner circuit 200
If it is not a dummy scan, the interrupt signal INT
Give to U600. When the CPU 600 decides to take in the scan data after the interruption signal INT is given, the CPU 600 sends the LOAD signal,
The k signal is provided to the output section 280 of the scanner circuit 200. As a result, the CPU 600 sends the CPU interface 500 and the DATA I / O from the SOUT signal line.
, The scan data of the scanner circuit 200 is fetched. When scanning data has been captured, IN
CPU interface 500 by TRST line
Supplies an INT signal reset command to the scanner circuit 200. Thereby, the interrupt signal of the INT signal line is turned off.

Oscillation stop processing All key switches are turned off (hereinafter referred to as ALL ZERO).
When the state becomes O), this is detected by the key all-off detection circuit 290 of the scanner circuit 200, and the scan cycle is stopped. At the same time, the scanner circuit 2
00 scan / oscillation stop circuit 240
A stop command is given to the oscillation circuit 400 from the signal line. The oscillation circuit 400 that has received the stop instruction stops the oscillation.
Thereafter, the scan timing signal lines R0 to R3 enter the simultaneous output state, that is, the key ON detection state. The scanner circuit 200 in the scan resumption processing key-on detection state is in a waiting state until one of the key switches of the key matrix circuit 100 is turned on. Here, when any key switch is pressed, the scanner circuit 200 immediately detects the key switch and starts scanning again. As described above, in the present embodiment, when there is no input to all the key switches, not only the scan but also the oscillation is stopped to reduce the current consumption and to the other circuits due to the high frequency noise generated by the scan operation. This has the advantage of reducing the adverse effects of

FIG. 3 is a detailed circuit diagram of the scanner circuit of FIG. The input unit 210 includes a power supply V _DD and a resistor 211 connected to the key state detection signal lines C0 to C3, respectively.
−0 to 211-3, and key state detection signal lines C0 to C
3 and inverters 212-0 to 21-21 respectively connected to
2-3. Key-on detection circuit 22
0 is constituted by a 4-input OR gate 221 connected to the output side of each of the inverters 212-0 to 212-3. The input latch circuit 230 includes an inverter 212
It comprises a 4-bit input signal storage latch circuit 231 having D terminals connected to the output sides of −0 to 212-3. An R terminal of the input signal storage latch circuit 231 receives a power-on circuit reset signal POR. The scan / oscillation operation / stop circuit 240 includes an inverter 241,
2-input NAND gate 242, flip-flops (hereinafter referred to as FF) 243, 244, 2-input NAND gate 245, 2-input AND gate 246, inverter 24
7.

An all key switch off signal ALL ZERO is input to the inverter 241. The output of the inverter 241 and the normal scan confirmation signal NOM SCAN are input to the NAND gate 242. The output of the NAND gate 242 is input to the D terminal of the FF 243,
A scan operation request signal SCAN REQ is input to a terminal, a circuit reset signal POR at power-on is input to an R terminal, and an oscillation operation / stop instruction signal OSC is input from a Q terminal.
EN is output. FF243 is connected to the D terminal of FF244.
, The output of the NAND gate 245 is input to the R terminal, and the scan enable signal SCANEN is output from the Q terminal. A clock signal φ ₂ is input to a clock terminal of the FF 244. AND gate 24
5 receives the Q terminal of the FF 243 and the power-on circuit reset signal POR, and outputs a reset timing signal. The AND gate 246 has a clock signal φ ₂ ,
The scan enable signal SCAN EN is input, and the scan operation start signal SCAN ST is output. The output of the OR gate 221 is input to the inverter 247,
Output to the S terminal of FF243.

The 1/4 frequency dividing circuit 250 includes FFs 251, 2
52, and a two-input NAND gate 253. The output of the QB terminal of the FF 252 is input to the D terminal of the FF 251, the output of the OR gate 245 is input to the R terminal, and the clock signal φ ₁ is output from the Q ₁ terminal. D terminal of the FF252 is output for Q ₁ terminal of FF1 is input, R terminal are input the output of the AND gate 245, the clock signal phi ₂ is output from the Q ₂ terminal.
The clocks φ ₁ and φ ₂ are input to the NAND gate 253, and the NAND gate 253 outputs a latch timing signal LATCH.
The scanner signal generating quarter-frequency dividing circuit 260 includes the FF 26
1,262, and NAND gates 263-0 to 263-
3 The D terminal of the FF 261 is connected to the FF 26
The output of the second QB ₂ terminal is input, the R terminal output of the AND gate 245 is input. The output of the Q ₁ terminal of the FF 261 is input to the D terminal of the FF 262, the output of the AND gate 245 is input to the R terminal, and the scan cycle end signal SCAN SYC is output from the QB ₂ terminal. The circuit 250 also functions as a scan cycle signal generation circuit.

The FF 26 is connected to the NAND gate 263-0.
The output of 1 for Q ₁ terminal, and the output of the QB ₂ terminals of FF262 is input. The FF is connected to the NAND gate 263-1.
Q ₁ output of the terminal 261, and the output Q ₂ 'terminal of the FF262 is input. NAND gate 263-2 has F
QB ₁ output terminals of the F261, and the output Q ₂ 'terminal of the FF262 is input. The NAND gate 263-3, the output of the QB ₁ terminals of the FF261, and QB ₂ output terminal of the FF262 is input. Scan timing signal generation circuit 270 includes NAND gates 271-0 to 271-27.
1-3, NOR gates 272-0 to 272-3, and inverters 273-0 to 273-3.
NAND gate 271-0 has scan enable signal SC
AN EN and the output of the NAND gate 263-0 are input. The NAND gate 271-1 has a scan enable signal SCAN EN and a NAND gate 263-1.
Is input. NAND gate 271-2 includes:
The scan enable signal SCAN EN and the output of the NAND gate 263-2 are input. NAND gate 271
-3 include scan enable signal SCAN EN and NA
The output of the ND gate 263-3 is input.

The NOR gate 272-0 receives the latch timing signal LATCH and the output of the NAND gate 263-0. The NOR gate 272-1 has a latch timing signal LATCH and a NAND gate 263-1.
Is input. The NOR gate 272-2 has a latch timing signal LATCH and a NAND gate 263.
-2 is input. The latch timing signal LATCH and the output of the NAND gate 263-3 are input to the NOR gate 272-3. Inverter 273-0
To 273-3, the scan timing signal line R
0 to R3 are output. NOR gates 272-0 to 272
-3 output latch signals L0 to L3. The output circuit 280 has a 4-bit output data latch circuit 281-0.
281-3, 4-input NOR gates 282-0 to 282
-3, and a 16-bit shift register 283. 4-bit output data latch circuit 281
The outputs of the four Q terminals of the 4-bit input signal storage latch circuit 231 are input to the four D terminals of −0 to 281-3. The outputs of the Q terminals of the output data latch circuits 281-0 to 281-3 are input to the NOR gates 282-0 to 282-3, respectively. The shift register 283 receives the output of the Q terminal of the 4-bit latch circuits 281-0 to 281-3, and receives the clock line and the LOAD line.

The key all-off detection circuit 290 comprises a 4-input NAND gate 291. NAND
The gate 291 has NOR gates 282-0 to 282-
3 is input, and all key switch off signal ALL ZERO
O is output. The INT signal generation circuit 300 includes an AND gate 301, an OR gate 302, an FF 303, an AND gate 304, an FF 305, an AND gate 306, and an
It comprises a gate 307, an OR gate 308, and an FF 309. The AND gate 301 has the FF 303 Q
The output of the B terminal and the output of the QB terminal of the FF 309 are input. The output of the AND gate 304 and the output of the AND gate 301 are input to the OR gate 302. F
The output of the OR gate 302 is input to the D terminal of F303. The output of the Q terminal of the FF 303 and the all key switch OFF signal ALL ZERO are input to the AND gate 304. An AND gate 3 is connected to the D terminal of the FF305.
04 is input. The AND gate 306 has F
The output of the Q terminal of F303, the output of the QB terminal of FF305, and the all key switch OFF signal ALL ZERO are input. The normal scan confirmation signal NOM SCAN is output from the QB terminal of the FF 303. AND gate 3
The 07, the output of the Q _A terminal of the FF303, the output of the Q _B terminal of the FF305 is input. In the OR gate 308,
The outputs of the AND gate 306 and the AND gate 307 are input. The output of the OR gate 308 is input to the D terminal of the FF 309.

FIG. 4 is a time chart showing the operation of FIG. Hereinafter, prevention of malfunction due to chattering using a dummy scan, which is one of the main contents of the present invention, will be described with reference to FIGS. When the power is turned on, the input signal storage latch circuit 231, the FF 243, the output data latch circuits 281-0 to 281-3, and the FF 309 are reset by the power-on circuit reset signal POR. The FFs 244, 2
51, 252, 261, 262, FF302, FF30
5 is reset. The FF 244 resets to S
"L" level is output to CAN EN. Therefore, N
AND gates 271-0 to 271-3 output an "H" level, and scan timing signal lines R0 to R3 are all set to "L" from inverters 273-0 to 273-3.
Become a level. Therefore, the key state detection signal lines C0 to C0
C3 is a key matrix circuit 100 connected to the outside.
To all the key switches on the lines C0 to C3. However, it is not possible to identify which key switch has been turned on. This state is a key-on detection state. Also, since the FF 243 has been reset, the OS
Since CEN is at the “L” level, the oscillation circuit 400 is stopped.

Here, when any key switch is turned on, the key state detection signal lines C0 to C3 connected to the line where the key switch exists are connected to the resistors 211-0.
To "L" level due to the output of OR gate 2
21 and the inverter 222 output an “H” level to SCAN REQ. SC changed to “H” level
AN REQ is the scan / oscillation operation / stop circuit 240
Is set. FF243 set
Sets the OSC EN line to the “H” level, and the oscillation circuit 400 outside the scanner circuit 200 starts oscillating. The oscillation signal φ ₀ given from the oscillation circuit 400 is
The clock is input to the FFs 251 and 252 of the ４ frequency divider 250. When the period of the oscillation signal φ ₀ is T, 1/4
The signals converted into the period of 4T by the FFs 251 and 252 of the frequency dividing circuit 250 are output as clocks φ ₁ and φ ₂ . The waveforms of the φ ₀ , φ ₁ , and φ ₂ signals are as shown in FIG. phi ₂ signal, scan oscillation operation / stop circuit 2
The clock is input to the FF 244 of the forty. FF243
Is set, and thus outputs an “H” level. The SCAN EN signal is set to “H” level by the FF 244 in response to the clock input of the φ ₂ signal. As a result, the scanner signal generated by the scanner signal generation quarter-frequency dividing circuit 260 is supplied to the NAND gates 271-0 to 271.
−3 is possible.

[0021] On the other hand, when SCAN EN signal becomes "H" level, phi ₂ signal periods 4T passes through the AND gate 246, the scanner signal generating 1/4 frequency divider circuit 260 as SCAN ST signal FF261 , 262
Clock. As a result, an "H" level signal having a pulse width of 4T is supplied to the NAND gate 263-.
Output in order from 0 to 263-3. The output “H” level signal is applied to NAND gates 271-0 to 271-
3. After passing through the inverters 273-0 to 273-3, "L" is input from the scan timing output terminals R0 to R3 to the key matrix circuit 100 outside the scanner circuit 200.
Output as a level. The signal waveforms of the scan timing signals R0 to R3 are as shown in FIG. Further, it outputs a frequency of SCAN SYC signal 16T which is one scan cycle time than QB ₂ terminal of the FF262. The SCAN SYC signal is FF243, 303, 3
05 and 309 are input. In synchronization with this clock signal, the INT signal generation circuit 300 determines the generation of the INT signal every time one scan cycle ends. Key matrix circuit 10 external to scanner circuit 200
During 0, the R0 signal line goes to "L" level first.
Here, if a key switch on the R0 signal line is O
If it is FF, the key state detection signal lines C0 to C
3, the terminal corresponding to the key switch in the off state is at "H" level. When this key switch is turned on, the voltage at the resistors 211-0 to 211-3 of the input unit 210 causes the corresponding terminal to go to "L" level. Thus, the on / off states of the key switches are sequentially taken into the input signal storage latch circuit 231 from the R0 line to the R3 line. The fetched data is output from the input signal storage latch 231 to the output data latches 281-0 to 281-
3 are periodically distributed by L0 to L3 signals.

Here, the transfer of data from the input signal storage latch circuit 231 to the output data latches 281-0 to 281-3 will be described. Input signal storage latch circuit 23
1 stores and outputs new data at intervals of 4T in response to the clock signal φ ₁ from the １ ／ frequency divider 250, and repeats this. This input signal storage latch circuit 23
The timing of the output state of No. 1 is as shown in FIG.
On the other hand, the "L" level signal having a pulse width T of period 4T output from the 1/4 frequency dividing circuit 250 and LATCH are NOR.
Input to the gates 272-0 to 272-3. LATC
The H signal waveform is as shown in FIG. The “L” level LATCH signal and the “L” level scan timing signal with a pulse width of 4T output from the NAND gates 263-0 to 263-3 of the scanner signal generation quarter divider circuit 260 are inverted. NO as the product of the signals
It passes through the R gates 272-0 to 272-3. This is L
0 to L3 signals. The signal waveforms of L0 to L3 are as shown in FIG. The L0 to L3 signals are input to the latch input terminals L of the output data latch circuits 281-0 to 281-3 of the output unit 280 as "H" level signals having a pulse width T. Thereby, the output data latch 281-0
281-3 take in the scan data from the input signal storage latch circuit 231.

Output data latch circuits 281-0 to 281
-3 output is a 16-bit parallel IN serial OU
Output to the T shift register 283. The parallel IN serial OUT shift register 283 receives a LOAD signal from the CPU 600 outside the scanner circuit 200,
The scan data of the output data latch circuits 281-0 to 281-3 is fetched. Then, from the CPU 600,
The CK signal is supplied, and the parallel IN serial OUT shift register 283 operates the CPU 6 from the SOUT signal line.
The scan data is output to 00. Thereafter, the scanner circuit 200 repeats output from the scan timing signal terminal, input from the key state detection signal terminal, and input of data to the parallel IN serial OUT shift register 283.

Next, it is assumed that all the key switches of the key matrix circuit 100 outside the scanner circuit 200 are turned off. When the scan cycle in which all the key switches are off is completed, the output data latch circuit 28
The outputs of 1-0 to 281-3 are all at "L" level. Therefore, the NOR gates 282-0 to 282-3
Outputs an “H” level. As a result, the NAND gate 291 sets the ALL ZERO signal to the “L” level. The ALL ZERO signal is generated by the INT signal generation circuit 3
00 and inverted by an inverter 241,
Scan / oscillation operation / stop circuit 24 as “H” level
0 is input to the NAND gate 242. At this time, NO indicating that the scan cycle is not a dummy scan
The INT signal generation circuit 300 sets the MSCAN signal to “H”.
When the level is set, the NAND gate 242 outputs an “L” level signal to the FF 243. FF243 is OSC
The EN signal and the input of the FF 244 are set to “L” level. Thus, the oscillation circuit 400 outside the scanner circuit 200
Stops oscillation.

At the same time, the FF 244 sets SCAN EN to the "L" level, so that the NAND gates 271-0 to 271-0
271-3 outputs an "H" level, and all the scan timing signal terminals R0 to R3 are at an "L" level.
That is, the state returns to the key-on detection state. At the end of the description of the operation of the scanner circuit 200, the INT signal generation circuit 3
00 and the dummy scan will be described. When the power is turned on, the FFs 300 and 30 of the INT signal generation circuit 300 are turned on.
5, 309 are reset, and the output INT signal of the FF 309 starts at "L" level. Here, if any one of the key switches of the key matrix circuit 100 is pressed, the SCAN SYC signal indicating the end of the scan cycle is generated by the scanner signal generation quarter-frequency dividing circuit 260 after the end of the first scan cycle. The first scan SYC signal is used as a clock and the FF 303
"H" level, FF305 is "L" level, FF30
9 outputs the “L” level. That is, no INT signal is generated. This result is obtained by the key all-off detection circuit 290.
Does not depend on the level of the output ALLZERO signal. On the other hand, regarding the oscillation operation, since the level of the NOM SCAN signal at the time of reset is “L” level, the FF 243 of the scan / oscillation operation / stop circuit 240 sets the first SCA
Even if the N SYC signal is input, the OSC EN signal maintains the “H” level, and the oscillation continues.

Next, if the key switch is still on when the second SCAN SYC signal is input, the ALL ZERO signal is at "H" level. Therefore, the FF 303 outputs an “H” level, the FF 305 outputs an “H” level, and the FF 309 outputs an “H” level. That is, 2
At the end of the second scan cycle, an INT signal is output. Regarding the oscillating operation, since the level of the NOM SCAN signal at the end of the first scan cycle is at the “H” level, the oscillating operation is continued for the above-described reason. Hereinafter, when the key switch is in the ON state, similarly to the end of the second scan cycle, every time the scan cycle ends,
An INT signal is output, and oscillation continues.

Next, when the key all-off detection circuit 290 detects that all the key switches are in the off state, the ALL ZERO signal becomes "L" level. Therefore, when the SCAN SYC signal is input, F
F303 is at “L” level, FF305 is at “L” level,
The FF 309 outputs an “H” level. Therefore, also at this time, the INT signal is output. Regarding the oscillation operation, the NOM SCAN signal is at “H” level,
Since the LZERO signal is at “H” level, FF243
In response to the input of the SCAN SYC signal, the OSCEN signal is set to the “L” level, and the oscillation stops. Scan data can be captured by the CPU 600 outside the scanner circuit 200 by outputting an interrupt signal to the CPU 600 from the INT signal line. When the INT signal is at “H” level, the CPU 600 can take in scan data from the parallel IN serial OUT shift register 283. After the completion of the capture by the CPU 600, the INT RST becomes “H” level and the FF309
Is reset, and the INT signal is set to the “L” level. I
The NT signal generation circuit 300, as described above,
After ERO changes from “H” level to “L” level,
The INT signal is maintained at "L" level until the second clock is input. That is, scanning starts when any key switch is turned on from the state where all key switches are off, but the INT signal at the end of the first scan cycle is not generated. Therefore, the CPU 600 does not take in the scan data from the first scan. This first scan cycle is a dummy scan.

Next, advantages of the dummy scan according to the embodiment of the present invention with respect to chattering will be described in detail. FIG.
8 are time charts of signals generated by the operation of the key input device of FIG. 1 incorporating the scanner circuit of FIG. In the following example, the scan timing signal line R
It is assumed that only the key switch SW1 at the intersection of the key switch 1 and the key state detection signal line C1 performs the ON / OFF operation, and the other key switches are always off ("H" level). Therefore, only when the R1 signal is at the “L” level or in the key-on detection state, the state of SW1 appears in the C1 signal.
FIG. 5 is a diagram illustrating a case where chattering is shorter than a scan cycle. SW1 indicates the on / off state of the key switch SW1. SCAN REQ indicates the signal level of the output of the key ON detection circuit 220. C0 to C3 indicate signal levels of the key state detection signal terminals C0 to C3. R
0 to R3 indicate signal levels of the scan timing signal terminals R0 to R3. INT indicates the signal level of the interrupt signal INT. CPU DATA (SW1) is CPU6
00 indicates the on / off state of the key switch SW1 to be read.

Initially, all key switches are off. Therefore, C0 to C3 are at "H" level, and S0
CAN REQ is at the “L” level. R0 to R3 are all in the "L" level key ON detection state. Since the scanning is stopped, INT is at the “L” level. C
PU DATA (SW1) indicates the OFF state of SW1. When the switch SW1 is turned on, there is a nuance mixed from outside the circuit. Chattering (which occurs due to poor contact of the SW itself) occurs. By the first ON operation by chattering, the SCAN REQ goes to the “H” level and scanning starts (time point a). However, the first scan cycle T1 is a dummy scan, and T1
After the termination, INT remains at the “L” level. In the second scan cycle T2, chattering has already ended, and SW1 is stable in the ON state. The “L” level of C1 scanned at the point b is taken into the CPU 600 when INT goes to “H” level after the end of T2. This is the rising edge of CPU DATA (SW1) (c
Time). When the loading of the CPU 600 is completed,
INT is returned to the "L" level. After that, the scan cycle is repeated, but since SW1 is stable in the ON state, CPU DATA (SW1) maintains the ON state.

As described above, the influence of chattering when SW1 rises due to the dummy scan does not affect the CPU 600. Similarly, a case where SW1 is turned off from the on state under the condition that chattering is shorter than the scan cycle will be described with reference to FIG. When SW1 is turned off, chattering occurs. At the time point d of the scan cycle T4, it is detected that C1 has changed to the "H" level for the first time. As a result, after the end of T4, it is determined to be ALL ZERO, the scanning is stopped, and the state returns to the key-on detection state.
The “H” level of C1 scanned at the time point d is changed to the “H” level at the end of T4 by the CPU 6
00 is taken in. This is the CPU DATA (SW
1) falls (at the point e). Thus, SW
After turning off 1, CPU DATA (SW 1) maintains the off state after the off state taken into CPU 600 for the first time. Thus, CPU DATA (SW1) has a waveform free from the influence of chattering. As described above, when the chattering is shorter than the scan cycle, the malfunction of the CPU 600 due to the chattering can be prevented by using the dummy scan and the scan stop at the time of ALL ZERO.

Next, a case where chattering is longer than a scan cycle will be described with reference to FIG. Initially, all key switches are in the off state, and the scanner circuit 200 is in the key on detection state. When SW1 is turned on, chattering occurs. Until the dummy scan T5 ends, the description is the same as that in the case of FIG. FIG.
In the example, chattering still remains after the dummy scan T5 ends. At the time point f of the normal scan T6, C
When the "H" level of 1 is scanned, ALL ZERO
It is determined as O, the scanning is stopped, and the state returns to the key-on detection state (time point g). The “H” level of C1 scanned at the point f is changed to the “H” level at the end of T6, and is taken into the CPU 600. Therefore, CPU
DATA (SW1) maintains the off state. At time point g, the scanner circuit 200 enters the key ON detection state,
Since W1 is already stable, SCAN REQ goes to the "H" level instantaneously and scanning resumes (time h). The scan cycle at the time of restart is a dummy scan, and INT remains at "L" level.

The "L" level of C1 is scanned at the time point i in the next scan cycle, and after the scan cycle, INT goes to "H" level and the CPU 600 receives the scan data of C1. This is the CPU DA
TA (SW1) rises (time j). After that, the scan cycle is repeated, but since SW1 is on and stable, CPU DATA (SW1)
Maintain the ON state. As described above, the influence of chattering when SW1 rises due to the dummy can is reduced by the CPU 6.
That's less than 00. Similarly, a case where SW1 is turned off under the condition that chattering is longer than the scan cycle will be described with reference to FIG. After SW1 is turned off, CPU DATA (SW1) falls at the time point k,
Until the scanning is stopped and the key-on is detected (at the point of time 1), the description is the same as that in FIG.

However, in the example of FIG. 6, since chattering still continues, SCAN is performed by the first chattering ON operation immediately after the state changes to the key-on detection state.
REQ becomes “H” level, and scanning restarts (time point m). The scan cycle T8 at the time of restart is a dummy scan, and INT remains at the "L" level even after the end of T8. Therefore, CPU DATA (SW1)
Maintain the OFF state. Next scan cycle T9
At time n, SW1 is already in the OFF state and stable, and the "H" level of C1 is scanned. After the end of T9, ALL ZERO is determined, the scan is stopped,
The key-on detection state is set. When the signal INT goes high, the CPU 600 takes in the scan data of C1. However, this scan data is stored in SW1
Indicates the OFF state of CPUDATA (SW
1) maintains the OFF state. Thus, the CPU DA
TA (SW1) has a waveform free from the influence of chattering. As described above, even when the chattering is longer than the scan cycle, the dummy scan and the ALL Z
C by chattering using scan stop at ERO
A malfunction of the PU 600 can be prevented. FIG. 7 is a time chart of a circuit that does not use dummy can when the same chattering as in FIG. 6 occurs in SW1. FIG.
As shown in the figure, both rising and falling edges of CPU DATA (SW1) are affected by chattering.

Next, the effect of dummy can when noise is mixed when the key switch is turned off will be described with reference to FIG. Here, all the key switches are in the off state, and the scanner circuit 200 is in the key on detection state. If noise is mixed in SW1, SCAN R
The EQ goes to the “H” level, and scanning starts. The scan cycle T10 is a dummy scan and is executed by the CPU.
600 does not take in scan data. Furthermore, when the normal scan cycle T11 starts, SW1 has already returned to the steady OFF state. for that reason,
The data scanned from C1 is at the “H” level, and after the end of T11, when INT goes to the “H” level, the scan data taken into the CPU 600 is SW.
1 is in an off state. As described above, even when noise is mixed, the CPU DATA (SW1) continues to maintain the off state. As described above, when there is no input to the key switch,
In addition to stopping scanning, the oscillation circuit 400 is also stopped to reduce current consumption and high frequency noise caused by scanning.
It is possible to prevent the malfunction of the CPU 600 due to chattering by using the scan stop and the dummy scan.

It should be noted that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications. (1) In the embodiment, a key matrix circuit having 4 × 4 = 16 key switches is used. However, the present invention can be applied to a circuit having more key switches. (2) In the embodiment, only the first scan cycle is set as the dummy scan after the start of the scan. However, the dummy scan time can be increased depending on the performance (length of chattering) of the key switch. (3) The present embodiment is considered to be widely applied to products having a keyboard having a large number of segments, particularly to in-vehicle electronic products, AV products, and portable communication devices expected to have low current consumption, low heat generation, and small size. Can be

[0036]

As described in detail above, the first, third, and third
According to the fourth aspect, when all the key switches are turned off, the oscillation operation of the oscillation circuit is stopped, so that the current consumption can be reduced. According to the second, third, and fifth aspects, an interrupt signal is not output to the CPU within a specific scan cycle after the start of scanning, so that malfunction due to chattering can be avoided.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a key input device according to an embodiment of the present invention.

FIG. 2 is a functional block diagram of the scanner circuit of FIG.

FIG. 3 is a detailed view of the scanner circuit of FIG. 2;

FIG. 4 is a time chart of FIG. 2;

FIG. 5 is a time chart illustrating advantages of the circuit of FIG. 2;

FIG. 6 is a time chart illustrating advantages of the circuit of FIG. 2;

FIG. 7 is a time chart when a dummy scan is not used.

FIG. 8 is a time chart showing the influence of noise on the circuit of FIG. 2;

[Explanation of symbols]

REFERENCE SIGNS LIST 100 key matrix circuit 200 scanner circuit 210 input section 220 key-on detection section 230 input latch circuit 240 scan / oscillation operation / stop circuit 250 1/4 frequency divider 260 scanner signal generation 1
/ 4 frequency divider 270 scan timing signal generator 280 output circuit 290 key all-off detector 300 INT signal generator 400 oscillation circuit 500 CPU interface 600 CPU

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Teruyuki Fujii 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Nobuyuki Shimizu 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (56) References JP-A-3-55619 (JP, A) JP-A-4-205217 (JP, A) JP-A-2-242316 (JP, A) JP-A-6-206 102986 (JP, A) JP-A-8-194570 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 3/02 330

Claims (5)

(57) [Claims] 1. A key matrix circuit in which a plurality of key switches are arranged in a matrix, one of an X axis and a Y axis is a scan timing signal line and the other is a key state detection signal line, and an operation timing signal is generated. An oscillation circuit that outputs a scan timing signal to the scan timing signal line, and detects an on / off state of the key switch from the key state detection signal line, and controls the oscillation circuit. In the key input method of the key input device, the scanner circuit includes: an oscillation stop process for stopping an oscillation operation of the oscillation circuit if there is no input of the key switch in an on state; A key that outputs a timing signal to detect the ON state of the key switch Performing an on-state detection process, if there is an input of the key switch in an on-state, an oscillation operation process for causing the oscillation circuit to perform an oscillation operation, and sequentially outputting the scan timing signal to the scan timing signal line, Performing a scanning process for detecting an on / off state of each of the key switches. 2. A key matrix circuit in which a plurality of key switches are arranged in a matrix, one of an X axis and a Y axis is a scan timing signal line and the other is a key state detection signal line, and an operation timing signal is generated. An oscillating circuit for outputting a scan timing signal to the scan timing signal line, detecting an on / off state of the key switch from the key state detection signal line, and terminating a fixed scan cycle of the scan timing signal;
A scanner circuit for outputting an interrupt signal to a central processing unit that captures scan data indicating the on / off state of the key switch. A key input method for a key input device, comprising: a key switch in an on state. If there is no input, the scan timing signal is always output to all the scan timing signal lines, and a key-on state detection process for detecting the on-state of the key switch is executed. If so, the scan timing signal is sequentially output to the scan timing signal line to start a scan for detecting the on / off state of each of the key switches. After the start of the scan, until a specific number of scan cycles are completed. Each time the specified number of scan cycles are performed Executing an interrupt signal output process for outputting the interrupt signal to the central processing unit every time a scan cycle is executed after the specific number of scan cycles are completed without outputting the interrupt signal to the central processing unit. A key input method characterized by doing so. 3. A key matrix circuit in which a plurality of key switches are arranged in a matrix, one of an X axis and a Y axis is used as a scan timing signal line and the other is used as a key state detection signal line, and an operation timing signal is generated. An oscillation circuit for outputting a scan timing signal to the scan timing signal line; detecting an on / off state of the key switch from the key state detection signal line; controlling the oscillation circuit; After a fixed scan cycle, turn on / off the key switch.
A scanner circuit that outputs an interrupt signal to a central processing unit that captures scan data indicating an off state, a key input method of a key input device, wherein the scanner circuit does not have an input of the key switch in an on state. An oscillation stop process for stopping the oscillation operation of the oscillation circuit, and a key-on state detection process for constantly outputting the scan timing signal to all the scan timing signal lines and detecting an on-state of the key switch, When there is an input of the key switch in the ON state, an oscillating operation process for causing the oscillating circuit to perform an oscillating operation, and sequentially outputting the scan timing signal to the scan timing signal line to turn on / off each of the key switches Start a scan to detect a specific number of scan Until the cycle is completed, the interrupt signal is not output to the central processing unit every time the specific number of scan cycles are executed, and after the specific number of scan cycles, the scan cycle is executed. Executing an interrupt signal output process for outputting the interrupt signal to the central processing unit each time the key input is performed. 4. A key matrix circuit in which a plurality of key switches are arranged in a matrix, one of an X axis and a Y axis is a scan timing signal line and the other is a key state detection signal line, and an operation timing signal is generated. An oscillation circuit that outputs a scan timing signal to the scan timing signal line, and detects an on / off state of the key switch from the key state detection signal line, and controls the oscillation circuit. In the key input device, the scanner circuit includes: a key-on detection unit that detects an input of the key switch in an on state; a key all-off detection circuit that detects that all the key switches are turned off during scanning; That all the key switches are turned off by the key all-off detection unit A scan / oscillation operation / stop circuit for stopping the oscillation operation of the oscillation circuit when detected, and for oscillating the oscillation circuit when the key-on detection unit detects an input of the key switch in an on state. When the key all-off detection unit detects that all of the key switches are turned off, the scan timing signal is always output to all the scan timing signal lines, and the key-on detection unit turns on the scan timing signal. And a scan timing signal generating circuit for sequentially outputting the scan timing signal to the scan timing signal line when the input of the key switch in the state is detected. 5. A key matrix circuit in which a plurality of key switches are arranged in a matrix, one of an X axis and a Y axis is a scan timing signal line and the other is a key state detection signal line, and an operation timing signal is generated. An oscillating circuit for outputting a scan timing signal to the scan timing signal line, detecting an on / off state of the key switch from the key state detection signal line, and terminating a fixed scan cycle of the scan timing signal;
And a scanner circuit that outputs an interrupt signal to a central processing unit that captures scan data indicating the on / off state of the key switch. The key input device, wherein the scanner circuit detects an input of the key switch in an on state A key-on detection circuit, a key-all off detection circuit for detecting that all the key switches are turned off during scanning, a scan cycle signal generation circuit for outputting a scan cycle end signal, and a key-off detection circuit. Based on the output and the scan cycle end signal, after the start of the scan, until the specific number of scan cycles ends, the interrupt signal is sent to the central processing unit every time the specific number of scan cycles is executed. Output after the specified number of scan cycles, An interrupt signal generation circuit that outputs the interrupt signal to the central processing unit every time a cycle is executed; and if the key all-off detection unit detects that all of the key switches have been turned off, The scan timing signal line is always output to the scan timing signal line, by the key-on detection circuit,
When the input of the key switch in the ON state is detected,
A scan timing signal generating circuit for sequentially outputting the scan timing signal to the scan timing signal line.