JP2899869B2 - Error detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for accurately distinguishing between bit errors and bit slips in a digital signal in an error detector for detecting errors in a digital signal transmitted by a transmission line or a transmission device of a digital communication network. .

[0002]

2. Description of the Related Art As a method for evaluating a digital signal transmission system, error measurement has been conventionally performed. Error measurement is
The pseudorandom signal is input to the transmission system under test, the signal output from the transmission system under test is input to the error detection device, and the input signal matches the reference pseudorandom signal generated in the device. The mismatch is determined on a bit-by-bit basis, and the error rate is determined from the number of times the mismatch is determined within a predetermined time.

[0003] By the way, errors generated by the transmission system include the reference data of FIG.
In addition to what is called a bit error in which the levels of the intermediate data D1 and A2 are simply inverted as shown in FIG. 6, the intermediate data D1 and E1 are omitted as shown in FIG. There is a so-called bit slip in which unnecessary data X is inserted in the middle and the subsequent data is shifted from the reference data.

When this bit slip occurs, the phase of subsequent data is shifted from the reference data.
Subsequent comparison results are meaningless.

[0005] For this reason, it is distinguished whether the generated error is caused by a bit error or a bit slip. If a bit slip occurs, the phase of the reference data is synchronized with the input signal, and then the error measurement is restarted. There is a need.

As a technique for realizing this, Japanese Patent Laid-Open No.
[0025] A first PN signal generation circuit that generates a pseudo-random signal by self-running using a received signal sequence as an initial pattern, and a second PN signal generation circuit that generates a pseudo-random signal while constantly receiving the received signal sequence A first error determination circuit that compares the received signal with the output of the first PN signal generation circuit on a bit basis, and a second error that compares the received signal with the output of the second PN signal generation circuit on a bit basis A determination circuit for determining the number of times the first and second error determination circuits determine a mismatch within a predetermined time t. When the number of mismatch determinations of the first error determination circuit is greater, the bit slip is reduced. The present applicant has proposed a technique of performing a synchronization pull-in operation of the first PN signal generation circuit by determining that the occurrence has occurred.

In this technique, when a signal including a bit error is input, the first error determination circuit determines a mismatch by the number of error data, whereas the second error determination circuit determines the error. Since the number of data and the second PN signal generating circuit make a mismatch determination for the total of the mismatch caused by fetching the error data, the number of mismatch determinations of the second error determination circuit increases, and , When a signal including a bit slip is input, the first error determination circuit continues to make a mismatch determination with a probability of 1/2 until a predetermined time t elapses with respect to a data string input after the occurrence of the bit slip. On the other hand, after the occurrence of a bit slip, the second error determination circuit causes the second PN signal generation circuit to convert the data sequence after the bit slip into a predetermined number of bits (shift of the PN signal generation circuit). Since mismatch determination only a probability of 1/2 until register the number of stages) capturing a second PN
If the predetermined time t is set to be longer than the time required for the signal generation circuit to take in data corresponding to the number of stages of the shift register, the fact that the number of mismatch determinations of the first error determination circuit is larger is utilized. Things.

[0008]

However, according to this technique, when a bit slip occurs a plurality of times within a predetermined time t, when a bit slip longer than the predetermined time t occurs, or when there are many bit errors, the predetermined time t It is conceivable that the number of times the first error determination circuit makes a mismatch determination and the number of times the second error determination circuit makes a mismatch determination approach, and the magnitude relationship is reversed. Then, the occurrence of the bit slip cannot be correctly recognized.

An object of the present invention is to improve this point and to provide an error detecting device which can recognize the occurrence of a bit slip accurately without being affected by the length of a bit slip and the frequency of occurrence of a bit error. And

[0010]

In order to achieve the above object, an error detecting apparatus according to the present invention comprises:
A first pseudo-random signal generating circuit (20) having a shift register (21), and an exclusive-OR circuit (22) for performing an exclusive-OR operation on a plurality of outputs of the first shift register; A first match / mismatch determination circuit (23) for determining match / mismatch between a signal output from the first pseudo-random signal generation circuit and a received signal on a bit-by-bit basis;
A second shift register (25) having the same number of stages as the first shift register, an exclusive OR circuit (26) for performing an exclusive OR operation on a plurality of outputs of the second shift register;
A switch (27) for switching between the output of the exclusive OR circuit and a received signal and inputting the received signal to the second shift register, and performs a synchronization pull-in operation when the second shift register inputs a received signal. When the output of the exclusive-OR circuit is input after the synchronization is determined, a second pseudo-random signal generation circuit (24) for generating a pseudo-random signal and an output from the second pseudo-random signal generation circuit In an error detection device including a second match / mismatch determination circuit (28) for performing a match / mismatch determination between a signal and a received signal on a bit-by-bit basis, in response to the second match / mismatch determination circuit determining that there is a mismatch. First detecting means (31, 3) for detecting that the first match / mismatch determination circuit has made a match determination for a first predetermined number of bits (N) continuously;
4, 35) and that the second match / mismatch determination circuit has made a match determination for a second predetermined number of bits (M) continuously in response to the second match / mismatch determination circuit making a mismatch determination. In response to the second detection means for detecting (32) and the second match / mismatch determination circuit making a mismatch determination, the second match / mismatch determination circuit determines the match by the second match / mismatch determination circuit.
And a third detection means (32) for detecting that the predetermined number of bits have not been consecutive, and it is recognized that a slip has occurred in the received signal based on the detection results of the first, second and third detection means. It is configured to be.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram illustrating a configuration of an error detection device according to an embodiment.

In FIG. 1, a first pseudo random signal generation circuit 20 includes a plurality of (K) -stage shift registers 21,
The shift register 21 includes an exclusive OR circuit (hereinafter referred to as an EXOR circuit) 22 that performs an exclusive OR operation on the output of the predetermined stage and the output of the final stage, and shifts the received signal S in synchronization with a clock signal (not shown). The EXOR circuit 22 takes in the first stage of the register 21 and sequentially shifts to the last stage.
To output a pseudo-random signal.

The output of the EXOR circuit 22 is input to the first match / mismatch determination circuit 23 together with the reception signal S. First
Is determined, for example, by an EXOR circuit. The EXOR circuit 22 compares the output of the EXOR circuit 22 with the received signal S on a bit-by-bit basis. Is output.

The output of the last stage of the shift register 21 of the first pseudo-random signal generation circuit 20, that is, the received signal S is
The signal S ′ delayed by a bit is input to the second pseudo-random signal generation circuit 24. The second pseudo-random signal generation circuit 24 includes a K-stage shift register 25, an EXOR circuit 26 that performs an exclusive-OR operation on the outputs of the predetermined stage and the last stage of the shift register 25, and an output of the EXOR circuit 26. And a switch 27 for selectively inputting any one of the last-stage output (received signal S ′) of the shift register 21 of the pseudo-random signal generation circuit 20 to the first stage of the shift register 25. When connected to the first pseudo-random signal generating circuit 20, the received signal S 'is taken into the first stage of the shift register 25 and sequentially shifted to the last stage, and the switch 27
When connected to the R circuit 26, the output signal of the EXOR circuit 26 is taken into the first stage of the shift register 25 and sequentially shifted to the last stage to generate a pseudo-random signal autonomously.

The output signal of the EXOR circuit 26 is input to a second match / mismatch determination circuit 28 together with the reception signal S '. The second match / mismatch determination circuit 28 is an EXOR circuit 2
6 is compared with the received signal S 'in bit units. For example, a determination signal is output which is low if they match and high if they do not match.

First and second match / mismatch determination circuits 2
The outputs of 3 and 28 are input to the slip determination unit 30.
The slip determination unit 30 includes a first counter 31, a second counter 32, and a determination circuit 33.

The first counter 31 counts the clock signal CK synchronized with the bit rate of the received signal, and outputs a high-level carry signal every time the clock signal is input N times (where K <N). Then, when receiving a determination signal indicating a mismatch from the first match / mismatch determination circuit 23, it is reset, and counting is restarted from the beginning.

That is, the first counter 31 detects the N-bit continuity of the match judgment by the first match / mismatch judgment circuit 23. The first counter 31 has a first flip-flop 34 and an AND Together with the circuit 35, it constitutes the first detection means of this embodiment.

The second counter 32 counts the clock signal CK and outputs the clock signal M times (where K <
M <N) Each time a signal is input, a high-level carry signal is output, for example. When a determination signal indicating a mismatch is received from the second match / mismatch determination circuit 28, the signal is reset and counting is restarted from the beginning.

That is, the second counter 32 is for detecting whether or not M bits have been continuously output as a match determination after the second match / mismatch determination circuit 28 has determined a mismatch. This forms second and third detection means.

The determination circuit 33 includes a first flip-flop 34 and an AND circuit 35 as shown in FIG.
And the second flip-flop 36.

When the determination circuit 33 receives a signal indicating a mismatch determination from the second match / mismatch determination circuit 28, it sets the output of the first flip-flop 34 to a high level, and the first and second counters 31 , 32 until a carry signal is output.

When the first counter 31 outputs a carry signal first, it is determined that a bit slip has occurred, and the carry signal and the first flip-flop 3 are output.
The output of the AND circuit 35 which takes the logical product with the output of the
Of the flip-flop 36 is set to a high level, and the switch 27 is switched to the reception signal S 'side by this high level output, so that the reception signal S' is taken into the second shift register 25 and the second coincidence is performed. A signal indicating a match determination is continuously output from the mismatch determination circuit 28 to the second counter 32.

When the second counter 32 outputs the carry signal first, the first and second flip-flops 34 and 36 are reset, and the second match / non-match judgment circuit 28 sets Wait until you make a decision.

That is, as shown in FIG. 2, when the second match / mismatch determination circuit 28 is in the pattern monitoring state J1 where the second match / mismatch determination circuit 28 waits for a mismatch check, as shown in FIG. When the discrepancy is determined, the state is changed to a determination waiting state J2 in which the first and second counters 31 and 32 wait for the output of the carry signal to determine whether the discrepancy is due to a bit error or a bit slip.

When the M-bit continuity of the match judgment of the second match / mismatch judgment circuit 28 is confirmed by the carry signal of the second counter 32 after entering the judgment waiting state J2, it is judged that a bit error has occurred. Then, the state returns to the pattern monitoring state J1, and after the state becomes the judgment waiting state J2, the first match / mismatch determination circuit 23 does not confirm the M-bit continuity of the match determination of the second match / mismatch determination circuit 28. Is determined by the logical sum output of the carry signal of the first counter 31 and the high-level output of the first flip-flop 34, it is determined that a bit slip has occurred and the fetch waits. Condition J
Move to 3.

In the fetch wait state J3, the M-bit continuity of the match judgment of the second match / mismatch judgment circuit 23 is the second.
Is determined by the carry signal of the counter 32, the receiving of the received signal S 'is determined to be completed, and the process returns to the pattern monitoring state J1. Note that the second flip-flop 3
The number of times that 6 outputs a high-level signal is counted by the slip counter 40, and if this count value is displayed on a display device (not shown), the number of occurrences of bit slips can be determined.

Next, the operation of this embodiment will be described. In the following description, the number of stages K of the shift registers 21 and 25 of the first and second pseudo-random signal generators 20 and 24 is assumed to be six.

As shown in FIG. 3A, a 6-bit error-free received signal sequence A0-F0 is previously taken into the shift register 25 of the second pseudo-random generating circuit 24, and the first pseudo-random signal is generated. It is assumed that the shift register 21 of the random generation circuit 20 has received error-free received signal sequences A1 to F1 following the signal sequences A0 to F0, and that A2 is input as the next data.

At this time, the second match / mismatch determination circuit 28
EXOR of the second pseudo random signal generation circuit 24
Since the data A1 generated by the circuit 26 and the data A1 of the last stage of the shift register 21 of the first pseudo random signal generation circuit 20 are input, the second match / mismatch determination circuit 28 determines the match Is output. The first match / mismatch determination circuit 23 stores the data A generated by the EXOR circuit 22 of the first pseudo-random signal generation circuit 20.
2 and the next received signal data A2, the second match / mismatch determination circuit 23 outputs a determination signal indicating a match.

The operation when the received signal S contains a bit error with the state of FIG. 3A (pattern monitoring state J1) as an initial state will be described.

FIG. 4 is a timing chart showing the operation when the reception signals S including bit errors are sequentially input from the state shown in FIG.

As shown in FIG. 4A, the data A
When an error bit obtained by inverting the data B2 after 2 is input, the first match / mismatch determination circuit 23 outputs a high-level signal indicating mismatch as shown in FIG. 4B. Also, as shown in FIGS. 3B and 3C, when the erroneous data is present in the fifth and last stages of the first shift register 21, the first match / mismatch determination circuit 23 does not match. Is output.

The first counter 31 resets the count value to 0 every time a high-level signal indicating a mismatch is output from the first match / mismatch determination circuit 23 as shown in FIG. The signal CK is counted, and the counted value is N
Every time it becomes (for example, 8), a carry signal is output as shown in FIG.

On the other hand, as shown in FIG. 4 (e), the received signal S 'input with a delay of 6 bits with respect to the received signal S and the signal generated by the second pseudo-random signal generating circuit 24 by itself. Second match / mismatch determination circuit 28 that compares
As shown in FIG. 4 (f), the first match / mismatch determination circuit 23 makes a mismatch determination at the timing of the third mismatch determination. By this mismatch determination, the count value of the second counter 32 is reset to 0 as shown in FIG. 4G, and the first flip-flop 3 of the determination circuit 33
4 is set as shown in FIG.

After the second match / mismatch determination circuit 23 makes a mismatch determination (judgment waiting state J2), the first counter 31
4 and the count value of the second counter 32 shown in FIG. 4H continuously and monotonically increase from the initial value 1, so that M bits (for example, 7 bits) continue from the data C2 to the received signal. If there is no error, the second counter 32 always outputs the carry signal first and resets the first and second flip-flops 34 and 36 of the determination circuit 33.
The process returns to the pattern monitoring state J1 described above.

Therefore, the second flip-flop 36
Does not go to the high level as shown in FIG. 4 (j), and it can be understood that the mismatch determination by the second match / non-match determination circuit 28 is based on a bit error.

Even when a plurality of erroneous data are successively input, the above operation is performed from the timing when the last error data is input as the reception signal S '. The output never goes high.

Next, an operation when a bit slip occurs with the state of FIG. 3A as an initial state will be described.

FIG. 5 shows that, from the state shown in FIG. 3 (a), as shown in FIG. 3 (d), after the data A2, two data B2 and C2, which should originally follow, are omitted and the data D2 is input. 6 is a timing chart showing an operation when the operation is performed.

The first coincidence / non-coincidence determination circuit 23 starts the operation after the data D2 is inputted as shown in FIG.
The data D2 is supplied to the first pseudo-random signal generation circuit 20.
Until the final stage of the first shift register 21
As shown in FIG. 5B, a high-level signal indicating a mismatch is output with a probability of 1/2. However, data E3 input following data D2 has reached the final stage of the first shift register 21. Thereafter, a low-level signal indicating a match determination is continuously output.

Therefore, the first counter 31
As shown in (c) of FIG.
During the period in which the signal indicating the mismatch is output with a probability of / 2 (undefined period), the signal is reset by the mismatch determination and the carry signal is not output, and after the undefined period has elapsed, the low level indicating the match determination is reached. Since the signal is continuously received, the counting result continuously and monotonically increases.

On the other hand, as shown in FIG. 5 (e), the received signal S 'which is input with a delay of 6 bits with respect to the received signal S and the signal generated by the second pseudo-random signal generating circuit 24 by itself. Second match / mismatch determination circuit 28 that compares
As shown in FIG. 5F, the data D2 is stored in the first shift register 2 of the first pseudo-random signal generation circuit 20.
After reaching the final stage of 1, a high-level signal indicating a mismatch is output with a probability of 1/2. The second counter 32 is frequently reset as shown in FIG. 5 (g) by the mismatch determination, so that no carry signal is output as shown in FIG. 5 (h). In addition, the first flip-flop 34 of the determination circuit 33 holds the set state as shown in FIG.

During this time (judgment waiting state J2), as described above, the count value of the first counter 31 continuously increases monotonously, so that the second coincidence / non-coincidence determination circuit 23 first performs a non-coincidence determination. At the latest timing when N-bit data is input, the count value of the first counter 31 becomes N
And a carry signal is output. By the carry signal, the output of the second flip-flop 36 of the determination circuit 33 is set to a high level as shown in FIG. 5 (j), indicating the occurrence of a bit slip.

The second flip-flop 36
Is set to high level (waiting for capture J
3) The switch 27 is switched to the reception signal S 'side, and a signal indicating a match determination is continuously output from the second match / mismatch determination circuit 28, and the count value of the second counter 32 is continuously monotonic. To increase. Therefore, the second counter 32
Is received by the second shift register 25 until the carry signal is output from the second counter 32, the first and second flip-flops are output. 34 and 36 are reset, the switch 27 is switched to the EXOR circuit 26 side, and FIG.
To the initial state (pattern monitoring state J1).

Since the number of occurrences of the bit slip is counted by the slip counter 40, if the counting result is displayed on a display device (not shown), the transmission system for the bit slip can be evaluated.

Although the description has been given of the case where the slip of two missing bits has occurred, the same operation as described above is performed even when there is a longer slip of missing bits. Also, when a received signal into which unnecessary bits are inserted is input, the same operation as described above is performed only by changing the indefinite period according to the length of the inserted unnecessary bits, and the bit slip is reduced. Upon detection, an acquisition process for synchronization is performed. As described above, since the length of the bit slip can be flexibly dealt with, even if the bit slip occurs continuously plural times, the bit slip can be reliably detected as described above.

As described above, in this error detection device, it is determined whether the first and second coincidence / non-coincidence determination circuits 23 and 28 perform the coincidence determination continuously for a predetermined number of bits (N, M).
By detecting in response to the second coincidence / non-coincidence determination circuit 28 performing a non-coincidence determination, it is determined whether the generated bit error is due to a bit error or a bit slip. Even when there are many bits and when there is a long bit slip, both can be reliably distinguished.

[0049]

In the above embodiment, the N-bit first counter 31 and the M-bit second counter less than N are compared with each other after the second coincidence / non-coincidence determination circuit 28 makes a non-coincidence determination.
The bit error or the slip is distinguished depending on which of the counters 32 outputs the carry signal first, but this is due to the circuit configuration and does not limit the present invention.

That is, even when the number of bits M is set to be equal to the number of bits N, or when the number of bits M is set to be larger than the number of bits N, the second match / mismatch determination circuit 28 performs the first match after determining the mismatch. If the N-bit continuity of the match determination by the match / mismatch determination circuit 23 is not confirmed and the M-bit continuity of the match determination by the second match / mismatch determination circuit 28 is not confirmed, it is determined that a bit slip has occurred. If the M-bit continuity of the match determination by the first match / mismatch determination circuit 23 is confirmed after the match / mismatch determination circuit 28 determines the mismatch, it may be determined that a bit error has occurred.

In the above-described embodiment, the signal output from the last stage of the first shift register of the first pseudo-random signal generation circuit is input to the second pseudo-random signal generation circuit as a reception signal. However, a received signal is input from the first or intermediate stage of the first shift register to the second pseudo-random signal generation circuit, or
May be provided with a plurality of stages of shift registers in front of the pseudo random signal generation circuit, and the received signal S may be input to the shift registers.

[0052]

As described above, the error detection apparatus of the present invention provides a pseudo-random signal output between the output of the first pseudo-random generating circuit and the received signal, which always generates the pseudo-random signal while always taking the received signal into the internal shift register. A first match / mismatch determination circuit for determining match / mismatch, and a second match / mismatch determination between an output of a second pseudo-random generation circuit for automatically generating a pseudo-random signal after receiving the received signal and the received signal. And an error detection device having two coincidence / non-coincidence determination circuits, wherein the first coincidence / non-coincidence determination circuit continuously determines the first predetermined number of bits in response to the second coincidence / non-coincidence determination circuit performing a non-coincidence determination. In response to the first detecting means for detecting the occurrence of the occurrence of the error and the second coincidence / non-coincidence determination circuit making a non-coincidence, the second coincidence / non-coincidence determination circuit continuously performs the second predetermined number of bits. Second detecting means for detecting that a match has been made, and in response to the second match / mismatch determination circuit making a mismatch determination, the second match / mismatch determination circuit determines the match continuously for a second predetermined number of bits. And a third detecting means for detecting that the received signal has not been detected, and is configured to recognize that a slip has occurred in the received signal based on the detection results of the first, second, and third detecting means. .

Therefore, the occurrence of the bit slip can be accurately recognized without being affected by the length of the bit slip and the frequency of occurrence of the bit error.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a state transition diagram of one embodiment.

FIG. 3 is a diagram illustrating an operation of the embodiment;

FIG. 4 is a timing chart for explaining the operation of the embodiment;

FIG. 5 is a timing chart for explaining the operation of the embodiment;

FIG. 6 is an explanatory diagram of a bit error and a bit slip.

[Explanation of symbols]

 REFERENCE SIGNS LIST 20 first pseudo random signal generation circuit 21 first shift register 22 EXOR circuit 23 first match / mismatch determination circuit 24 second pseudo random signal generation circuit 25 second shift register 26 EXOR circuit 27 switch 28 second Match / mismatch determination circuit 30 Slip determination section 31 First counter 32 Second counter 33 Determination circuit 34 First flip-flop 35 AND circuit 36 Second flip-flop

Claims (1)

(57) [Claims] A first shift register having a first shift register for inputting a received signal and an exclusive OR circuit for obtaining an exclusive OR of a plurality of outputs of the first shift register. And a first match / mismatch determination circuit (23) that determines match / mismatch between a signal output from the first pseudo-random signal generation circuit and a received signal on a bit-by-bit basis. A second shift register (25) having the same number of stages as the first shift register, an exclusive OR circuit (26) for taking an exclusive OR of a plurality of outputs of the second shift register,
A switch (27) for switching between the output of the exclusive OR circuit and a received signal and inputting the received signal to the second shift register, and performs a synchronization pull-in operation when the second shift register inputs a received signal. A second pseudo-random signal generating circuit (24) for generating a pseudo-random signal when inputting the output of the exclusive-OR circuit after the synchronization is determined; and outputting from the second pseudo-random signal generating circuit. An error detection device including a second match / mismatch determination circuit (28) for determining match / mismatch between a signal and a received signal on a bit-by-bit basis, in response to the second match / mismatch determination circuit determining that there is a mismatch. First detecting means (31, 34, 35) for detecting that the first match / mismatch determination circuit has made a match determination for a first predetermined number of bits (N) continuously; The second detecting means (2) detects that the second match / mismatch determination circuit has continuously made the match determination by the second predetermined number of bits (M) in response to the match / mismatch determination circuit of No. 2 32) responsive to the second match / mismatch determination circuit making a mismatch determination, detecting that the match determination by the second match / mismatch determination circuit has not continued for the second predetermined number of bits. An error detection device comprising: a third detection unit (32); and certifying that a slip has occurred in a received signal based on detection results of the first, second, and third detection units.