JP3115756B2 - Demultiplexer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention detects a start signal included in input serial data in a binary mode and converts the serial data into parallel data starting from the start signal. In particular, the present invention relates to a demultiplexer circuit capable of realizing a high bit rate operation.

2. Description of the Related Art In a computer system, a demultiplexer circuit which detects a start signal included in input serial data in a binary mode and converts the serial data into parallel data using the start signal as a starting point is used. Can be A demultiplexer circuit having such a function needs to be able to operate at a high bit rate in order to improve the processing speed of a computer system.

[0003]

2. Description of the Related Art A demultiplexer circuit has, for example, "0".
When serial data in the binary mode such as "10011001110101..." Is input, a start signal "01100111" of, for example, 8 bits included in the serial data is detected.
Starting from this start signal, as shown in FIG.
This is a process for converting serial data into parallel data by cutting it out, for example, every 8 bits.

FIG. 13 shows a circuit configuration of a conventional demultiplexer circuit. As shown in FIG. 1, in the conventional demultiplexer circuit, an n-bit shift register circuit 1 that shifts and latches input serial data in synchronization with a clock, and data latched by the shift register circuit 1 A comparator circuit 2 for detecting whether or not the signal is displaying a start signal, and a clock frequency dividing circuit 3 for dividing the frequency of the clock to "1 / n" when the comparator circuit 2 detects the display of the start signal. And a latch circuit 4 for reading and latching data latched by the shift register circuit 1 in parallel using a clock output from the clock frequency dividing circuit 3 as a synchronization signal.

[0005] According to this configuration, the conventional demultiplexer circuit, when serial data shifting through the shift register circuit 1 matches the start signal, then decrements by 1 /.
The serial data is converted to n using the clock divided by n.
Processing is performed so as to convert the data into parallel data by cutting out each bit.

[0006]

However, according to such a conventional technique, when the clock frequency exceeds a prescribed value, the comparator circuit 2 detects the start signal and the clock frequency dividing circuit 3 starts the frequency dividing. Between,
There is a problem that the serial data of the next bit is latched in the shift register circuit 1 and the latch circuit 4 latches the latched serial data.

That is, according to the conventional demultiplexer circuit, when the clock frequency is increased, the delimiter of the bit string is shifted, so that there is a problem that accurate parallel data cannot be cut out.

The present invention has been made in view of such circumstances, and detects a start signal contained in input serial data in a binary mode, and uses the start signal as a starting point to convert the serial data into parallel data. It is an object of the present invention to provide a new demultiplexer circuit capable of realizing a high bit rate operation when adopting a configuration for converting data.

[0009]

1 (a) and 1 (b) show the principle configuration of the present invention. In the figure, reference numeral 10 denotes a demultiplexer circuit provided with the present invention, which detects a start signal included in serial data in an input binary mode and converts the serial data into parallel data based on the start signal. Is processed so as to be converted.

The demultiplexer circuit 1 shown in FIG.
0 indicates a shift register circuit 11 that shifts and latches input serial data in synchronization with a clock in order to realize the demultiplexer function, and latches and latches the latch data of the shift register circuit 11 in parallel. A latch circuit 12, a detection circuit 13 for detecting whether the latch data of the shift register circuit 11 indicates a start signal, and a control circuit 14 for supplying a sampling signal for instructing the latch circuit 12 to perform a latch process. , Shift register circuit 11 and latch circuit 12
And a delay circuit 15 for delaying the data taken into the latch circuit 12.

In addition to this configuration, in order to prevent a malfunction, when the detection circuit 13 detects the start signal display, a stop circuit 16 for forcibly stopping the detection function of the subsequent detection circuit 13 may be provided. is there.

When employing this configuration, the number of shift stages of the shift register circuit 11 is configured to be larger than the number of latch stages of the latch circuit 12 in order to increase the detection accuracy of the start signal by the detection circuit 13. Or
The shift register circuit 11 may include a plurality of shift register circuit units each having the same number of shift stages as the number of latch stages of the latch circuit 12.

This configuration (shift register circuit 1)
When the shift register circuit 11 employs a clock obtained by dividing the original clock by "1/2", the shift register circuit 11 , An even-numbered shift register circuit and an odd-numbered shift register circuit. Among these, the even-numbered shift register circuit shifts and latches the even-numbered serial data while the odd-numbered shift register circuit includes the odd-numbered shift register circuit. , May be configured to shift and latch the odd-numbered serial data.

The demultiplexer circuit 10 shown in FIG. 1B is a first shift register which shifts and latches input serial data in synchronization with a clock in order to realize the demultiplexer function. A circuit 20, a data delay circuit 21 for delaying the input serial data, a second shift register circuit 22 for shifting and latching the serial data delayed by the data delay circuit 21 in synchronization with a clock, and a second shift register circuit 22. A latch circuit 23 for fetching and latching the latch data of the shift register circuit 22 in parallel, a detection circuit 24 for detecting whether the latch data of the first shift register circuit 20 indicates a start signal, and a latch circuit. And a control circuit 25 for supplying a sampling signal for instructing a latch process to That.

In addition to this configuration, the clock used by the second shift register circuit 22 is delayed by a data delay in order to absorb a change in clock frequency and a change in the amount of delay time of the data delay circuit 21 due to an environmental change. In order to provide a clock delay circuit 26 for delaying the same delay time as the circuit 21 or to prevent malfunction, when the detection circuit 24 detects the start signal display, the detection function of the subsequent detection circuit 24 is forcibly stopped. There is a case where a stop circuit 27 is provided.

When adopting this configuration, the number of shift stages of the first shift register circuit 20 is increased in order to increase the detection accuracy of the start signal by the detection circuit 24. Or the first shift register circuit 20
However, in some cases, a plurality of shift register circuit units having the same number of shift stages as the number of shift stages of the second shift register circuit 22 may be used.

At the time of adopting this configuration (including the case where the first shift register circuit 20 adopts the above-described configuration), it operates with a clock obtained by dividing the original clock by "1/2". The first shift register circuit 20 is composed of two types, an even number shift register circuit and an odd number shift register circuit, and the second shift register circuit 22 is provided with an even number shift register circuit. Odd-numbered shift register circuits are composed of two types. These even-numbered shift register circuits shift and latch even-numbered serial data, while these odd-numbered shift register circuits store odd-numbered serial data. It may be configured to latch while shifting.

[0018]

In the demultiplexer circuit 10 according to the present invention, whose principle configuration is shown in FIG. 1A, an n-bit shift register circuit 11 latches while shifting input serial data in synchronization with a clock. When doing
When the detection circuit 13 detects that the latch data of the shift register circuit 11 indicates the start signal, the control circuit 14 generates a sampling signal by dividing the frequency of the clock to “1 / n”. , Latch circuit 12
Fetches the latch data of the shift register circuit 11 in parallel in synchronization with the generated sampling signal, thereby cutting out the serial data every n bits starting from the start signal.

When performing the conversion processing to the parallel data, the shift register circuit 11 and the latch circuit 1
2. Delay circuit 15 provided corresponding to n signal lines between
Detects the data taken into the latch circuit 12 by the detection circuit 1
3 / Delay by a delay time amount corresponding to the signal processing time in the control circuit 14.

Since the clock frequency is increased in accordance with the delay operation of the delay circuit 15, the serial data of the next bit may be latched in the shift register circuit 11 before the control circuit 14 sends out the sampling signal. Even if there is, the latch circuit 12 can cut out the original bit string starting from the start signal from the serial data.

Further, in the demultiplexer circuit 10 of the present invention whose principle configuration is shown in FIG. 1B, the first shift register circuit 20 having an n-bit configuration synchronizes input serial data with a clock. When the detection circuit 24 detects that the latch data of the first shift register circuit 20 indicates the start signal during the latch while shifting, the control circuit 25 sets the clock frequency to “1/1”. The sampling signal is generated by dividing the frequency to n ″.

On the other hand, the data delay circuit 21 delays the input serial data by a delay time equivalent to the signal processing time in the detection circuit 24 / control circuit 25, and receives the delay operation to receive the second data. The shift register circuit 22 shifts and latches serial data delayed by the data delay circuit 21 in synchronization with a clock. At this time, when the clock delay circuit 26 is provided, the second shift register circuit 22 performs the latch operation using the clock delayed by the clock delay circuit 26.

The latch circuit 23 includes a control circuit 25
By latching the latch data of the second shift register circuit 22 in parallel in synchronization with the sampling signal generated by the above, serial data is cut out every n bits starting from the start signal.

In accordance with this operation, when the clock frequency is increased, the serial data of the next bit may be latched in the first shift register circuit 20 before the control circuit 25 sends out the sampling signal. Also, since the serial data before the next bit is latched is latched in the second shift register circuit 22, the latch circuit 12 can cut out the original bit string starting from the start signal from the serial data. become able to.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to embodiments. FIG. 2 illustrates an embodiment of the demultiplexer circuit 10 whose principle configuration is illustrated in FIG.

In this embodiment, it is assumed that serial data is converted into parallel data by dividing the serial data into 8-bit units, and is the same as that described with reference to FIG. Are indicated by the same symbols. In this embodiment, the stop circuit 16 is not provided.

The shift register circuit 11 of this embodiment is
A serial connection of nine flip-flops, the first of which is a serial data input stage, is provided with nine buffers for each of the outputs of the second to ninth eight flip-flops. Is connected.

The latch circuit 12 is composed of eight flip-flops to which the output signal of the delay circuit 15 is input, and each of these flip-flops corresponds to a case where a latch instruction signal is input to a clock terminal. Delay circuit 15
Is latched.

The detection circuit 13 is composed of eight EOR circuits and a NOR circuit for calculating the logical OR of the output signals of these EOR circuits.
To each of the R circuits, the output signals of the first to eighth flip-flops of the shift register circuit 11 are input and a start signal (eg, “01100111”) of 8 bits included in the serial data is included. Si) is input as a comparison reference value.

Further, the control circuit 14 is configured by a serial connection of three toggle flip-flops exhibiting a "1/2" frequency dividing function, thereby exhibiting a "1/8" frequency dividing function. The clock is supplied as an input signal, and the output signal is supplied to the latch circuit 12 as a latch instruction signal. An output signal of the NOR circuit of the detection circuit 13 is input to a reset terminal of each toggle flip-flop of the control circuit 14.

In the demultiplexer circuit 10 of the embodiment shown in FIG. 2, the nine flip-flops constituting the shift register circuit 11 shift the input serial data in synchronization with the clock. Latch. At this time, for example, “011” is assigned to the first to eighth eight flip-flops.
When the start signal “00111” is latched, all the EOR circuits constituting the detection circuit 13 output a low level. In response to the output result, the NOR circuit constituting the detection circuit 13 receives the start signal. Outputs a high level to indicate what has been done.

In response to the high level output of the detection circuit 13, all the toggle flip-flops constituting the control circuit 14 are reset, whereby the control circuit 14
Starting from the time when the output of the detection circuit 13 returns to the low level by the next clock, the clock is again set to “８”.
, A regular latch instruction signal is generated. That is, a latch instruction signal is supplied to the latch circuit 12 every time eight clocks are counted.

In response to the latch instruction signal, the flip-flops constituting latch circuit 12 take in parallel the output signals of the second through ninth flip-flops of shift register circuit 11 delayed by delay circuit 15. Then, the serial data is cut out every eight bits starting from the start signal, and the circuit mechanism connected to the subsequent stage of the demultiplexer circuit 10 receives the high level output of the detection circuit 13 and cuts out the data. Import parallel data as having the correct meaning.

Thus, in the embodiment shown in FIG.
The increase in the clock frequency may cause the second to ninth flip-flops of the shift register circuit 11 to latch the next bit of serial data before the control circuit 14 sends out the latch instruction signal. Even if there is, the latch circuit 12 can cut out the original bit sequence starting from the start signal from the serial data.

In the embodiment shown in FIG. 2, the shift register circuit 11 is disclosed as being composed of nine flip-flops. However, it can be basically composed of eight flip-flops. Oh, one flip-flop
The extra is simply provided to perform detection one clock earlier.

FIGS. 3, 4 and 5 show modifications of the embodiment of FIG. In the embodiment shown in FIG. 3, the shift register circuit 11 is an 8-bit shift register circuit 1.
This embodiment differs from the embodiment shown in FIG. 2 in that it employs a configuration including three components 1a, 1b and 1c and a configuration in which the latch data of the shift register circuit 11a is connected to the latch circuit 12.

According to this configuration, in the embodiment of FIG.
When the start signal specified by the bit is latched by the shift register circuits 11a, 11b, 11c, conversion processing from serial data to parallel data is performed, so that the detection accuracy of the start signal can be improved. Become.

On the other hand, in the embodiment shown in FIG. 4, a frequency dividing circuit 17 for dividing the clock by "1/2" is provided, and the control circuit 14 uses the frequency-divided clock output from the frequency dividing circuit 17. At the same time, the shift register circuit 11 is composed of two 4-bit shift register circuits 11D and 11d, and one of the shift register circuits 11D uses this frequency-divided clock to generate the odd bit number data of the serial data. The shift processing is executed and the other shift register circuit 11d
However, this embodiment differs from the embodiment of FIG. 2 in that a configuration is employed in which the even bit number data of the serial data is shifted using the inverted value of the divided clock. Here, this frequency-divided clock can also be given from outside.

According to this configuration, in the embodiment of FIG.
Since the operation can be performed using the clock divided to "/ 2", normal operation can be performed even when a high-frequency clock is used.

On the other hand, in the embodiment shown in FIG. 5, a frequency dividing circuit 17 for dividing the clock by "1/2" is provided, and the control circuit 14 uses the frequency-divided clock output from the frequency dividing circuit 17. At the same time, the shift register circuit 11 is replaced with a 4-bit shift register circuit 11E, F, G, e, f,
And one shift register circuit 11E, F,
G shifts the odd bit number data of the serial data using the divided clock, and the other shift register circuits 11e, f, and g use the inverted value of the divided clock to perform serial processing. It differs from the embodiment of FIG. 2 in that a configuration is adopted in which the shift processing of the even bit number data of the data is executed and the latch data of the shift register circuits 11E and e is connected to the latch circuit 12. . Here, this frequency-divided clock can also be given from outside.

According to this configuration, in the embodiment of FIG.
When the start signal defined by the bit is latched by the shift register circuits 11E, F, G, e, f, and g, the conversion processing from serial data to parallel data is performed, so that the detection accuracy of the start signal is improved. As a result, the operation can be performed using a clock divided by "1/2", so that the device can operate normally even when a high-frequency clock is used.

Next, an embodiment of the demultiplexer circuit 10 whose principle configuration is shown in FIG. 1B will be described. FIG. 6 shows an embodiment of the demultiplexer circuit 10 whose principle configuration is shown in FIG. 1B.

In this embodiment, it is assumed that serial data is converted into parallel data by dividing the data into 8-bit units. In the drawing, the same as that described with reference to FIG. Are indicated by the same symbols.

First shift register circuit 2 of this embodiment
0 is a serial connection of eight flip-flops whose first stage is a serial data input stage. Also,
The data delay circuit 21 is configured by serial connection of nine buffers. Further, the second shift register circuit 22
Is composed of a serial connection of nine flip-flops, the first of which is connected to the data delay circuit 21.

The latch circuit 23 is composed of eight flip-flops to which the output signals of the second to ninth flip-flops of the second shift register circuit 22 are input. When the latch instruction signal is input to the clock terminal, the latch data of the flip-flop of the corresponding second shift register 22 is latched.

The detection circuit 24 is composed of eight EOR circuits and a NOR circuit for calculating the logical OR of the output signals of these EOR circuits.
To each of the R circuits, an output signal of the flip-flop of the first shift register circuit 20 is input, and an 8-bit “011001” included in the serial data is included.
A start signal (Si) “11” is input as a comparison reference value.

Further, the control circuit 25 has a serial connection of three toggle flip-flops exhibiting a "1/2" frequency dividing function, thereby exhibiting a "1/8" frequency dividing function. The clock is supplied as an input signal, and the output signal is supplied to the latch circuit 23 as a latch instruction signal. The output signal of the NOR circuit of the detection circuit 24 is input to the reset terminal of each toggle flip-flop of the control circuit 25.

The clock delay circuit 26 is composed of a serial connection of nine buffers. Stop circuit 2
Reference numeral 7 denotes a flip-flop which inputs an inverted output value of the NOR circuit of the detection circuit 24 to the clock terminal, inputs a high level to the D terminal, and supplies an output signal of the Q terminal to an input of the NOR circuit of the detection circuit 24. You. Here, the stop circuit 27 supplies a low-level output signal to the input of the NOR circuit of the detection circuit 24 as an initial state.

In the demultiplexer circuit 10 of the embodiment of FIG. 6 configured as described above, the eight flip-flops constituting the first shift register circuit 20 synchronize input serial data with a clock. Latch while shifting. At this time, when a start signal, for example, “01100111” is latched for these flip-flops, all the EOR circuits constituting the detection circuit 24 output a low level. The NOR circuit constituting 24 outputs a high level to indicate that a start signal has been input.

In response to the high level output of the detection circuit 24, all the toggle flip-flops constituting the control circuit 25 are reset, whereby the control circuit 25
Starting from the time when the output of the detection circuit 24 returns to the low level by the next clock, the clock is again set to “８”.
, A regular latch instruction signal is generated. That is, each time eight clocks are counted, the latch instruction signal is supplied to the latch circuit 23.

In response to the high-level output of the detection circuit 24, the flip-flop constituting the stop circuit 27 turns the high-level output to a low level, that is, at the time when the next clock is input. , D terminal is latched, and N of the detection circuit 24 is latched.
By giving the signal to the input of the OR circuit, the detection circuit 24 is controlled so as not to output a high level again.

On the other hand, the data delay circuit 21 delays the input serial data, and the clock delay circuit 26 delays the clock. In response to this delay operation, the nine flip-flops constituting the second shift register circuit 22 shift the serial data delayed by the data delay circuit 21 in synchronization with the clock delayed by the clock delay circuit 26. While latching.

When the flip-flop constituting the latch circuit 23 receives the latch instruction signal from the control circuit 25, it outputs the output signals of the second to ninth flip-flops of the second shift register circuit 22 in parallel. The serial data is cut out every eight bits starting from the start signal, and the circuit mechanism connected to the subsequent stage of the demultiplexer circuit 10 receives the high-level output of the detection circuit 24, The extracted parallel data is taken in as having the correct meaning.

Thus, in the embodiment shown in FIG.
By increasing the clock frequency, even if the next bit of serial data may be latched in the flip-flop of the first shift register circuit 20 before the control circuit 25 sends out the latch instruction signal, Circuit 23
Can extract an original bit string starting from a start signal from serial data.

In the embodiment of FIG. 6, the second shift register circuit 22 is disclosed as being composed of nine flip-flops. However, basically, the second shift register circuit 22 is composed of eight flip-flops. The reason why the extra flip-flop is provided is simply to match the order of the latch instruction signal with the 8-bit data of the latch circuit 23.

FIGS. 7 and 8 show timing charts of the embodiment of FIG. 6 described above. Here, in FIG. 7, represents the output of the first flip-flop of the first shift register circuit 20, and represents the output of the eighth flip-flop of the first shift register circuit 20, and so on. 2 shows the output of the flip-flop of the first shift register 20. 8 shows the output of the first flip-flop of the second shift register circuit 22, and FIG.
The output of the flip-flop of the second shift register 22 is indicated, such as the output of the second ninth flip-flop.

FIGS. 9, 10 and 11 show modifications of the embodiment of FIG. In the embodiment shown in FIG.
6 is different from the embodiment of FIG. 6 in that the shift register circuit 20 is composed of three 8-bit shift register circuits 20a, 20b and 20c.

According to this configuration, in the embodiment of FIG.
When the start signal specified by the bit is latched by the shift register circuits 20a, 20b, 20c, conversion processing from serial data to parallel data is performed, so that the detection accuracy of the start signal can be improved. Become.

On the other hand, in the embodiment shown in FIG. 10, a frequency dividing circuit 28 for dividing the clock into "1/2" is provided, and the control circuit 25 uses the frequency-divided clock output from the frequency dividing circuit 28. In addition, the first shift register circuit 20 is composed of two 4-bit shift register circuits 20D and 20d, and the second shift register circuit 22 is composed of two 4-bit shift register circuits 22D and 22d. Then, one shift register circuit 20D / 22D executes a shift process of the odd-numbered bit number data of the serial data by using the divided clock, and
0d / 22d uses the inverted value of the divided clock to
This embodiment differs from the embodiment shown in FIG. 6 in that a configuration for shifting the even bit number data of the serial data is employed. Here, this frequency-divided clock can also be given from outside.

According to this configuration, in the embodiment of FIG.
Since operation can be performed using a clock divided by "1/2", normal operation can be performed even when a high-frequency clock is used.

On the other hand, in the embodiment shown in FIG. 11, a frequency dividing circuit 28 for dividing the clock by "1/2" is provided, and the control circuit 25 uses the frequency-divided clock output from the frequency dividing circuit 28. At the same time, the first shift register circuit 20 is replaced with a 4-bit shift register circuit 20E, F, G, e,
f, g, the second shift register circuit 22
Is composed of two 4-bit shift register circuits 22E and 22e, and one of the shift register circuits 20E, F and G
/ 22E executes a shift process of the odd bit number data of the serial data using the divided clock,
The other shift register circuit 20e, f, g / 22e
This embodiment is different from the embodiment of FIG. 6 in that a configuration is employed in which the even bit number data of the serial data is shifted using the inverted value of the divided clock. Here, this frequency-divided clock can also be given from outside.

According to this configuration, in the embodiment of FIG.
When a start signal defined by 4 bits is latched by the shift register circuits 20E, F, G, e, f, and g,
Since the conversion process from serial data to parallel data is executed, the detection accuracy of the start signal can be improved, and the operation can be performed using the clock divided by "1/2". In addition, normal operation can be performed even when a high-frequency clock is used.

Although the illustrated embodiment has been described, the present invention is not limited to this. For example, the embodiment of FIGS. 3 and 5 discloses a configuration in which the number of bits of the shift register circuit 11 is an integer multiple of the number of bits of the latch circuit 12, and the embodiment of FIGS. Has been disclosed in which the number of bits of the shift register circuit 20 is an integral multiple of the number of bits of the second shift register circuit 22, but the present invention is not limited to the integral multiple.

[0064]

As described above, according to the present invention,
A demultiplexer circuit configured to detect a start signal included in the input serial data in the binarization mode and convert the serial data into parallel data starting from the start signal. Rate operation can be realized.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is an embodiment of the present invention.

FIG. 3 is a modification of the embodiment of FIG.

FIG. 4 is a modification of the embodiment of FIG. 2;

FIG. 5 is a modification of the embodiment of FIG. 2;

FIG. 6 is another embodiment of the present invention.

FIG. 7 is a timing chart of the embodiment of FIG.

FIG. 8 is a timing chart of the embodiment of FIG.

FIG. 9 is a modification of the embodiment of FIG.

FIG. 10 is a modification of the embodiment of FIG.

FIG. 11 is a modification of the embodiment of FIG.

FIG. 12 is an explanatory diagram of processing of a demultiplexer circuit.

FIG. 13 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 Reference Signs List 10 Demultiplexer circuit 11 Shift register circuit 12 Latch circuit 13 Detection circuit 14 Control circuit 15 Delay circuit 16 Stop circuit 20 First shift register circuit 21 Data delay circuit 22 Second shift register circuit 23 Latch circuit 24 Detection circuit 25 Control circuit 26 Clock delay circuit 27 Stop circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-57-190420 (JP, A) JP-A-59-83243 (JP, A) JP-A-60-186123 (JP, A) JP-A 61-190 80918 (JP, A) JP-A-5-331571 (JP, A) JP-A-3-139020 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 9/00

Claims (10)

(57) [Claims] 1. A demultiplexer circuit configured to detect a start signal included in input binary mode serial data and convert the serial data into parallel data starting from the start signal. A shift register circuit (11) for latching while shifting the serial data in synchronization with a clock; and a latch circuit (12) for latching the latch data of the shift register circuit (11) in parallel according to a sampling signal. ), A detection circuit (13) for detecting whether the latch data of the shift register circuit (11) indicates a start signal, and a clock when the detection circuit (13) detects the start signal display. The control circuit (14) that generates the sampling signal by dividing the frequency and supplies the sampling signal to the latch circuit (12).
And a delay circuit (15) provided corresponding to a signal line between the shift register circuit (11) and the latch circuit (12) and delaying data taken in the latch circuit (12). A demultiplexer circuit. 2. The demultiplexer circuit according to claim 1, wherein the number of shift stages of the shift register circuit is equal to that of the latch circuit.
A demultiplexer circuit characterized in that the number of latch stages is larger than the number of latch stages in 2). 3. The demultiplexer circuit according to claim 1, wherein the shift register circuit (11) comprises a plurality of shift register circuit units having the same number of shift stages as the number of latch stages of the latch circuit (12). Characteristic demultiplexer circuit. 4. The demultiplexer circuit according to claim 1, wherein the shift register circuit (11) is composed of two types of an even-number shift register circuit and an odd-number shift register circuit. A shifter for shifting even-numbered serial data and latching the odd-numbered shift register while shifting odd-numbered serial data. 5. A demultiplexer circuit configured to detect a start signal included in input serial data in a binary mode and convert the serial data into parallel data starting from the start signal. A first shift register circuit (20) for latching the serial data while shifting it in synchronization with a clock; a data delay circuit (21) for delaying the serial data; and a data delay circuit (21). A second shift register circuit (22) that shifts and latches the delayed serial data in synchronization with a clock, and latches and latches the latch data of the second shift register circuit (22) in parallel according to a sampling signal. It is checked whether the latch data of the latch circuit (23) and the first shift register circuit (20) indicate a start signal. Output detection circuit (2
4) and a control circuit (25) that generates the sampling signal by dividing the clock and supplies it to the latch circuit (23) when the detection circuit (24) detects the start signal display. A demultiplexer circuit comprising: 6. The demultiplexer circuit according to claim 5, further comprising a clock delay circuit (26) for delaying a clock used by the second shift register circuit (22) by the same delay time as the data delay circuit (21). A demultiplexer circuit. 7. The demultiplexer circuit according to claim 5, wherein the number of shift stages of the first shift register circuit (20) is larger than the number of shift stages of the second shift register circuit (22). A demultiplexer circuit. 8. The demultiplexer circuit according to claim 5, wherein the first shift register circuit (20) has the same number of shift stages as the number of shift stages of the second shift register circuit (22). A demultiplexer circuit characterized by comprising a plurality of. 9. The demultiplexer circuit according to claim 5, wherein the first shift register circuit (20) is composed of two types: an even-number shift register circuit and an odd-number shift register circuit. The second shift register circuit (22) is composed of two types, an even-number shift register circuit and an odd-number shift register circuit.
A demultiplexer circuit characterized in that even-numbered serial data is shifted and latched, while these odd-numbered shift register circuits are configured to shift and latch odd-numbered serial data. 10. The method of claim 1, 2, 3, 4, 5, 6, 7,
10. The demultiplexer circuit according to 8 or 9, wherein the detection circuit (13, 24) forcibly stops the detection function of the detection circuit (13, 24) after detecting the start signal display. A demultiplexer circuit comprising: