JP3538163B2 - Asynchronous pulse signal capture circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse signal capturing circuit, and more particularly to an asynchronous pulse signal capturing circuit that captures a pulse signal input at an arbitrary timing in synchronization with a predetermined operation clock.

[0002]

2. Description of the Related Art Conventionally, when the pulse width of an asynchronous input pulse signal is narrower than the operation clock cycle of the fetch side, it is necessary to fetch the signal after shaping it into a pulse width that can be sampled by the operation clock. That is, the capture circuit for the pulse signal having a small width input at an arbitrary timing sets the FLAG when detecting the rising edge, and sets the rising FL signal.
The FLAG is cleared when the AG is synchronized with the operation clock (Japanese Patent Laid-Open No. 2000-27825).
No. 2).

Hereinafter, the configuration and operation of a conventional asynchronous pulse signal capturing circuit will be described with reference to FIGS. FIG. 6 is a diagram showing a configuration of a conventional asynchronous pulse signal capturing circuit. Capture FL that captures a pulse signal input at an arbitrary timing at the input timing
It is composed of an AG unit A and a signal synchronization unit B that performs an operation of taking in an input signal only at the time of a rise of a predetermined operation clock or the like.

FIG. 7 is a diagram showing an operation time chart of the circuit of FIG. In FIG. 7, the operation clock is a clock signal of the signal synchronization unit B. Also, the asynchronous pulse is
An example is shown in which the pulse is input as a pulse whose time width is shorter than the period or pulse width of the operation clock of the signal synchronization unit B. The circuit operation is as follows.

[0005] The capture FLAG unit A captures and holds the signal at the leading edge of the asynchronous pulse (sets it high).
The signal is output to the signal synchronization unit B. The signal synchronization unit B captures the output (high level) of the capture FLAG unit A at the rising timing of the operation clock and outputs (high level) and outputs a part of the output as a FLAG clear signal C. To clear the FLAG unit A (set the output of the FLAG unit A to low level).

Since the output of the FLAG unit A is cleared (set to a low level) at the rising timing of the next operation clock, the signal synchronization unit B also changes the synchronization output to the state before the input of the asynchronous pulse. Return (go low).

The asynchronous pulse input by the above operation is shaped into a synchronous pulse having a pulse width between the rising timings of two operation clocks (clock cycle) by the signal synchronizer B, and is output as a synchronous signal. .

[0008]

In the conventional asynchronous pulse signal capturing circuit, the FLAG unit A captures and holds the asynchronous pulse, and outputs the FLA output from the signal synchronizing unit B at the subsequent rising edge of the operation clock.
It has a feedback loop configuration that is cleared by the G clear signal, and an interface for feedback is indispensable.

The asynchronous pulse signal capturing circuit having such a feedback configuration cannot operate even if an asynchronous pulse is input again until the circuit is cleared to an initial state by feedback. In other words, the section from the time when the capture FLAG rises to the point where the synchronization output becomes the value before the input of the asynchronous pulse is an unrecognizable section even if the next asynchronous pulse is input, and the section for the input of the high-speed asynchronous pulse is The problem is that it is not possible to generate a synchronized output.

(Object) It is an object of the present invention to provide an asynchronous pulse signal capturing circuit capable of capturing an asynchronous pulse by an operation clock without forming a feedback loop.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an asynchronous pulse signal taking-in circuit capable of reliably outputting a synchronous pulse even to an adjacent asynchronous pulse.

[0012]

The present invention is characterized in that a pulse is taken as an event and is taken in by an operation clock without performing processing such as waveform shaping using a feedback circuit.

According to the present invention, an asynchronous pulse signal to be input is detected , and a plurality of states are determined according to the number of the pulse signals.
A pulse detector that holds one of the states, the state held by the pulse detector is captured by an operation clock and held as a current value, and the state captured by the operation clock immediately before the operation clock is defined as a past value. A state holding unit including at least two holding means for holding,
A state comparison / change detection unit that inputs and compares a current value and a past value of the state holding unit and outputs a difference between the current value and the past value.

Further, the pulse detector has a plurality of state holding functions for holding the number of input pulses as the state. Further, the pulse detection unit includes:
It is a register unit for detecting a pulse signal to be input by a clock having a different repetition frequency higher than the operation clock, and in particular, a register unit for inputting a signal including a bus clock and a write enable signal from the digital processing device.

Further, the state comparison / change detection section outputs three or more multi-valued or multi-level signals as the output difference.

(Operation) The detection state of the asynchronous pulse is sequentially held as the past state and the present state by the operation clock, and the two are compared to be output as a synchronous pulse. The occurrence of a non-recognizable period is avoided by increasing the number of states for detecting and holding asynchronous pulses.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of an asynchronous pulse signal capturing circuit according to the present invention will be described in detail with reference to the drawings.

(Explanation of Configuration) FIG. 1 is a diagram showing a configuration example of the present embodiment. In the present embodiment, the pulse detector 1
, A state holding unit 2 and a state comparison / change detection unit 3.

The pulse detector 1 inputs a pulse signal (also referred to as an "asynchronous signal") arriving at an arbitrary time asynchronously with an operation clock of a subsequent circuit for capturing the pulse signal, and detects a change point of the asynchronous signal. It has a state holding circuit that captures (detects an edge or the like) and holds it. Further, the timing of the state signal held in the pulse detection unit 1 is asynchronous with the operation clock similarly to the input.

In particular, the state holding circuit of the pulse detecting section 1 can be a circuit capable of holding a plurality of states, for example, a counter circuit. It can be configured to have a function of holding a plurality of states corresponding to the states.

The state holding unit 2 includes a synchronization unit 21, a current value holding unit 22, and a past value holding unit 23. Each of the circuit units has a clock input terminal, and receives an input signal. An operation clock to be synchronized is supplied.

The synchronization section 21 captures the state detected and held by the pulse detection section 1 at the rising timing of the operation clock, and the current value holding section 22 and the past value holding section 23
Output means. The current value holding unit 22 is a unit for holding a current state value (current value), and the past value holding unit 23 is a unit for holding a state (past value) one operation clock before. Current value holding unit 21 and past value holding unit 2
2 also operates with the operation clock.

The synchronization section 21 captures the state detected and held by the pulse detection section 1 based on the operation clock at the rising timing of the operation clock, and holds the state in the current value holding section 22. At this time, the state immediately before being held in the current value holding unit 22 is moved to and held in the past value holding unit 23.

That is, the current value holding unit 22 of the state holding unit 2
The past value holding unit 23 inputs the state from the pulse detection unit 1 as a state signal synchronized with the operation clock by the synchronization unit 21, and holds the state signal in the current value holding unit 22 at the rising timing of the operation clock. The state held immediately before in the current value holding unit 22 is the past value holding unit 23.
, The value of each holding state is constantly updated, and both the state at the current time and the state at the past time (one operation clock before) are output to the state comparison / change detection unit 3.

The state comparison / change detection unit 3 receives an operation clock, compares the respective states (past value and current value) held in the current value holding unit 22 and the past value holding unit 23 with each other, and It has a function of detecting a change in state and outputting a signal corresponding to the event that has occurred at the rising timing of the operation clock. In other words, outputs corresponding to the coincidence, non-coincidence, and the difference between the states held in the current value holding unit 22 and the past value holding unit 23 are output as synchronization signals at the timing of the operation clock. If no mismatch is detected as a result of the comparison, a signal indicating a normal state is output,
If a mismatch is detected, it is determined that there is a change in the state, and the change state is output as a detection signal of the occurrence of the event.

(Description of Operation) Next, the operation of the embodiment shown in FIG. 1 will be described with reference to a signal timing chart. FIG. 2 is a diagram illustrating an example of operation timing according to the present embodiment. In the example shown in the figure, the asynchronous signal is a pulse whose pulse width is sufficiently narrower than the period of the operation clock, and shows an example in which a single pulse signal arrives within the period of the operation clock.

First, as the state of each section of the circuit, the state a of the asynchronous signal is already held, and the current value holding section 21 and the past value holding section 22 hold the current value a and the past value a, respectively. Suppose you have In this state, the state comparison / change detection unit 3 detects the same state based on the current value a and the past value a from the rise of the operation clock, and outputs the normal state.

Next, when an asynchronous signal is input, the pulse detector 1 detects a change point of the asynchronous signal and immediately outputs the state b, and the synchronizer 21 outputs the state b at the subsequent rising timing of the first operation clock. b, and the current value holding unit 21 and the past value holding unit 22 output the state b and the state a, respectively.
And output. As a result, the state comparison / change detection unit 3
Detects a mismatch or a state difference between the state a and the state b and outputs a changed state.

Subsequently, the synchronization unit 21 outputs the state b at the rising timing of the subsequent operation clock, and the current value holding unit 21 and the past value holding unit 22 hold and output the state b and the state b, respectively. As a result, the state comparison / change detection unit 3 detects that the outputs of the current value holding unit 21 and the past value holding unit 22 are the same state in the state b, and outputs the normal state.

FIG. 3 is a diagram showing another example of the operation timing of the present embodiment. In the example shown in FIG.
Is the same as the example shown in FIG. 1, but shows an example in which a plurality of pulse signals arrive within the cycle of the operation clock.

In this example, the pulse detector 1 inputs an asynchronous signal, the state detection circuit detects the first and second two pulses, outputs the state b (a + 1) by the first pulse, and outputs the second state.
The state c (a + 2) is output by the pulse of (1). The synchronizer 21 synchronizes the state c (a + 2) at the rising timing of the operation clock, and the current value holder 22 synchronizes the state c (a + 2).
+2) is held and output, and the past value holding unit 22 holds and outputs the state a.

As a result, the state comparison / change detection unit 3 compares the state a and the state c (a + 2) of the current value holding unit 21 and the past value holding unit 22, and uses the change 2 as, for example, a multi-valued pulse signal. Output. Then, at the next rising timing of the operation clock, the outputs of the current value holding unit 21 and the past value holding unit 22 both become the same state of the state c (a + 2), so that the state comparison / change detection unit 3 returns to the normal state. Is output.

(Other Embodiments) Next, another embodiment of the asynchronous pulse signal capturing circuit according to the present invention will be described with reference to FIGS. FIG. 4 is a block diagram showing another embodiment of the present invention for a signal operating with a high-speed clock that is asynchronous with the operation clock synchronized as an asynchronous signal, and FIG. 5 is a diagram showing the operation timing thereof. It is. In the present embodiment, the digital signal processing device M
It comprises a PU 4, a register section 5, a synchronization circuit section 6, a state holding section 7 for holding current values and past values, and a state comparison / change detection section 8.

The MPU 4 is a digital signal processor of a synchronous bus type, and outputs an address, data and a write enable signal synchronized with a high-speed bus clock from the MPU as shown in FIG. The register unit 5 is an IO accessed by the MPU 4 using the signal, and is a holding circuit that holds a state of a signal from the MPU 4.

In other words, the register section 5 has an MPU which is sufficiently smaller than the period of the operation clock input to the circuits subsequent to the synchronization circuit section 6 and is not necessarily synchronized with the operation clock.
4, the data of the address bus and the data bus and the write enable signal synchronized therewith are held and output, so that the write enable output of the register value of the output of the register unit 5 is higher than the operation clock. This corresponds to the asynchronous signal, and in this respect corresponds to the pulse detection unit 1 shown in FIG.

The synchronization circuit section 6 holds the register value (write enable output) output from the register section 5 at the rising timing of the operation clock to generate a synchronization signal. Synchronization 1 by the same function of holding current value and past value
(Current value) and synchronization 2 (past value). The state comparison / change detection unit 8 compares the two signals of the synchronization 1 and the synchronization 2 to detect a match, a mismatch, and a difference between the signals, and outputs a change state. In the example of FIG. 5, the mismatch of the comparison result is detected only when the signal including the write enable is written to the register unit 5, and the signal for detecting that the register unit has been accessed is generated in synchronization with the operation clock. Is done.

Also in this embodiment, when the repetition cycle of the bus clock is faster and a plurality of pulse (write enable) signals arrive at the register within the cycle of the operation clock on the synchronous circuit side, the register is not used. Has a plurality of state holding functions to hold the number of pulse signals of the counter circuit etc., and makes the register value have a plurality of state information (multi-bit signal)
Is output, and the state comparison and
The detection output of the plurality of pulses can be obtained as a synchronization signal from the change detection unit 8 based on multi-bit (multi-value) difference information.

In the embodiment shown in FIG. 1, it is possible to adopt a configuration in which the pulse detector on the input side has the function of a register unit operated by a high-speed clock similar to the embodiment shown in FIG. In addition, in the embodiment shown in FIG. 1, it is possible to use a multi-bit signal instead of using a multi-level pulse for detecting the plurality of pulses. It goes without saying that in the embodiment, multi-level pulses can be used.

[0039]

According to the present invention, it is possible to reliably capture an asynchronous signal having a width smaller than the operation clock cycle in synchronization with the operation clock.

Further, in the present invention, each circuit for detecting and synchronizing the asynchronous pulse is a separate block, but can be configured without employing a feedback configuration, and the interface between the blocks can be simplified. This has the effect.

In particular, there is a remarkable effect that an asynchronous signal faster than the operation clock can be detected as a synchronous signal.

[0042]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of operation timing according to the first embodiment;

FIG. 3 is a diagram illustrating another example of the operation timing according to the first embodiment;

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a diagram illustrating an example of operation timing according to the second embodiment;

FIG. 6 is a block diagram showing a conventional example.

FIG. 7 is a diagram showing operation timing of a conventional example.

[Explanation of symbols]

1 pulse detector 2,7 State holding unit 21 Synchronization unit 22 Current value holding unit 23 Past value holding unit 3, 8 State comparison / change detection unit 4 Digital signal processing unit (MPU) 5 Register section 6 Synchronous circuit section

Claims (5)

(57) [Claims] 1. An input asynchronous pulse signal is detected.
And, among the plurality of states, according to the number of the pulse signals.
A pulse detector for holding one state, and the pulse detector
While holding the state held by the operation clock and holding as a current value, the state held by the operation clock immediately before the operation clock and holding the state as a past value, and the current value held by the state holding unit, An asynchronous pulse signal capturing circuit, comprising: a state comparison / change detection unit that inputs and compares the past values and outputs a difference between the two. 2. The asynchronous pulse signal capturing circuit according to claim 1, wherein said pulse detector has a plurality of state holding functions for holding the number of input pulses as said state. 3. The asynchronous pulse signal capturing circuit according to claim 1, wherein said pulse detector detects an input pulse signal by using a clock having a different repetition frequency than said operation clock. 4. The asynchronous pulse signal capturing circuit according to claim 3, wherein said pulse detector is a register for inputting a signal including a bus clock and a write enable signal from a digital processing device. 5. The asynchronous pulse signal capturing circuit according to claim 2, wherein the state comparison / change detection unit outputs a multi-level or multi-level signal of three or more as a difference to be output. .