KR950005623B1 - Compressed data decompressing circuit - Google Patents

Abstract

The device reduces delay times according to errors of data when compressed data is restored. It comprises: (i) an image extender (2) which restores comprssed image data and synchronous signals (Vsync3) to original image data; (ii) a counter (10) which counts digital image data from the image extender (2) and generates synchronous signal (Vsync4); (iii) an error detector (11) which resets the image extender (2) if an error is detected.

Description

Compressed Data Restoration Circuit

1 is a block diagram of an image compression and reconstruction circuit.

2 is a timing diagram of a synchronization signal associated with an image compression circuit and an image expansion circuit.

3 is a relationship diagram between a synchronization signal and data.

4 is a conventional data restoration circuit for resetting an image expansion circuit.

5 is a block diagram of a compressed data recovery circuit of the present invention.

6 is a detailed circuit diagram of the error detection unit in FIG.

7 is a view of each sub waveform of FIG.

* Explanation of symbols for main parts of the drawings

1: Image Compressor 2: Image Extender

3: end of image detection block 10: counter

11: error detection unit 11-1, 11-2: timer

The present invention relates to the control of an image compression system, and more particularly, to a compressed data recovery circuit adapted to shorten the processing delay time of a system due to an error of data when recovering compressed data.

In general, if the compressed data is broken in the process of compressing and transmitting digital image data in the image compression system and receiving the compressed data and restoring it back to the original data, it is difficult to restore the original image from the data, The generated error will propagate to the next data.

The moving picture compression system prevents such error propagation and has a structure in which the compressed data is synchronized with the original picture data in picture units for real time processing.

In the image compression system, the data is input to the image compression unit 1 together with the synchronization signal V _sync1 and compressed as shown in FIG. 1, and the compressed data is further _expanded along with the synchronization signal V _sync3 . Inputted to the unit 2, the original digital image data is restored.

At this time, the synchronization signals V _sync1 and V _sync3 have a predetermined delay time until they appear in the output terminal after a predetermined process in the image compression unit 1 and the image extension unit 2, as shown in FIG. Has

The operation and problems of the conventional image data compression and decompression techniques will be described in detail as follows.

Conventional technology detects an error generated in an image by recognizing that it is the last data of a field of image data by inserting an end of image signal into the compressed data to distinguish a field of compressed data as shown in FIG. It has a structure that can be limited to one field.

In order to reset the image stretcher 2 at the end of each field, a block 3 for receiving compressed image data as shown in FIG. 4 and detecting an end-of-image is required. Each time an image occurs, a reset signal is applied to the image extending unit 2.

In this case, when an end of image is detected during the flow of compressed data, the image extension unit 2 resets the component circuit so that an error that may have occurred in the previous data is no longer propagated to the next data. By doing so, the synchronization signal and the data are kept synchronized.

Here, it can be seen that the synchronization signals V _sync1 to V _sync4 of FIG. 2 and FIG. 3 are all synchronized, and the processing of the error propagation and moving picture is completed by terminating the processing in synchronization units using an end of image. Implement processing.

However, as described above, the conventional method synchronizes synchronization with data using an end of image code. In this case, the image extension unit 2 requires a process of resetting each field. do.

Therefore, since the image decompression unit 2 is reset for each field, the RAM or first-in first-out memory used in the image processing process consumes a lot of time for reset or initialization, and thus a lot of time delay occurs.

Accordingly, an object of the present invention is to count the reconstructed data in the process of decompressing compressed data in order to solve the problems caused by the conventional video compression system as described above, and determine whether an error has occurred by determining whether the synchronization signal is out of the count value. The present invention provides a video compression system control circuit that eliminates the time delay caused by resetting for each field by resetting only the case.

5 is a synchronous signal generating circuit of the image compression system of the present invention, which receives the digital image data output from the image extension unit 2 that receives the compressed image data and the synchronous signal V _sync and restores them to the original image data. and a coefficient to the counter 10 for generating a synchronizing signal (V _sync4), receiving the input synchronization signal (V _sync3) of the synchronizing signal (V _sync4) and the image expansion section (2) is generated in the counter 10 It consists of an error detection section 11 which detects whether an error has occurred in the transmission data and resets the image extension section 2 if an error is detected.

The circuit of the present invention configured as described above _restores the image data compressed in accordance with the synchronization signal V _sync3 to the original data by the image extending unit 2, and inputs the restored digital image data to the counter 10. If the count value is different from the normal value, the sync and the data are different.

At this time, the image extending unit 2 should be reset so that the generated error does not affect the next data. The error detecting unit 11 performs this function. The comparison synchronizing signal wherein the error detection unit 11 receives the synchronization signal (V _sync4) occurs in the input synchronization signal (V _sync3) and the counter 10 of the image decompression unit (2), synchronizing signal (V _sync4) ( V _sync3 ), and if an error occurs in the sync signal V _sync4 , the reset signal is sent to the image extension unit 2.

However, if no error occurs, the above circuit does not reset the image stretcher 2 unlike the conventional circuit, thereby reducing the signal processing time in the image stretcher 2 according to unnecessary reset. It can be shortened.

FIG. 6 is a detailed circuit diagram of the error detector 11. When the configuration thereof is described, the sync signal V _sync3 input to the image extending unit 2 and the sync signal V _sync4 output from the counter 10 are _described. Are input to 11-1 and 11-2, and the two outputs of the timers 11-1 and 11-2 are applied to one side and the other input terminal of the NOR gate NR11. The output of the timer 11-1 and the sync signal V _sync4 are respectively input to the NOR gate _NR10 . The outputs of the noah gates NR10 and NR11 are input to the noah gate NR 12 at the rear end, and the output of the noah gate NR12 together with the enable signal / ENABLE provides an input signal of the OR gate OR10. The output signal of the OR gate OR10 is applied to the image extending unit 2 as a reset signal.

Referring to the operation and effects of the circuit of the present invention configured as described above in detail as follows.

The operation of the circuit of FIG. 6, which is an error detection circuit according to the present invention, will be described with reference to the timing diagram of FIG. 7. The timers 11-1 and 11-2 are connected to the resistors R1 and R2 connected to the outside thereof. Since the time delay of the input signal can be adjusted by appropriately adjusting the values of the capacitors C1 and C2, the falling edge of the output T1 of the timer 11-1 is generated later than the rising edge of the synchronization signal V _sync4 . When the falling edge of the output signal T2 of the timer 11-2 is generated later than the rising edge of the output signal T1 of the timer 11-1, it is possible to detect that the period of the synchronization signal V _sync4 is _shifted . have.

That is, when the outputs of the timers 11-1 and 11-2 are referred to as T1 and T2, respectively, the outputs of the _{NOA gates NR10 and} NR11 are Q1 = (T1 + V _sync4 ) 'and Q2 =, respectively. Since (T1 + T2) ', the signal Q3 that _nominated these signals is Q3 = (Q1 + Q2)' = ((T1 + V _sync4 ) '+ (T1 + T2)') '= T1 + T2 · V _sync4

In addition, this logical expression causes the output signal Q3 of the NOR gate NR12 to become " low level " when an error occurs in the transmission data and the synchronization signal V _sync4 is distorted. If the synchronizing signal V _sync4 has a normal pulse and timing, the falling edge of the output T1 of the timer 11-1 is generated later than the rising edge of the synchronizing signal V _sync4 and the timer ( Since the falling edge of the output signal T2 of 11-2) is later than the rising edge of the output signal T2 of the timer 11-2, the value of Q3 = T1 + T2 · V _sync 4 is always “high level”. Maintain the state of.

However, if an error occurs in the data and the sync signal V _sync4 generated after the counter 10 counts the data amount is scattered and does not satisfy the timing relationship, the output T1 of the timer 11-1 While the output T2 of the timer 11-2 or the synchronization signal V _sync4 becomes "low level" while having the value of "low level", the output Q3 of the noah gate NR is shown in FIG. As described above, the image expander 2 is reset at a low level.

Therefore, the time required for initializing the system reset and the related circuit can be shortened by counting the amount of recovered data and generating an error signal only when the count value is different from the normal value.

As described above, unlike the method of resetting the system for each field in the video compression or decompression circuit, the present invention resets the system only when an error occurs, thereby minimizing the delay time of signal processing according to the reset process. give.

Claims (3)

The image stretcher 2 which receives the compressed image data and restores the digital image data by the synchronization signal V _sync3 , and counts the amount of data in each field by receiving the image data restored from the image stretcher 2. and a counter (10) for generating a synchronizing signal (V _sync4) corresponding to the counter value, the counter 10, a synchronization signal (V _sync3 applied in which the synchronization signal (V _sync4) and upon decompression of video data generated in the And an error detection unit (11) for detecting whether an error has occurred in the restored data by inputting < RTI ID = 0.0 > The method of claim 1, wherein the error detector 11 receives a synchronization signal V _sync3 and an synchronization signal V _sync4 output from the counter 10 and is delayed for a predetermined time. A timer 11-1, 11-2 for generating a signal, a noah gate NR11 for receiving the two outputs of the timers 11-1, 11-2, and performing a nil operation on the inputs; Noah gate NR10 for outputting the output T1 and the sync signal Vsync4 of 11-1) and the noah gate ('NR12) for outputting the output of the Noah gates NR10 and NR11. And an ORA gate OR10 that receives the output of the NOA gate NR12 together with an enable signal / ENABLE and applies a reset signal to the image extending unit 2. Circuit. 3. The timer 11-1 is characterized in that the falling edge of the output T1 is generated later than the rising edge of the synchronization signal V _{sync4 and} the falling edge of the output signal T2 of the timer 11-2. And the edge is adjusted to occur later than the rising edge of the output signal (T1) of the timer (11-1).