JP5083429B2 - High-speed serial transfer device test method, program and apparatus - Google Patents

Description

The present invention relates to a high-speed serial transfer device test method, program, and apparatus for verifying an out-of-synchronization failure of a high-speed serial transfer device, and in particular, creates a test pattern such that the same value continues in serial transfer data that has been code-converted from the test pattern. The present invention relates to a high-speed serial transfer device test method, program, and apparatus for continuous transfer.

  Conventionally, in a high-speed data transmission system such as Ethernet (R), a high-speed data transfer of a gigabit order is realized using a high-speed serial transfer device.

  In systems and devices that use high-speed serial transfer devices, the proportion of out-of-synchronization and related bit corruption failures (hereinafter referred to as “out-of-synchronization”) accounted for as device failures caused by high-speed serial transfer devices. Many are known.

  The high-speed serial transfer device has a built-in PLL circuit. The PLL circuit detects the shift between the received data and the clock at the timing of the bit change of the received data and feeds back the shift to maintain the synchronization state. As described above, since the timing of detecting and feeding back the shift in the PLL circuit is performed at the timing of the bit change of the received data, the feedback function of the synchronization shift by the PLL circuit while the same value as bit 0 or 1 continues. Does not work.

  As a result, in a high-speed serial transfer device having a weak tolerance against frequency deviation, a margin, etc., the data and the clock are shifted to the extent that the signal cannot be correctly reproduced due to continuous equivalence, resulting in loss of synchronization.

  Although the high-speed serial transfer device is shipped as a single component that has passed the test, when it is mounted in the device, a device with a low tolerance to frequency deviation or a small margin will be affected by noise from the entire device, etc. May cause. For this reason, it is necessary to effectively perform a test for out-of-synchronization in a state where the high-speed serial transfer device is mounted on the apparatus or in an operation state.

Conventionally, a test for verifying out-of-synchronization or the like can be performed using a PRBS pattern (Pseudo-random Binary Sequence) which is a benchmark test for high-speed serial transfer.

JP2002-084247 JP-A-2002-051033 JP 05-028211 JP2001 197043 JP 10-243017 A

Title: What is a pseudorandom number sequence URL: http: // infohost. nmt. edu / tcc / help / lang / fortran / pseudo. html

  However, such a conventional test for verifying out-of-synchronization has a problem that it often takes a long time. One reason for this is that a test using a pattern aimed at detecting loss of synchronization of a high-speed serial transfer device is not performed. In addition, the test using the PRBS pattern, which is a benchmark test for high-speed serial transfer devices, is not a pattern specially designed for detection of out-of-synchronization of high-speed serial transfer devices. Absent.

  For this reason, if a high-speed serial transfer device is shipped as a test pass for a single component, but a device with an out-of-synchronization of the high-speed serial transfer device passes the mass production test and fails in the field, it is collected and investigated. , Repair and maintenance procedures take time and effort, which contributes to increased costs.

  In a high-speed serial transfer device, for example, transfer data is serially transferred after code conversion. In this code conversion, a running disparity RD (Running Disparity) is used to support weak signal amplification. It has two different code conversion tables, RD-conversion and RD + conversion, and whether the conversion of the next data is RD + conversion depending on whether the number of bits 0 and 1 of the preceding post-conversion data is the same or different RD -Controls whether to convert.

  For this reason, as one of the function tests of the high-speed serial transfer device, it is desired to test all functions on the receiving side in the field by flowing all the converted data stored in the code conversion table to the transfer channel in order. In this test, for example, in the case of 8-bit / 10-bit conversion, 256 types of 8-bit data may be continuously flowed for conversion.

  However, there are two different conversions, RD + conversion and RD- conversion, in the code conversion of the high-speed serial transfer device, and which one is converted depends on the RD value of the converted data immediately before the test pattern. It cannot be identified externally depending on the current state of the device. Therefore, even if 256 types of 8-bit data are continuously flowed, it is not possible to transfer all the converted data in the code conversion table for which the RD + conversion and the RD- conversion are performed.

  Therefore, by repeating the flow of 256 types of 8-bit data, it is only possible to statistically approximate the function verification using all the converted data, and the verification takes time and the number of converted data that is not transferred is small. There is a problem that remains.

  The present invention creates a test pattern specialized for verification of out-of-synchronization failure in a high-speed serial transfer device and continuously transfers it within the target device, thereby enabling high-speed serial transfer to verify out-of-synchronization in a short time An object is to provide a device test method, a program, and an apparatus.

The present invention also provides a high-speed serial transfer device test method, program, and apparatus that can generate a test pattern for transferring all post-conversion data in code conversion of a high-speed serial transfer device to enable functional tests to be verified in a short time. For the purpose.

(High-speed serial transfer device test method)
The present invention provides a high-speed serial transfer device test method. The high-speed serial transfer device test method of the present invention comprises:
Test pattern creation that creates a test pattern in which pre-conversion data is arranged so that the same value of bit 0 or 1 is continuously transferred to each of a plurality of serial transfer channels of a high-speed serial transfer device using the converted data by the code conversion table Steps,
A test step in which a test pattern is input to a high-speed serial transfer device on the transmission side, code-converted, and the converted data is continuously transferred so as to pass through the serial transfer channel to verify out-of-sync failure on the reception side,
It is provided with.

Here, the test pattern creation step
A basic pattern setting step for setting a basic pattern in consideration of a byte order system and a running disparity (RD value) of code conversion in a high-speed serial transfer device;
A basic pattern resetting step for resetting the basic pattern according to the channel usage of the bit transfer order in the high-speed serial transfer device;
A basic pattern rearrangement step for rearranging the basic pattern so that it is transferred to each channel according to the channel usage method such as the bit transfer order and the number of channels used in the high-speed serial transfer device;
It is provided with.

The code conversion table used for code conversion in the high-speed serial transfer device converts m-bit data of one conversion unit into n-bit data having a large number of bits, and the converted data is RD + conversion in which running disparity becomes positive. An m-bit / n-bit code conversion table for performing two conversions of RD-conversion in which running disparity is negative.
The basic pattern setting step is
determining whether the converted data in one unit of conversion in the m-bit / n-bit code conversion table includes the same number of consecutive consecutive bits 0 or 1 of the specified run length or more;
1 unit test pattern extraction step for extracting, as a test pattern, pre-conversion data that satisfies the specified run length within one unit of the converted data when the number of consecutive equivalences greater than or equal to the specified run length is included;
A 2-unit test pattern extraction step for extracting, as a test pattern, 2 units of pre-conversion data that satisfy the specified run length at the boundary portion combining the 2 units of the converted data if the number of consecutive equivalences greater than the specified run length is not included When,
Is provided.

The 2 unit test pattern extraction step consists of:
Two units of pre-conversion data are (X) and (Y), the respective post-conversion data are (X: RD−) and (X: RD +), and the post-conversion data of data Y is (Y: RD−) and When (Y: RD +),
Changes in running disparity of post-conversion data in a data stream (XYXYXYXY... XY) obtained by cyclically transferring two units of pre-conversion data (XY).
(1) Running disparity of the converted data stream when the number of bits 0 and 1 of the converted data of the data X is different and the number of bits 0 and 1 of the converted data of the data Y is the same number Changes in (X: RD +) (Y: RD-) (X: RD-) (Y: RD +)
The first case that repeats
(2) Running disparity of the converted data stream when the number of bits 0 and 1 of the converted data of the data X is different and the number of bits 0 and 1 of the converted data of the data Y is the same number Changes in (X: RD-) (Y: RD +) (X: RD +) (Y: RD-)
The second case, which repeats
(3) The running disparity of the converted data stream when the number of bits 0 and 1 of the converted data of data X is the same and the number of bits 0 and 1 of the converted data of data Y is different Change is (X: RD +) (Y: RD +) (X: RD-) (Y: RD-)
The third case that repeats
(4) The running disparity of the converted data stream when the number of bits 0 and 1 of the converted data of data X is the same and the number of bits 0 and 1 of the converted data of data Y is different Change is (X: RD-) (Y: RD-) (X: RD +) (Y: RD +)
The fourth case that repeats
(5) Changes in running disparity of the converted data stream when the number of bits 0 and 1 of the converted data of data X and Y are different (X: RD +) (Y: RD-)
The fifth case that repeats
(6) The change in running disparity of the converted data stream when the number of bits 0 and 1 of the converted data X and Y is different is (X: RD−) (Y: RD +)
The sixth case, which is a repetition of
(7) Changes in running disparity of the converted data stream when the number of bits 0 and 1 of the converted data of data X and Y are the same (X: RD +) (Y: RD +)
The seventh case, which repeats
(8) Changes in running disparity of the converted data stream when the number of bits 0 and 1 of the converted data of data X and Y are the same (X: RD−) (Y: RD−)
The 8th case,
In this case, two units of pre-conversion data satisfying the designated RL at the boundary portion are extracted as test patterns.

  The 2-unit test pattern extraction step consists of a first byte order method (little endian method) that takes a bit arrangement with the lower end as the lower bit in a high-speed serial transfer device, and a second byte order that takes a bit arrangement with the upper end as the upper bit. Corresponding to each of the systems (big endian system), 2 units of pre-conversion data satisfying the designated RL at the boundary portion of the 2 units of conversion data are extracted as test patterns.

When the high-speed serial transfer device is provided with an 8-bit / 10-bit code conversion table (hereinafter referred to as “8b / 10b code conversion table”), the 2-unit test pattern extraction step uses XY = F4EB or XY = EBF4
To decide.

  In the basic pattern reset step, the basic data is set so that the post-transfer data according to the bit transfer order control that determines the transfer order is divided into odd bits and even bits in the high-speed serial transfer device becomes the basic data that satisfies the specified field or length. Is reset to the data before the bit transfer order control to obtain basic data.

For example, the basic pattern resetting step is a two-unit test pattern extracting step, in which XY = F4EB or XY = EBF4 in hexadecimal display as a basic pattern from the 8b / 10b code conversion table of the high-speed serial transfer device.
, XY = E9CF or XY = CFE9 from the basic pattern as the reset basic pattern in accordance with the bit transfer order control in which the odd bits are transferred first and then the even bits are transferred.
To reset.

  The basic pattern rearrangement step rearranges one unit of basic pattern (X) or two units of basic pattern (XY) so that the basic patterns are continuous by the number of channels in the high-speed serial transfer device.

  In the basic pattern rearrangement step, when the high-speed serial transfer device has four channels, the basic pattern (X) of one unit is rearranged to repeat the basic pattern (XXXX), and the basic pattern (XY) of two units is changed to the basic pattern (XXXXYYYY). ) Is repeated.

  The basic pattern resetting step is a two-unit test pattern extraction step, which determines (F4EB) or (EBF4) in hexadecimal notation as the basic pattern from the 8b / 10b code conversion table of the high-speed serial transfer device. Is 4 channels, the basic pattern F4EB is rearranged to repeat the basic pattern (F4F4F4F4EBEBEBEBEB), and the basic pattern EBF4 is rearranged to repeat the basic pattern (EBEBEBEBBF4F4F4F4).

(Code conversion function test method)
According to another aspect of the present invention, there is provided a high-speed serial transfer device test method for flowing all converted data in code conversion from a high-speed serial transfer device.

The high-speed serial transfer device test method of the present invention comprises:
A test pattern creation step for creating a test pattern in which pre-conversion data is arranged so that all post-conversion data stored in the code conversion table is continuously transferred to each of a plurality of serial transfer channels of the high-speed serial transfer device When,
A test step in which a test pattern is input to a high-speed serial transfer device on the transmission side to perform code conversion, and all converted data in the code conversion table is continuously transferred so as to pass through the serial transfer channel, thereby verifying the function on the reception side. ,
It is provided with.

The test pattern creation step
In the code conversion table, the number of bits 0 and 1 of the converted data is the same, and there is no RD change group that does not change the running disparity of the subsequent converted data, and the number of bits 0 and 1 of the converted data is A group classification step for classifying into a group with RD change that changes the running disparity of the subsequent converted data differently;
Each unit of data before conversion in the RD-changeless group is arranged one unit at a time to form a first group, and then the same data of each data before conversion in the RD-changed group is arranged in units of two to form a second group. Subsequently, only one unit of predetermined pre-conversion data belonging to the group with RD change is arranged to form the third group, and each pre-conversion data of the group without RD is arranged one unit at a time to form the fourth group. A test pattern placement step for generating a test pattern by
A test pattern rearranging step for rearranging the test patterns so that all converted data is transferred to each channel according to the number of channels used in the high-speed serial transfer device;
It is provided with.

When the code conversion table is an 8b / 10b code conversion table,
The group classification step classifies the 8b / 10b code conversion table into 133 types of RD change-free groups and 123 types of RD change groups.
In the test pattern placement step, 133 types of 8-bit data in the RD-change-free group are arranged one unit at a time to form the first group, and then 123 types of 8-bit data in the RD-change group are set in two units. The second group is arranged to form a third group by arranging only one unit of predetermined 8-bit data belonging to the group with RD change, and further each of 133 types of 8-bit data of the group without RD. One unit is arranged to form a fourth group to generate a test pattern.

  The test pattern rearrangement step rearranges one unit of pre-conversion pattern (X) or two units of pre-conversion pattern (XX) so that one unit pattern is continuous by the number of channels in the high-speed serial transfer device.

(program)
The present invention provides a test data creation program for creating test data for verifying out of synchronization. The test data creation program of the present invention is stored in a computer.
A designation information input step for reading the designation information of the conversion method of the code conversion table of the high-speed serial conversion device, and the run length designation information for continuously transferring the same value of bit 0 or 1 with the converted data by the code conversion table;
Create a test pattern in which the pre-conversion data is arranged so that the same value of bit 0 or 1 of the specified run length is continuously transferred to each of the multiple serial transfer channels of the high-speed serial transfer device using the converted data from the code conversion table A test pattern creation step to perform,
Is executed.

The present invention also provides a test data creation program for verifying the code conversion function. The test data creation program of the present invention is stored in a computer.
A designation information input step for reading designation information of the conversion method of the code conversion table of the high-speed serial conversion device;
A test data creation step for creating a test pattern in which pre-conversion data is arranged so that all post-conversion data stored in the code conversion table is continuously transferred to each of a plurality of serial transfer channels of the high-speed serial transfer device When,
A test pattern rearranging step for rearranging so that all converted data is transferred to each channel according to the number of channels used in the high-speed serial transfer device;
Is executed.

(apparatus)
The present invention provides a test data creation apparatus for creating test data for verifying out of synchronization. The test data creation apparatus of the present invention is
A designation information input unit for reading the designation information of the conversion method of the code conversion table of the high-speed serial conversion device, and the run length designation information for continuously transferring the same value of bit 0 or 1 with the converted data by the code conversion table;
Create a test pattern in which the pre-conversion data is arranged so that the same value of bit 0 or 1 of the specified run length is continuously transferred to each of the multiple serial transfer channels of the high-speed serial transfer device using the converted data from the code conversion table A test pattern creation unit,
It is provided with.

The present invention also provides a test data creation device for creating test data for a code conversion function test. The test data creation apparatus of the present invention is
A designation information input unit that reads designation information of a conversion method of a code conversion table of a high-speed serial conversion device;
A test pattern creation unit that creates a test pattern in which pre-conversion data is arranged so that all post-conversion data stored in the code conversion table is continuously transferred to each of the plurality of serial transfer channels of the high-speed serial transfer device When,
A test data rearrangement unit that rearranges test patterns so that all converted data is transferred to each channel according to the number of channels used in the high-speed serial transfer device;
It is provided with.

  According to the present invention, a test pattern is input to a high-speed serial transfer device incorporated in a system or apparatus, and sign conversion is performed, whereby converted data having the same value continues to flow through a serial transfer channel and specializes in verification of out-of-sync failure. The system can be tested and the ability to verify out-of-synchronization of high-speed serial transfer devices can be enhanced compared to the conventional method. be able to. For this reason, an apparatus having a high-speed serial transfer device out-of-synchronization device is not shipped, and field quality can be improved.

  In addition, a test pattern specialized for verification of out-of-synchronization failures in accordance with the code conversion method, byte ordering method, and number of channels of high-speed serial transfer devices is created and tested. This greatly reduces the number of test steps and costs.

  Even if out-of-synchronization of the high-speed serial transfer device occurs in the field, the test using the test pattern specialized for verification of out-of-synchronization failure created by the present invention will result in out-of-synchronization failure compared to the conventional case. The time required for the reproduction test is shortened, and procedures such as collection, investigation, repair, and maintenance can be appropriately and efficiently performed.

In another embodiment of the present invention, a test pattern for performing conversion using all of two conversion methods RD-conversion and RD-re conversion in the code conversion table used in the high-speed serial transfer device is generated. By doing so, all RD-conversion and RD-re conversion are performed in one test pattern conversion without depending on the running disparity of the converted data immediately before the start of the test, and the converted data is sent to the serial transfer channel. Can be evaluated.

Block diagram of an embodiment of a test data creation apparatus of the present invention for creating a test pattern for verification of out-of-sync failure Explanatory drawing of the code conversion table of FIG. Explanatory drawing of the code conversion management table of FIG. Explanatory drawing of 8b / 10b code conversion table used for code conversion of high-speed serial transfer device 1 is a block diagram of a hardware environment of a computer that realizes the function of the test data creation apparatus of FIG. Block diagram of a high-speed serial transfer device using the test pattern of the present invention Block diagram of the input FIFO and 8/10 encoder of FIG. Circuit block diagram of 8b / 10b conversion circuit of FIG. Explanatory drawing which divided | segmented the equivalence continuous pattern which arises in the boundary part at the time of combining the data after 2 units of conversion in 8b / 10b code conversion by the byte order system. Explanatory drawing combining 2 units of post-conversion data using the little endian method with the end side as the lower bit Explanatory drawing of switching the converted data of 2 units using the little endian method to the big endian method with the higher end bit at the end and obtaining the number of consecutive equivalences at the boundary Explanatory drawing which divided the case into the RD value change in cyclic repetitive transfer of 2 units of converted data XY Explanatory drawing of the test pattern 0xF4EB obtained by controlling the bit transfer order of the test pattern 0xF4EB Explanatory drawing of problems when basic pattern 0xF4EB is transferred continuously without considering the number of serial transfer channels Explanatory drawing when the basic pattern 0xF4EB is rearranged according to the number of serial transfer channels and transferred continuously The flowchart which showed the basic process sequence of the test data creation process in embodiment of FIG. Flowchart of basic pattern creation processing in step S1 of FIG. Flowchart of 2-unit generation processing in step S4 of FIG. Flowchart of generation processing of cases 1 to 4 in step S2 of FIG. 19 is a flowchart of generation processing following FIG. Flowchart of generation processing of cases 5 and 6 in step S3 in FIG. Flowchart of generation processing following FIG. Flowchart of generation processing of cases 7 and 8 in step S4 in FIG. Flow chart of generation processing following FIG. Explanatory drawing of the test method using the test pattern created in the embodiment of FIG. Explanatory drawing of another test method using the test pattern created in the embodiment of FIG. Block diagram of an embodiment of the present invention for creating a test pattern for performing all RD conversions in the code conversion table Explanatory drawing which divided the change of RD value at the time of cyclically transferring 2 units of pattern XY and the appearance of RL = 5 into cases Explanatory drawing of a change of RD value at the time of cyclically transferring the pattern of 3 units about cases 5-8 of FIG. Explanatory drawing which grouped the 8b / 10b code conversion table for creating the test pattern which performs all RD conversions without depending on the RD value immediately before transfer Explanatory drawing which showed the relationship between the test pattern created based on the grouping of FIG. 30, and RD conversion Explanatory drawing of the use area | region of the 8b / 10b code conversion table at the time of carrying out code conversion of the test pattern of FIG. Flowchart of test pattern creation processing according to the embodiment of FIG.

  FIG. 1 is a block diagram of an embodiment of a test data creation apparatus of the present invention that creates a test pattern for verifying an out-of-sync failure.

  In FIG. 1, the test data creation apparatus of the present invention comprises a test pattern creation unit 10, a run length designation unit 12, a code conversion method designation unit 14, a code conversion table 16, a code conversion management table 18, and a test pattern storage unit 20. Is done.

  In the test pattern creation unit 10, before conversion, the same value of bit 0 or 1 is continuously transferred to each of a plurality of serial transfer channels included in the high-speed serial transfer device using the converted data by the code conversion table. Create a test pattern with the data arranged. The test pattern created by the test pattern creation unit 10 is input to the high-speed serial transfer device on the transmission side, converted in code, and continuously transferred so that the converted data passes through each of the plurality of serial transfer channels. Verify the failure of the high-speed serial transfer device on the device side, such as loss of synchronization and accompanying bit corruption.

  The test pattern creation unit 10 is provided with functions of a basic pattern setting unit 22, a basic pattern resetting unit 24, and a basic pattern rearranging unit 26. The basic pattern setting unit 22 sets the basic pattern in consideration of the byte order system and the running disparity value of code conversion (hereinafter referred to as “RD value”) in the high-speed serial transfer device.

  The basic pattern resetting unit 24 resets the basic pattern in accordance with the channel usage method of the bit transfer order in the high-speed serial transfer device.

  Further, the basic pattern rearrangement unit 26 rearranges the basic pattern so that the basic pattern is continuously transferred to each channel according to the channel usage method such as the bit transfer order and the number of channels used in the high-speed serial transfer device.

  FIG. 2 is an explanatory diagram of the code conversion table 16 of FIG. The code conversion table 16 is the same code conversion table as that used in the high-speed serial transfer device for which a test pattern is to be created. The code conversion table 16 converts m-bit data of one conversion unit into n-bit data having a large number of bits as a conversion method, and the converted data is a plus RD + conversion in which the running disparity becomes positive and the running disparity. Two post-conversion data of minus RD-conversion with a negative parity are provided.

  Specifically, “conversion methods” in the code conversion table 16 include 1b / 2b, 3b / 4b, 4b / 5b, 5b / 6b, 8b / 10b, and the like. In the following description of the present embodiment, an example of the conversion method is 8b / 10b, that is, a conversion method that converts 8-bit data in one conversion unit into 10-bit data. The 10-bit data after conversion becomes data after conversion by RD + conversion and data after conversion by RD- conversion.

  “Input data” in the code conversion table 16 is pre-conversion data to be converted. In the 8b / 10b code conversion, 256 types of 8 bits of “0x00,..., 0xFF” are expressed as octet values (hexadecimal). Data becomes input data.

  The “converted bit string (RD−)” prepares 10-bit data after conversion as an address and stores a binary value in each element. The same applies to the “converted bit string (RD +)”. “RD conversion exchange presence / absence” is a parameter for determining whether the number of 0's and the number of 1's in the bit code of the 10-bit data after conversion are the same or not. Whether the number of 0s or 1s in the converted data is the same or different is data necessary for switching whether the next code conversion is the RD conversion Ho or the RD + conversion. Make it clear in the description.

  FIG. 3 is an explanatory diagram of the code conversion management table 18 of FIG. The code conversion management table 18 includes, as items, “conversion method”, “number of conversions”, “maximum RL”, “maximum RL within one conversion unit”, “RD + maximum number of equivalent equivalences”, “RD + conversion j side” “Maximum Equivalent Consecutive Number”, “RD-Conversion a-side Maximum Equivalent Consecutive Number” and “RD-Conversion j-side Maximum Equivalent Consecutive Number” are stored.

  The “conversion method” is the same as the code conversion table 16 of FIG. “The number of conversions” is the number of converted data with respect to input data. In 8b / 10b code conversion, there are 256 types of input data. On the other hand, the number of converted data includes RD + conversion and RD− conversion. 256 × 2 = 512.

  “Maximum RL” is a value determined by a conversion method, for example, 8b / 10b code conversion. In this case, RL = 5. In the present invention, the creation process is performed so as to generate a test pattern having the maximum RL in this code conversion method.

  “Maximum RL in one unit of conversion” is the maximum number of run lengths in which 0 or 1 continues in one of the converted data, and RL = 4 is the maximum in the 8b / 10b code conversion. This means that it is not possible to secure the maximum number of consecutive RL = 5 necessary for the test pattern in one conversion unit. Therefore, in the case of 8b / 10b code conversion, the test pattern creation processing of the present invention is processed so that the maximum RL = 5 is realized at the boundary portion by combining the data of 2 conversion units instead of the data of 1 conversion unit. ing.

  Each of the next “maximum number of continuous equivalence on the side of RD + conversion a” and “maximum number of continuous equivalence on the side of RD + conversion j”, for example, in 8b / 10b code conversion, 8-bit data is converted into 10-bit data, For the 10-bit data after conversion, a code table is created with the first 6 bits on the a side and the latter 4 bits on the j side. In this converted 10-bit data, the maximum number of consecutive equivalences in the first half of 6 bits is stored as table information, which is “3” in the case of 8b / 10b code conversion. This is the same 3 on the j side, which is the last 4 bits of the RD + conversion.

  Similarly, the “maximum number of consecutive equivalences on the RD-conversion a side” and “maximum number of consecutive equivalences on the RD + conversion j side” are also “3” in the 8b / 10b code conversion.

  FIG. 4 is an explanatory diagram showing a part of an 8b / 10b code conversion table used for code conversion of the high-speed serial transfer device. In FIG. 4, the 8b / 10b code conversion table 28 includes a code group name 30, an octet value (hexadecimal number) 32, an octet bit 34, RD-conversion data 36, and RD + conversion data 38. Of these, the octet value 32 and the octet bit 34 are 8-bit input data, and the RD-converted data 36 and the RD + converted data 38 are 10-bit converted data.

  As is apparent from the 8b / 10b code conversion table 28, two types of RD-converted data and RD + converted data are provided for one 8-bit input data. For this reason, there are 256 ways × 2 = 512 ways of converted 10-bit data with respect to 256 ways of 8-bit input data.

  Further, as shown below the 8b / 10b code conversion table 28, the RD-conversion data 36 and the RD + conversion data 38 are divided into the first 6 bits and the latter 4 bits, and the first 6 bits are assigned to the a side, The latter 4 bits are on the j side.

  FIG. 5 is a block diagram of a hardware environment of a computer in which the function of the test data creation apparatus of FIG. 1 is realized. In FIG. 5, a device interface 52 and a network adapter 60 for connecting a RAM 46, a ROM 48, a hard disk drive 50, a keyboard 54, a mouse 56, and a display 58 are connected to the bus 44 of the CPU 42.

  The hard disk drive 50 is installed with a program for executing the test pattern creation processing of the present invention. When the computer is started, the program is read from the hard disk drive 50 to the RAM 46 and executed by the CPU 42.

  Next, the creation of the test pattern in the embodiment of the test data creation apparatus of FIG. 1 will be described in detail.

  On the receiving side of the high-speed serial transfer device, synchronization at the timing of the bit change in the received data after code conversion prevents synchronization loss and bit corruption (hereinafter simply referred to as “out of synchronization”). Yes. For this reason, as a test pattern for verifying an out-of-synchronization failure, it is effective to continuously transfer data that can obtain a bit string in which the same value of bits 0 or 1 continues as much as possible in the data after code conversion, that is, continuous data of the same value. is there.

  Equivalent continuous data that becomes such a test pattern can be obtained by back-calculating from the code conversion logic in the high-speed serial transfer device. However, simply transferring the obtained equivalent continuous data does not become equivalent continuous data.

  This is because a high-speed serial transfer device usually has multiple serial transfer channels, and the distribution method and transfer bit order of the transfer target data to each channel depends on the channel usage method and transfer method of the target high-speed serial transfer device. This is because even if simple continuous data is simply transferred, it may not actually be transferred to each channel.

  Therefore, it is necessary to rearrange the equivalence continuous data according to the channel usage method etc. with respect to the equivalence continuous data obtained by the reverse calculation from the code conversion logic, and to create a test pattern for continuously transferring this as test data.

  FIG. 6 is a block diagram of a high-speed serial transfer device to which the test pattern of the present invention is applied. In FIG. 6, the high-speed serial transfer devices 62-1 and 62-2 are connected by, for example, 4-channel serial transfer paths 65-1 and 65-2 to form a 4-lane serial transfer path.

  The high-speed serial transfer devices 62-1 and 62-2 include a transmission unit 64-1 and a reception unit 66-1, as shown on the high-speed serial transfer device 62-1 side. The transmission unit 64-1 is provided with an input FIFO 68, 8/10 encoders 70-1 to 70-4, SP converters 72-1 to 72-4, drivers 74-1 to 74-4, and a PLL circuit 76. .

  The receiver 66-1 is provided with receivers 78-1 to 78-4, a PLL circuit 80, SP converters 82-1 to 82-4, 8/10 decoders 84-1 to 84-4, and an output FIFO 86. Yes.

  FIG. 7 shows the input FIFO 68 and 8/10 encoders 70-1 to 70-4 shown in FIG. For example, data is input to the input FIFO 68 in a 32-bit width, that is, a 4-byte width, and the data for each channel is stored in the input FIFO 68 in units of 8 bits corresponding to 4 channels.

  Here, assuming that the four channels are channels A, B, C, and D, bits 0 to 7, 32 to 39,... Are given to channel A, and bits 8 to 15, 40 to 47,. .. Are given, channel 16 is given bits 16-23, 48-55,..., And channel D is given bits 24-31, 56-63,.

  The 8/10 encoders 70-1 to 70-4 are provided with interleavers 88-1 to 88-4 and 8b / 10b code conversion circuits 90-1 to 90-4. The interleavers 88-1 to 88-4 send odd bits first and send even bits after every predetermined transfer unit based on the bit transfer order system of the high-speed serial transfer device 62-1, or conversely, even bits first. The bit transfer order control is performed to send odd number bits or send odd number bits later. A normal high-speed serial transfer device employs a bit transfer order system in which odd bits are first and even bits are next.

  FIG. 8 is a circuit block diagram of the 8b / 10b conversion circuit 90-1 shown in FIG. 8, the 8b / 10b conversion circuit 90-1 includes a register 92, an RD− 8b / 10b conversion table 94, an RD + 8b / 10b conversion table 96, a selector 98, and an RD determination switching unit 100.

  The register 92 holds 8-bit input data. The 8-bit data in the register 92 is input to the RD- 8b / 10b conversion table 94 and the RD + 8b / 10b conversion table 96, converted into corresponding 10-bit data, and output to the selector 98.

  The selector 98 is selected and controlled by the RD determination unit 100. The RD determination unit 100 determines whether the number of bits 0 and 1 in the 10-bit data after the previous conversion is the same or different. If the number is different, the RD is switched for the next conversion data. Do.

  That is, if the preceding code data is, for example, RD-conversion, and the number of bits 0 and 1 of the converted data is the same, the next conversion is the same RD-conversion. On the other hand, if the values of bits 0 and 1 of the preceding post-conversion data are different, the next conversion is determined as conversion exchange and is set as RD + conversion.

  The high-speed serial transfer device having the configuration shown in FIGS. 6 to 8 takes, for example, the high-speed serial transfer device 62-1 shown in FIG. After encoding and serializing, high-speed transfer is performed to the high-speed serial transfer device 62-2 through the 4-channel serial transfer path 65-1, and the serial data received by the receiving unit 66-2 is decoded and returned to parallel data. Transfer to the subsequent stage.

  The loss of synchronization in this case is observed as a reception error in the receiving unit 66-2 of the high-speed serial transfer device 62-2 as the transmission destination. Therefore, it is necessary to create a test pattern that easily causes a reception error in the receiving unit 66-2 in order to verify the loss of synchronization of the high-speed serial transfer device.

  In the present invention, a data pattern specialized for causing out-of-synchronization on the receiving side of the high-speed serial transfer device is created as a test pattern. Since a reception error in the receiving unit is a cause of loss of synchronization, the received data on the receiving side, that is, data passing through the receiving-side serial unit of the high-speed serial transfer device is set to a pattern that easily induces out of synchronization.

  A pattern that easily causes out-of-synchronization of a high-speed serial transfer device is a pattern that has a large run length (the maximum number of consecutive equivalences) and a small change in bits from 0 to 1 and from 1 to 0. The reason is due to a mechanism such as loss of synchronization in a high-speed serial transfer device.

  That is, as shown in FIG. 6, when the high-speed serial transfer device 62-1 is taken as an example, the receiving unit 66-1 includes a PLL circuit 80, and the PLL circuit 80 shifts the received data from the clock. Detects and keeps synchronized by feeding back the deviation. The feedback performed by detecting the difference between the received data and the clock is performed at the timing of the bit change of the received data.

  For this reason, the feedback function of the synchronization shift by the PLL circuit 80 does not work while the same value is continued for the received data. As a result, for a high-speed serial transfer device with weak tolerance against frequency deviation, margin, etc., the received data and the clock are shifted to the extent that the signal cannot be correctly reproduced due to the continuous value, resulting in loss of synchronization.

  Usually, a high-speed serial transfer device is provided with a plurality of channels. For this reason, the focus of the test pattern created by the present invention is to create a state in which a high-speed serial transfer device is likely to be out of synchronization by efficiently creating and transferring a pattern having a large run length to each transfer channel. It becomes.

  In the present invention, the test data to be transmitted to the high-speed serial transfer device so that the same values are continuous is obtained from the reverse calculation of the code conversion method. Here, the reverse calculation of the code conversion method means that the high-speed serial transfer device serially transfers the encoded data after encoding the actual transfer data by adding a certain number of bits by code conversion. Means that the actual data is determined retroactively from the encoded data so as to be equivalent continuous data.

In this way, the process of selecting the basic pattern for the test from the code conversion table for the pre-conversion data to be input to the high-speed serial transfer device so that the same value continues in the encoded data. In that case, it is necessary to determine the basic pattern in consideration of the following points.
(1) Consideration of byte order (2) Consideration of running disparity (3) Consideration of bit transfer order (4) Consideration of number of transfer channels

First, consideration of byte order when determining a basic pattern will be described. Since the basic pattern is meaningful in the order in which the bit string transfers the serial part of the high-speed serial transfer device, it is necessary to consider the byte order system. The byte ordering method includes (1) a little endian method (little endian method) that takes a bit arrangement with the terminal side as the lower bit.
(2) Big endian system that takes a bit array with the termination side as the upper bits
There are two.

  Considering this byte ordering method, the larger the equivalency number, the more the equivalent equivalence number cannot be obtained with one unit of code conversion, and when two units of code transformation are combined, the equivalence number Will be obtained. For example, in the 8b / 10b code conversion, as shown in the code conversion management table 18 of FIG. 3, the maximum RL given in the specification is RL = 5, and this equivalence number 5 is a combination of 2 bytes (8b × 2). Can be obtained for the first time.

  FIG. 9 is an explanatory diagram showing the equivalence continuous pattern generated at the boundary when the two units of converted data in the 8b / 10b code conversion are combined, divided by the byte order method. In the boundary equivalence continuous pattern list 102 of FIG. 9, the bit order is divided into the little endian method and the big endian method as the byte order, and the 10-bit bit string number which is the converted data is shown. At the data boundary 104 of the 10-bit converted data obtained by the code conversion of the data combination, a pattern having the same number of consecutive RL = 5 belonging to any of the patterns 1 to 4 is obtained.

  FIG. 10 is an explanatory diagram in which two units of post-conversion data using the little endian method with the end side as the lower bit are combined. The equivalence area 110 of the post-conversion data 106 is on the upper bit side, and the post-conversion data 108 On the contrary, this is the case where the equivalence area 112 exists on the lower bit side. In this case, an equivalence number of RL = 5 can be obtained from the equivalence areas 110 and 112 adjacent to the boundary between the two converted data 106 and 108.

  FIG. 11A shows a case where the converted data 114-1 and 116-1 adopting the same little endian method as FIG. 10 are combined. In this case, the equivalence areas 118-1 and 120-1 are opposite to the boundaries. May exist on the bit side.

  In such a case, as shown in FIG. 11B, in the case of the big endian method, equivalence areas 118-2 and 120-2 are present on both sides of the boundary for the same converted data 114-2 and 116-2. In the case of the little endian method, the equivalent continuous number of RL = 5 cannot be ensured. In the big endian method, the equivalent continuous number of RL = 5 can be ensured at the boundary portion.

  Therefore, when determining the test pattern of the present invention, the number of consecutive equivalences required as a test pattern is determined in consideration of whether the byte order method adopted by the high-speed serial transfer device is a little endian method or a big endian method. It is necessary to determine the pre-conversion data to have.

  Next, consideration of running disparity (RD value) when determining a test pattern will be described. Running disparity in a high-speed serial transfer device is a technique used to support weak signal amplification. In the conversion technique using the code conversion table such as 3b / 4b, 4b / 5b, 5b / 6b, 8b / 10b, in the case of conversion 1 unit, for example, 8b / 10b conversion, the conversion 1 unit is 8 bits. On the other hand, there are two different conversions, RD + conversion and RD- conversion, and these two conversions are selectively used according to the value of running disparity.

  That is, consideration of running disparity means that a basic pattern is determined including switching between RD + conversion and RD− conversion by data itself flowing through the transfer channel.

  For example, when data X and data Y are cyclically transferred as “XYXYXY...” As pre-conversion data used in the test, the state of change in the RD value is any of cases 1 to 8 in FIG.

  In the 2-unit cyclic pattern RD change list 122 of FIG. 12, the state of the RD value change and the conditions of the X and Y data at that time are shown for cases 1 to 8. “Conditions for X and Y data” are “there is a number difference” or “there is no number difference” for the number of bits 0 and 1 in 10-bit data after conversion by 8b / 10b conversion of data X and Y. As a condition. In addition, the notation shown in “change of RD value” means that, for example, (X: RD +) means that the data X has been RD + converted.

The change in the RD value due to the difference in the number of bits 0 and 1 in the converted data follows the following rule.
(1) If there is no difference in the number of bits 0 and 1 of the converted data (the same number), RD conversion is not exchanged.
(2) If there is a difference in the number of bits 0 and 1 of the converted data (if the number is different), RD conversion is exchanged.

  For example, taking case 1 in FIG. 12 as an example, in cyclic transfer data “XYXYXYXY...”, The number of bits 0 and 1 of the converted data of data X has a number difference, while the converted data of data Y This is a case where there is no difference in the number of bits 0 and 1. In this case, since there is a difference in the number of bits 0 and 1 in the converted data (X: RD +) of data X, RD conversion is exchanged for the converted data of the next data X, and the converted data is ( Y: RD-).

  As for the next data X, there is no difference in the number of the converted data of the immediately preceding data Y, so the RD conversion is not exchanged, and the converted data is (X: RD−). Subsequently, since there is a difference in the number of converted data for data X, RD conversion is exchanged for the converted data of the next data Y, and the converted data becomes (Y: RD +). This is repeated below.

  Case 2 is a case where the post-conversion data immediately before the first data X in case 1 is RD−, and the change of (X: RD−) (Y: RD +) (X: RD +) (Y: RD−) Become. Here, even if the data X and Y are the same data, whether to be case 1 or case 2 is determined by whether the RD value of the immediately preceding converted data is based on RD-conversion or RD + conversion. It will be.

  Cases 3 and 4 are cases where there is no difference in the number of bits 0 and 1 of the converted data of data X and there is a difference in the number of bits 0 and 1 of the converted data of data Y. Cases 5 and 6 are cases where both the data X and Y have a difference in the number of bits 0 and 1 of the converted data. In this case, exchange of RD conversion is repeated for each data conversion.

  Further, cases 7 and 8 are cases in which there is no difference in the number of bits 0 and 1 of the converted data in both data X and Y. RD conversion is not exchanged for data X and Y, and the first converted data RD continues.

When the basic pattern is determined based on the consideration of the above byte order method and the consideration of running disparity, in the present embodiment, the maximum continuous number of RL = 5 is created with the encoded data in the 8b / 10b code conversion. XY = 0xF4EB or XY = 0xEBF4 as one of the data XY that is a combination of two units of data before conversion
Can be determined. Here, “XY = 0xF4EB” corresponds to case 6 in FIG. 12, and “XY = 0xEBF4” corresponds to case 5 in FIG.

  If the basic pattern can be determined in this way, it is necessary to rearrange the test pattern actually used in consideration of the bit order and the number of transfer panels. This is because high-speed serial transfer devices usually have multiple data transfer channels, but the number of channels actually used in the device and the bit transmission order differ depending on the mounting location and design concept. The test pattern must be created in consideration of

  Therefore, the basic pattern rearrangement considering the bit transfer order will be described. In the high-speed serial transfer device, the bit transfer order is taken into account, for example, as shown in FIG. 7, the interleavers 88-1 to 88-4 are arranged before the 8b / 10b code conversion circuits 90-1 to 90-4. In some cases, for example, odd-numbered bits are transferred first with respect to pre-conversion data serving as a predetermined transfer unit, and then even-numbered bits are transferred.

  In such a case, for example, even if “0xF4EB” is determined as a test pattern and code conversion is performed, post-conversion data having a predetermined bit arrangement order cannot be transferred. Since the equivalence continuous data generated by code conversion by flowing the test pattern is meaningful in the bit string, the basic pattern is retransmitted so that the bit transfer sequence having the basic pattern having the desired number of equivalence continuations is serially transferred. Deploy.

For example, in the basic pattern “0xF4EB”, when the big endian method is used as an example of the byte order method, the bit string of the data before conversion is “1111 0100 1110 1011”.
Assuming that the odd-numbered bits flow first and the even-numbered bits flow later as the byte transfer order method, the basic pattern in this case changes to “0xE9CF”.

  FIG. 13 is an explanatory diagram of the test pattern “0xF4EB” after the bit transfer order control. For this reason, when the bit transfer order control is performed with the odd bits first and the even bits later, if “0xE9CF” in FIG. A certain “0xF4EB” is obtained, which can be converted into post-conversion data having the same number of continuous values of RL = 5 at the boundary by 8b / 10b code conversion and serially transferred.

  FIG. 13 shows an odd-numbered bit and an even-numbered bit separately arranged in the bit arrangement of the basic pattern “F4EB”. The odd-numbered bit becomes “0xE9” as 8-bit data, and the even-numbered bit becomes “0xCF”. For such a rearrangement basic pattern “0xE9CF”, if bit order control is performed and odd bits are transferred first and even bits are transferred later, “0xF4” is obtained by odd bit transfer, “0xEB” is obtained in the transfer. That is, when the rearranged basic pattern “0xE9CF” is sent through the bit transfer order control as the pre-conversion data, the original basic pattern “F4EB” is obtained, and this can be subjected to 8b / 10b code conversion.

  Finally, consideration of the number of transfer channels when determining the basic pattern will be described. FIG. 14 is an explanatory diagram of problems when the basic pattern “0xF4EB” is continuously transferred without considering the number of serial transfer channels. In FIG. 14, since the input FIFO 68 has a bit storage position for the input data as shown in FIG. 7, when “0xF4EB” is continuously input as input data as it is, the storage state in the input FIFO 68 is shown in the figure. Thus, if this is distributed to the serial transfer channels 75-1 to 75-4, the basic pattern "0xF4EB" cannot be flowed.

  Therefore, as shown in FIG. 15, the basic pattern “F4EB” is rearranged into “F4F4F4F4EBEBEBEB” and written repeatedly in the input FIFO 68 in consideration of the number of transfer channels of four channels. With writing by such rearrangement, the basic pattern “F4EB” can be continuously flowed in parallel to the serial transfer channels 75-1 to 75-4.

  FIG. 16 is a flowchart showing a basic processing procedure of test data creation processing in the embodiment of FIG. In FIG. 16, the test data creation process determines a basic pattern from the code conversion table in step S1. For example, in the case of 8b / 10b code conversion, the basic pattern is determined from the code conversion table shown in FIG.

  If the basic pattern is determined, the basic pattern is reset in step S2 in consideration of the bit order of the high-speed serial transfer device. In step S3, the basic pattern is rearranged in consideration of the bit transfer order and the number of transfer channels so that the basic pattern flows in each channel of the high-speed serial transfer device, and a final test pattern is generated.

  FIG. 17 is a flowchart of the basic pattern creation process in step S1 of FIG. Here, the basic pattern creation process will be described with reference to the 8b / 10b code conversion table 28 of FIG.

  First, in step S1, a specified run length, which is a desired number of consecutive equivalences required for creating a test pattern, and a maximum RL in one conversion unit are read. As the designated run length, RL = 5, which is the maximum RL in use, is designated as shown in the code conversion management table 18 of FIG. It can be seen from the code management table 18 of FIG. 3 that the maximum RL within one conversion unit is maximum RL = 4.

  In step S2, the designated RL is compared with the maximum RL in one conversion unit. In this case, since the designated RL = 5 and the maximum RL = 4 within one conversion unit, the process proceeds to step S4, and a combination having a run length satisfying the designated RL is searched by combining two units of conversion data. As a result of this search, in this embodiment, for example, “0xF4EB” can be searched as a basic pattern.

  On the other hand, if the maximum RL in one unit of conversion is larger than the designated RL in step S2, the process proceeds to step S3, and the post-conversion data satisfying the designated RL with the run length RL that is the number of consecutive equivalents in one unit is searched. To obtain the pre-conversion data. Subsequently, in step S5, the pre-conversion data consisting of a combination of one unit or two units that can be searched is stored as a basic pattern. In step S6, the saved search results are displayed, and the operator selects one necessary basic pattern from them.

  FIG. 18 is a flowchart of a process for generating a test pattern by combining two units of conversion data in step S4 of FIG. In FIG. 18, a test pattern is generated by combining two units of conversion data. In step S1, for example, an 8b / 10b code conversion table is converted into a group with RD change and a group without RD change depending on whether or not running / disparity conversion is exchanged. To separate. That is, the number of bits 0 and 1 is obtained for 10-bit data as converted data, and if the number is the same, it is separated into a group without RD change, and if it is different, it is separated into a group with RD change.

  Subsequently, in step S2, a process of searching for and generating a basic pattern corresponding to cases 1 to 4 in FIG. 12 is executed. Subsequently, in step S3, a process of searching for a basic pattern corresponding to cases 5 and 6 in FIG. 12 and generating a basic pattern is executed. In step S4, a process for searching for and generating basic patterns corresponding to cases 7 and 8 in FIG. 12 is executed.

  19 and 20 are flowcharts of the generation processing of cases 1 to 4 in step S2 of FIG. In FIG. 19, first, basic pattern generation processing in case 1 is performed in steps S1 to S4. In the generation process of case 1 of step S1, data X having a unique maximum equivalence number from the j side, which is the last 4 bits of 10 bits in the RD + conversion table classified into the group with RD change in step S2, is stored. Extract. In the case of 8b / 10b, the inherent maximum number of consecutive equivalences on the j side is the maximum number of consecutive equivalences = 3 from the code conversion management table 18 of FIG.

Next, in step S3, (specified RL-j side specific maximum equivalence number of consecutive numbers) from the a side in the RD-conversion table in the same RD changing group (= specified RL-j side continuous number) = 5-3 = 2
Data Y having the same number of continuous values is extracted. Then, in step S4, the extracted data XY are combined, and the combination data having the same number of consecutive equivalences at the boundary and the specified run length RL = 5 are selected and stored.

  Steps S5 to S8 are case 2 basic pattern generation processing. In step S6, data X having the maximum number of consecutive equivalence values 3 is extracted from the j side in the RD-conversion table of the RD change group. In the RD + conversion table of the non-change group, data Y having the same equivalence number 2 obtained by subtracting the maximum equivalence number 3 on the j side from the specified RL is extracted, and the extracted data XY are combined in step S3, and the same value is continued at the boundary. The combination data whose number is designated RL = 5 is selected and saved.

  Steps S9 to S12 in FIG. 20 are basic data generation processing of case 3. In step S10, data X having the maximum number of consecutive equivalence values 3 is extracted from the j side in the RD + conversion table of the RD unchanged group in step S10. In step RD, the data Y having the number of consecutive equivalences 2 obtained by subtracting the j-side inherent maximum number of equivalences 3 from the specified RL is extracted from the a side of the RD + conversion table of the group with RD change. Combination data with the same number of consecutive equivalences being designated RL = 5 is selected and saved.

  Further, steps S13 to S16 in FIG. 20 are the generation process of case 4. In step S14, data X having the maximum number of consecutive equivalence values 3 is extracted from the j side in the RD-conversion table of the group without RD change. In step RD, the data Y having the same number of consecutive continuations 2 is extracted from the a side of the RD-conversion table of the group with RD change, the extracted data XY is combined in step S14, and the combination having the same number of continuous continuations at the boundary becomes RL = 5 Select and save the data.

  21 and 22 are flowcharts of the generation processing of cases 5 and 6 in step S3 of FIG. In FIG. 21, first, in steps S1 to S4, test pattern generation processing by the big endian method in case 5 is executed. Of course, the generation processing of cases 5 and 6 is performed for the group with RD change.

First, in step S2, data X having a unique maximum equivalence number is extracted from the a side in the RD + conversion table. In the case of 8b / 10b code conversion, the maximum number of consecutive equivalences on the a side is 3. Next, in step S3, in the RD-conversion table, an equivalence sequence obtained by subtracting the maximum equivalence sequence 3 on the a side in step S2 from the designated run length RL from the j side, in this case (specified RL)- (A side maximum equivalence number of consecutive) = 5-3 = 2
Data Y having the same number of continuous values is extracted. In step S4, the extracted data X and Y are combined, and the combination data having the same number of consecutive equivalences at the boundary is selected and stored.

  Next, in steps S5 to S8, generation processing by the little endian method is executed for the same case 5. In the case of the little endian method, in step S6, the data X having the maximum equivalence number 3 is extracted from the j side in the RD + conversion table, and the data having the remaining equivalence number 2 for the specified run length RL is extracted in step S7. The data is extracted from the a side of the RD-conversion table, and both are combined in step S8, and the combination data in which the number of consecutive equivalent values is the specified run length RL = 5 is selected and stored at the boundary.

  Similarly to the case 5 process, the generation process by the big endian method is performed for the case 6 in steps S9 to S12, and the generation process by the little endian method is executed by steps S13 to S16.

  23 and 24 are flowcharts of the generation processing of cases 7 and 8 in step S4 of FIG. In the generation process of cases 7 and 8, the generation process is executed for the group without RD change.

  Steps S1 to S4 are generation processing according to the big endian method of case 7, in which data X having the maximum number of consecutive equivalences 3 from the a side in the RD + conversion table is extracted in step S2, and the specified RL = 5 in step S3 Data Y having the remaining equivalence number 2 is extracted from the j side in the RD + conversion table. Then, in step S4, the extracted data XY are combined, and the combination data having the same number of consecutive equivalences at the boundary RL = 5 is selected and stored.

  Next, generation processing by the little endian method of case 7 is performed in steps S5 to S8. In the generation process using the little endian method, in step S6, data X having the maximum number of consecutive equivalences 3 is extracted from the j side in the RD + conversion table, and in step S7, the specified RL is converted from the specified RL to the j side. Data Y having the remaining number of equivalence continuations 2 minus the number of equivalence continuations is extracted. Then, in step S8, the extracted data XY are combined, and the combination data having the same number of consecutive equivalences at the boundary RL = 5 is selected and stored.

  Next, steps S9 to S12 in FIG. 24 are generation processing by the big endian method of case 8, and steps S13 to S16 are generation processing by the little endian method of the same case 8.

  FIG. 25 is an explanatory diagram of a test method for verifying loss of synchronization according to the present invention using the test pattern created in the embodiment of FIG. In FIG. 25, the test target device is a network device 134 such as a router, for example, and function boards 136-1 to 136-n for executing communication processing with the network 144 are arranged in the network device 134. The high-speed serial transfer devices 62-1 to 62-n are used as interfaces for connecting the function boards 136-1 to 136-n.

  In other words, the function board 136-1 is provided with a packet transmission unit 140 implemented by a processor, and communicates with the network 144 via the function boards 136-2 to 136-n.

  For the test using the test pattern of the present invention, a test pattern storage unit 138 is provided on the functional board 136-1, and the test pattern created by the embodiment of FIG. 1 is stored. The test pattern from the test pattern storage unit 138 is continuously sent as a packet payload in the packet transmission unit 140 to the test pattern transfer path 142 that reciprocates through the high-speed serial transfer devices 62-1 to 62-n.

  Since the transfer throughput of the test pattern in this case affects the detection effect of the out-of-synchronization failure, it is desirable to transfer at the highest possible throughput. Also, the longer the test pattern, the better. In network devices such as routers, the NTU is determined according to the type of network, but the test pattern is transferred multiple times in units of NTU.

  FIG. 26 is an explanatory diagram of another test method using the test pattern created in the embodiment of FIG. In this test method, a test packet is created from a test pattern stored in the test pattern storage unit 138 by an external measuring instrument 148, transferred to the test target apparatus 146, and provided in the test target apparatus 146. A test pattern having continuous repetition of the same value based on the test packet is serially transferred between the high-speed serial transfer devices 62-1 and 62-2.

  FIG. 27 is a block diagram of another embodiment of the present invention for generating a test pattern for performing all code conversion of RD-conversion and RD + conversion of a code conversion table provided in a high-speed serial transfer device.

  In FIG. 27, the test data creation device 152 newly adds a code conversion function test data generation unit in addition to the test pattern creation unit 10-1 that creates a test pattern for verifying a failure such as loss of synchronization shown in FIG. 1. 156 is provided, and accordingly, an RD switching data designation unit 154 and a code conversion function test pattern storage unit 158 are provided. The other constituent functions are the same as those in the embodiment of FIG.

  The code conversion function test data generation unit 156 transfers data converted by all code conversions of the RD− conversion and the RD + conversion of the code conversion table to each of the plurality of serial transfer channels of the high-speed serial transfer device. Then, create a test pattern in which the pre-conversion data is arranged.

  The code conversion function test data generation unit 156 is provided with a group classification unit 160 and a data arrangement unit 162. The group classification unit 160 classifies the code conversion table into a group without RD change and a group with RD change. The group with RD change is data in which the number of bits 0 and 1 of the converted data is the same, and the running disparity RD of the subsequent converted data is not changed. The data in the group with RD change is data in which the number of bits 0 and 1 of the converted data is different and the running disparity RD of the subsequent converted data is changed.

  The data placement unit 162 forms the first group by arranging the data before conversion of the group without RD change by one unit, and then arranges the same data of the data before conversion of the group without RD change by two units. Then, the second group is formed, and then, only one unit of predetermined data before conversion belonging to the group without RD change is arranged to form the third group, and further, each data before conversion of the group without RD change is set to one unit. The fourth group is formed by arranging them one by one, thereby generating a test pattern.

  The code conversion function test pattern generated by the code conversion function test data generation unit 156 is such that the basic pattern rearrangement unit 26 transfers all converted data to each channel according to the number of channels used in the high-speed serial transfer device. After the test pattern rearrangement, the test pattern rearrangement is finally stored in the code conversion function test pattern storage unit 158.

  The embodiment in FIG. 27 is an example in which the embodiment of FIG. 1 is combined with the embodiment in FIG. 1, but a dedicated apparatus for generating a test pattern for performing all code conversions of RD-conversion and RD + conversion of the code conversion table. It is good. This dedicated device is a device excluding the configuration of FIG. 1 from FIG. 27, but the basic pattern rearrangement unit 26 remains.

  The necessity of the code conversion function test according to FIG. 27 will be described as follows. In the high-speed serial transfer device, for example, 8-bit data in one conversion unit is subjected to RD-conversion or RD + conversion according to the RD value of the immediately previous converted data, and the converted data is serially transferred. Which of the two types of RD− conversion or RD + conversion is used depends on the RD value at the time of transferring the data. This RD value changes with the difference in the number of bits 0 and 1 of the data flowing through the transfer channel.

  Considering that various data flows before the test pattern is transferred to the high-speed serial transfer device, it is usually necessary to know exactly whether RD + conversion or RD- conversion occurs when the test data is flowed. Is very difficult. Therefore, in the case of the above-described test pattern for verifying out-of-synchronization, a test pattern that generates a target run length value, for example, RL = 5, is generated.

  When data of one conversion unit is transferred by a high-speed serial transfer device, if there is a difference in the number of bits 0 and 1, the next transfer data is the reverse conversion of the previous one, for example, if the previous is RD +/- conversion, the next transfer data Is the same conversion if there is no difference in number, for example, if the previous RD +/− conversion, the next transfer data is RD +/− conversion.

  Therefore, if the data after the code conversion having a difference in the number of bits 0 and 1 is added to the basic pattern, the RD value can be forcibly changed by the additional data.

  For example, when the combination data of data X and Y is cyclically transferred as “XYXYXY...”, The state of change of the RD value is as shown in FIG.

  In FIG. 28, the state of the change in the RD value is shown separately for cases 1 to 8, which is the same as FIG. FIG. 28 shows a problem with respect to the appearance of RL = 5 that gives the maximum number of consecutive equivalences for cases 1 to 8.

  In cases 1 to 4 of FIG. 28, for example, when RL = 5 is obtained at the boundary between data X and Y by 8b / 10b code conversion, when data XY is cyclically transferred, RD-conversion and RD + conversion are performed. Regardless of which conversion is performed, one RL = 1 is always obtained in 4 bytes.

  However, in cases 5 to 8, no RL = 5 can be obtained under the illustrated conditions. Therefore, by adding data Z for forcibly changing the RL value after code conversion to cases 5 to 8 to obtain data XYZ, the problem that RL = 5 does not appear is solved.

FIG. 29 shows how the RD value changes in cyclic transfer when data Z for forcibly changing the RL value is added for cases 5 to 8 in FIG. In this case, for example, X = 0xF4 as the data XYZ
Y = 0xEB
Z = 0xFC
Is used.

  The concept of forcibly adding data to which RD values are added in this way is the test pattern for executing all table conversions of RD + conversion and RD- conversion in the code conversion table by the code conversion function test data generation unit 156 of FIG. It can be applied to the process of creating.

  For example, as apparent from the 8b / 10b code conversion table 28 shown in FIG. 4, there are two types of conversion data, RD + conversion and RD− conversion, for 256 types of input 8-bit data, and therefore 256 × 2 = 512. It is necessary to create a test pattern that continuously executes all 512 conversions.

Here, the 8b / 10b code conversion table can be classified into the following two types.
(1) RD change-free group in which the number of bits 0 and 1 is equal and the RD value does not change in the data after 10b conversion (2) In the data after 10b conversion, the RD value changes due to the difference in the number of bits 0 and 1 RD change group (123 species)

Therefore, in order to create a test pattern for realizing the full conversion of the code conversion table, the data of 133 types of RD change-free groups and 123 types of RD value change groups are arranged as shown in FIG. The arrangement according to the table classification in FIG. 30 follows the following procedure.
(1) 133 types belonging to the RD value unchanged group are arranged one by one to form a group G1.
(2) 123 types belonging to the group with RD value change are arranged in units of 2 units to form a group G2.
(3) For switching the RD value, one piece of data belonging to the group with RD change is selected and arranged as a group G3.
(4) 133 types belonging to the RD value unchanged group are arranged one by one to form a group G4.

  The table classification of FIG. 30 according to this procedure will be specifically described as follows. FIG. 30 shows the classification conversion table 164-1 for the immediately previous RD + and the classification conversion table 164-2 for the immediately previous RD-, which are divided into two.

  For example, in the classification conversion table 164-1, according to the above (1) to (4), 133 types of groups without RD change are arranged one unit at a time as the group G1, and in this case, the immediately preceding RD value is RD +. , The RD values of the group G1 are all RD +.

  Subsequently, in the group G2, the same 8-bit data from the group with RD change is arranged in units of 2 units. For example, 8-bit data “0x03” is arranged as “0x0303”, and two converted data “RD + conversion data” and “RD-conversion data” are arranged.

  In the next group G3, one of the data in the group G2, for example, “0xFC” is arranged. Since “0xFC” has an RD switching function and RD1 of the last converted data of the group G2 is “RD−”, “RD +” is arranged as the group G3, and the group G4 as the next group G4 The same pre-conversion data as G1 is arranged so that the remaining “RD−” is converted with respect to “RD +” that has already been converted.

  The classification conversion table 164-2 is a case where the immediately previous RD value is “RD−”. In this case, the group G4 in the classification conversion table 164-1 becomes the group G1, and the group G1 is replaced with the group G4. The RD value in “0xFC” for switching the RD value of the group G3 is “RD−” because the last of the group G2 is “RD +”, and the first RD value of the group G4 is “RD +” by switching. It is trying to become.

  As is clear from the classification conversion tables 164-1 and 164-2 as shown in FIG. 30, all the conversions of the RD + conversion and the RD- conversion of the 8b / 10b code conversion table 28 are related to the RD value immediately before. As test data for performing conversion using all of them, 8-bit data as input data arranged in groups G1, G2, G3, and G4 as input data in the classification conversion tables 164-1 and 164-2 are arranged. What is necessary is just to create the test pattern with a line.

  FIG. 31A shows an 8-bit test data string 168 that performs all the conversion of the code conversion table created based on FIG. 30, in which 133 pieces of 8-bit data 170 having no RD value change are arranged, and then the RD value Changed 8-bit data 172 is arranged in units of 128 by two, and a total of 246 are arranged, followed by RD switching data Z, that is, one of the data belonging to the group without RD change, and then no RD value change 8 133 bit data 176 are arranged in the same manner as the head portion.

  When the 8-bit test data sequence 168 of FIG. 31A is passed through a high-speed serial transfer device using the 8b / 10b code conversion table, if the RD value immediately before the test is “RD +”, RD conversion like 31 (B), that is, conversion using the classification conversion table 164-1 of FIG. 29 is performed. If the RD value immediately before the test data is “RD−”, conversion using all RD− and RD + in FIG. 31C is performed. This is the same as using the classification conversion table 164-2 of FIG.

  FIG. 32 shows table areas corresponding to the groups G1 to G4 in the 8b / 10b code conversion table 28, and the table contents are divided into a group without RD change and a group with RD change for the sake of simplicity. As is apparent from the group area in this table, a test using all conversions of the 8b / 10b code conversion table, that is, all RD− conversion and RD + conversion can be performed by outputting test data once.

  FIG. 33 is a flowchart of the data creation process of the code conversion function test in the embodiment of FIG. In FIG. 33, the target code conversion table is classified into a group without RD change and a group with RD change in step S1, and then in step S2, RD + conversion for pre-conversion data (8-bit data) belonging to the group without RD change is performed. Data is arranged as a first group.

  Subsequently, in step S3, RD-converted data and RD + converted data for the same two pre-conversion data (8-bit data) belonging to the RD no-change group are arranged as a second group in succession by 2 bytes. Subsequently, in step S4, pre-conversion data (8-bit data) for RD switching and RD + post-conversion data are arranged as a third group. Subsequently, in step S5, the RD-converted data for the pre-conversion data (8-bit data) belonging to the same RD unchanged group as in step S2 is arranged as the fourth group.

  Finally, in step S6, rearrangement is performed so that patterns of all groups flow in each channel of the high-speed serial transfer device, and a test pattern is created.

  As for the function test using the test pattern for the code conversion function test created in this way, as shown in FIG. 25 or FIG. 26, the test pattern is stored in the test pattern storage unit 138, and the test pattern is stored in the payload. Is generated and sent to the high-speed serial transfer device, and a function test using all the conversions of the RD + conversion and the RD- conversion of the code conversion table can be performed.

  Further, the present invention provides a program for generating test data to be tested focusing on the out-of-synchronization and code conversion function tests of the high-speed serial transfer device. 24 has the contents of the flowchart of FIG. 33 and the creation of the test pattern for the code conversion function test has the contents of the flowchart of FIG.

In the above embodiment, the 8b / 10b code conversion is taken as an example. However, the present invention can be applied to other code conversions as they are. The present invention can be applied as appropriate without impairing its object and advantages. It includes modifications and is not limited by the numerical values shown in the above embodiment.

Here, the features of the present invention are enumerated as follows.
(Appendix)

(Appendix 1)
Test pattern creation that creates a test pattern in which pre-conversion data is arranged so that the same value of bit 0 or 1 is continuously transferred to each of a plurality of serial transfer channels of a high-speed serial transfer device using the converted data by the code conversion table Steps,
A test step of inputting the test pattern into a high-speed serial transfer device on the transmission side to perform code conversion, continuously transferring the converted data so as to pass through the serial transfer channel, and verifying a loss of synchronization failure on the reception side;
A high-speed serial transfer device test method characterized by comprising: (1)

(Appendix 2)
In the high-speed serial transfer device test method described in Appendix 1,
The test pattern creation step
A basic pattern setting step for setting a basic pattern based on a byte order system and a running disparity of code conversion in the high-speed serial transfer device;
A basic pattern resetting step for resetting the basic pattern in accordance with a channel use method of a bit transfer order in the high-speed serial transfer device;
A basic pattern rearrangement step for rearranging the basic pattern so that the basic pattern is transferred to each channel according to the channel use method including the bit transfer order and the number of used channels in the high-speed serial transfer device;
A high-speed serial transfer device test method characterized by comprising: (2)

(Appendix 3)
In the high-speed serial transfer device test method described in Appendix 2,
The code conversion table used for code conversion in the high-speed serial transfer device converts m-bit data of one conversion unit into n-bit data having a large number of bits, and the converted data has RD + conversion in which running disparity becomes positive. And an m-bit / n-bit code conversion table for performing two conversions of RD-conversion in which running disparity is negative,
The basic pattern setting step includes:
Determining whether or not the converted data in one unit of conversion in the m-bit / n-bit code conversion table includes the same number of consecutive consecutive bits 0 or 1 having a specified run length or more;
A unit test pattern extraction step for extracting, as a test pattern, pre-conversion data that satisfies the specified run length within one unit of the converted data when the number of consecutive equivalences greater than or equal to the specified run length is included;
2-unit test pattern extraction that extracts 2 units of pre-conversion data that satisfies the specified run length at the boundary portion combining the 2 units of the converted data as test patterns when the number of consecutive equivalences greater than the specified run length is not included Steps,
A high-speed serial transfer device test method characterized by comprising:

(Appendix 4)
In the high-speed serial transfer device test method according to attachment 3, the 2 unit test pattern extraction step includes:
Two units of pre-conversion data are (X) and (Y), post-conversion data of data (X) is (X: RD−) and (X: RD +), and post-conversion data of data Y is (Y: RD -) And (Y: RD +)
Changes in the running disparity value RD of the converted data in the data stream (XYXYXYXY... XY) in which the two units of pre-conversion data (XY) are cyclically transferred continuously,
(1) Running disparity of the converted data stream when the number of bits 0 and 1 of the converted data of the data X is different and the number of bits 0 and 1 of the converted data of the data Y is the same number Changes in (X: RD +) (Y: RD-) (X: RD-) (Y: RD +)
The first case that repeats
(2) Running disparity of the converted data stream when the number of bits 0 and 1 of the converted data of the data X is different and the number of bits 0 and 1 of the converted data of the data Y is the same number Changes in (X: RD-) (Y: RD +) (X: RD +) (Y: RD-)
The second case, which repeats
(3) The running disparity of the converted data stream when the number of bits 0 and 1 of the converted data of data X is the same and the number of bits 0 and 1 of the converted data of data Y is different Change is (X: RD +) (Y: RD +) (X: RD-) (Y: RD-)
The third case that repeats
(4) The running disparity of the converted data stream when the number of bits 0 and 1 of the converted data of data X is the same and the number of bits 0 and 1 of the converted data of data Y is different Change is (X: RD-) (Y: RD-) (X: RD +) (Y: RD +)
The fourth case that repeats
(5) Changes in running disparity of the converted data stream when the number of bits 0 and 1 of the converted data of data X and Y are different (X: RD +) (Y: RD-)
The fifth case that repeats
(6) The change in running disparity of the converted data stream when the number of bits 0 and 1 of the converted data X and Y is different is (X: RD−) (Y: RD +)
The sixth case, which is a repetition of
(7) Changes in running disparity of the converted data stream when the number of bits 0 and 1 of the converted data of data X and Y are the same (X: RD +) (Y: RD +)
The seventh case, which repeats
(8) Changes in running disparity of the converted data stream when the number of bits 0 and 1 of the converted data of data X and Y are the same (X: RD−) (Y: RD−)
The 8th case,
A high-speed serial transfer device test method, wherein two units of pre-conversion data satisfying the specified run length at the boundary portion are extracted as test patterns.

(Appendix 5)
The high-speed serial transfer device test method according to appendix 3, wherein the two-unit test pattern extraction step includes a first byte order method (little endian method) that takes a bit arrangement having a termination in the high-speed serial transfer device as a lower bit. 2 units of pre-conversion data satisfying the specified run length at the boundary of 2 units of conversion data corresponding to each of the second byte order system (big endian system) taking a bit arrangement with the end as the upper bits Is extracted as a test pattern. A high-speed serial transfer device test method.

(Appendix 6)
In the high-speed serial transfer device test method described in Appendix 3,
When the high-speed serial transfer device has an 8-bit / 10-bit code conversion table for code conversion, the 2-unit test pattern extraction step is XY = F4EB or EBF4 in hexadecimal notation as a basic pattern.
A method of testing a high-speed serial transfer device, characterized by:

(Appendix 7)
In the high-speed serial transfer device test method according to appendix 2, the basic pattern resetting step includes: transferring post-transfer data according to bit transfer order control for determining a transfer order in an odd bit and an even bit in the high-speed serial transfer device; A high-speed serial transfer device test method, wherein the basic pattern is reset to data before bit transfer order control so that the basic pattern satisfies the specified run length.

(Appendix 8)
The high-speed serial transfer device test method according to appendix 7, wherein the basic pattern resetting step is a two-unit test pattern extraction step in which a hexadecimal pattern is generated as a basic pattern from the 8-bit / 10-bit code conversion table of the high-speed serial transfer device. XY = F4EB or XY = EBF4 on display
, XY = E9CF or XY = CFE9 in hexadecimal notation as the reset basic pattern from the basic pattern in accordance with the bit transfer order control in which the odd bit is transferred first and then the even bit is transferred.
A high-speed serial transfer device test method characterized by re-setting.

(Appendix 9)
In the high-speed serial transfer device test method according to appendix 2, the basic pattern rearrangement step includes one unit of basic pattern (X) or two units of basic pattern (XY) by the number of channels in the high-speed serial transfer device. A high-speed serial transfer device test method, wherein basic patterns are rearranged so as to be continuous.

(Appendix 10)
In the high-speed serial transfer device test method according to appendix 9, the basic pattern rearranging step arranges one unit of basic pattern (X) in repetition of basic pattern (XXXX) when the high-speed serial transfer device has four channels. A high-speed serial transfer device test method characterized in that the basic pattern (XY) of two units is rearranged into a repetition of the basic pattern (XXXXYYYY).

(Appendix 11)
The high-speed serial transfer device test method according to appendix 9, wherein the basic pattern resetting step is a two-unit test pattern extraction step in which a hexadecimal pattern is generated as a basic pattern from the 8-bit / 10-bit code conversion table of the high-speed serial transfer device. (F4EB) or (EBF4) on the display
And the basic pattern is rearranged to repeat (F4F4F4F4EBEBEBEBEB) or (EBEBEBEBEBF4F4F4F4) when the high-speed serial transfer device has four channels.

(Appendix 12)
A test pattern creation step for creating a test pattern in which pre-conversion data is arranged so that all post-conversion data stored in the code conversion table is continuously transferred to each of a plurality of serial transfer channels of the high-speed serial transfer device When,
The test pattern is input to the high-speed serial transfer device on the transmission side for code conversion, and all the converted data in the code conversion table is continuously transferred so as to pass through the serial transfer channel to verify the function on the reception side. Testing steps;
A high-speed serial transfer device test method characterized by comprising: (3)

(Appendix 13)
In the high-speed serial transfer device test method according to appendix 12, the test pattern creation step includes:
In the code conversion table, the number of bits 0 and 1 of the converted data is the same, and there is no RD change group that does not change the running disparity of the subsequent converted data, and the number of bits 0 and 1 of the converted data. A group classification step for classifying into a group with RD change that changes the running disparity of the converted data that is different from each other and changes,
The data before conversion of the group without RD change is arranged by one unit to form a first group, and then the same data of the data before conversion of the group with RD change is arranged by two units to arrange the second group. Next, only one unit of predetermined data before conversion belonging to the group with RD change is arranged to form a third group, and each data before conversion of the group without RD is arranged one unit at a time. A data placement step for creating a test pattern by forming a group;
A test pattern rearranging step for rearranging the test patterns so that all converted data is transferred to each channel according to the number of channels used in the high-speed serial transfer device;
A high-speed serial transfer device test method characterized by comprising: (3)

(Appendix 14)
In the high-speed serial transfer device test method according to appendix 12, when the code conversion table is an 8-bit / 10-bit code conversion table,
In the group classification step, the 8-bit / 10-bit code conversion table is classified into 133 types of RD-changeless groups and 123 types of RD-change groups.
In the data arrangement step, 133 types of 8-bit data of the group without RD change are arranged one unit at a time to form a first group, and then 123 types of 8-bit data of the group with RD change are set to 2 A unit is arranged to form a second group, and then a predetermined group of 8-bit data belonging to the group with RD change is arranged in one unit to form a third group, and each of 133 types of groups without RD A test method for a high-speed serial transfer device, characterized in that a test pattern is generated by arranging a fourth group by arranging 8-bit data one by one.

(Appendix 15)
The high-speed serial transfer device test method according to appendix 12, wherein the test pattern rearrangement step is performed by converting one unit of pre-conversion pattern (X) or two units of pre-conversion pattern (XX) to the number of channels in the high-speed serial transfer device. A high-speed serial transfer device test method, wherein one unit pattern is rearranged by as much as possible.

(Appendix 16))
On the computer,
A designation information input step for reading the designation information of the conversion method of the code conversion table of the high-speed serial conversion device and the run length designation information for continuously transferring the same value of bit 0 or 1 in the data after conversion by the code conversion table;
A test pattern in which pre-conversion data is arranged so that the same value of bit 0 or 1 of the specified run length is continuously transferred to each of a plurality of serial transfer channels of a high-speed serial transfer device using post-conversion data according to the code conversion table Creating a test pattern,
A test data creation program characterized in that

(Appendix 17)
In the test data creation program described in Appendix 16,
The test pattern creation step
A basic pattern setting step for setting a basic pattern based on a byte order system and a code conversion RD value in the high-speed serial transfer device;
A basic pattern resetting step for resetting the basic pattern in accordance with a channel use method of a bit transfer order in the high-speed serial transfer device;
A basic pattern rearrangement step for rearranging the basic pattern so that the basic pattern is transferred to each channel according to the channel use method including the bit transfer order and the number of used channels in the high-speed serial transfer device;
A test data creation program characterized by comprising: (4)

(Appendix 18)
On the computer,
A designation information input step for reading designation information of the conversion method of the code conversion table of the high-speed serial conversion device;
Test data creation that creates a test pattern in which pre-conversion data is arranged so that all post-conversion data stored in the code conversion table is continuously transferred to each of a plurality of serial transfer channels of a high-speed serial transfer device Steps,
A test pattern rearranging step for rearranging the test patterns so that all converted data is transferred to each channel according to the number of channels used in the high-speed serial transfer device;
A test data creation program characterized in that

(Appendix 19)
A designation information input section for reading the designation information of the conversion method of the code conversion table of the high-speed serial conversion device, and the run length designation information for continuously transferring the same value of bit 0 or 1 with the converted data by the code conversion table;
A test pattern in which pre-conversion data is arranged so that the same value of bit 0 or 1 of the specified run length is continuously transferred to each of a plurality of serial transfer channels of a high-speed serial transfer device using post-conversion data according to the code conversion table A test pattern creation section for creating
A test data creation device characterized by comprising: (5)

(Appendix 20)
A designation information input unit that reads designation information of a conversion method of a code conversion table of a high-speed serial conversion device;
Test data creation that creates test data in which pre-conversion data is arranged so that all the converted data stored in the code conversion table is continuously transferred to each of the plurality of serial transfer channels of the high-speed serial transfer device And
A test data rearrangement unit for rearranging so that the data after all conversion is transferred to each channel according to the number of channels used in the high-speed serial transfer device;
A test data creation device characterized by comprising:

10: Test pattern creation unit 12: Run length designation unit 14: Code conversion method designation unit 16: Code conversion table 18: Code conversion management tables 20, 138, 150: Test pattern storage unit 22: Basic pattern setting unit 24: Basic pattern Reset unit 26: basic pattern rearrangement unit 28: 8b / 10b code conversion table 30: code group name 32: octet value 34: octet bit 36: RD-conversion data 38: RD + conversion data 42: CPU
44: Bus 46: RAM
48: ROM
50: hard disk drive 52: device interface 54: keyboard 56: mouse 58: display 60: network adapters 62-1 to 62-n: high-speed serial transfer devices 64-1, 64-2: transmission units 65-1, 65-2 : 4-channel serial transfer path 66-1, 66-2: Receiver 68: Input FIFO
70-1 to 70-4: 8/10 encoders 72-1 to 72-4: SP converters 74-1 to 74-4: Drivers 75-1 to 75-4: Serial transfer channel 76, 80: PLL circuit 78 -1 to 78-4: Receivers 82-1 to 82-4: SP converters 84-1 to 84-4: 8/10 decoder 86: Output FIFO
88-1 to 88-4: Interleavers 90-1 to 90-4: 8b / 10b conversion circuit 92: Register 94: RD- 8b / 10b conversion table 96: RD + 8b / 10b conversion table 98: Selector 100: RD Determination unit 102: boundary equivalence continuous pattern list 104: data boundaries 106, 108, 114-1, 114-2, 116-1, 116-2: post-conversion data 110, 112, 118-1, 118-2, 120- 1, 12-2: Equivalent area 122: 2-unit cyclic pattern RD change list 134: System 136-1 to 136-n: Function board 140: Packet transmission unit 142: Test pattern transfer path 144: Network 146: Test target device 148: Measuring instrument 152: Test data creation device 154: RD switching data designation unit 156: Code conversion Tolerance test data creation unit 158: code conversion function test pattern storage unit

Claims (1)

A test pattern creation step for creating a test pattern in which pre-conversion data is arranged so that all post-conversion data stored in the code conversion table is continuously transferred to each of a plurality of serial transfer channels of the high-speed serial transfer device When,
The test pattern is input to the high-speed serial transfer device on the transmission side for code conversion, and all the converted data in the code conversion table is continuously transferred so as to pass through the serial transfer channel to verify the function on the reception side. Testing steps;
With
The test pattern creation step includes
A basic pattern setting step of setting a basic pattern based on the high-speed serial transfer byte ordering scheme in the device and code conversion run two ring disparity,
A basic pattern resetting step of resetting the basic pattern to suit the high-speed serial transfer channel usage method of the bit transmission order in the device,
A basic pattern rearranging step of rearranging to basic pattern is transferred to each channel in accordance with the channel usage, including the high-speed serial transfer bits transferred order and use the channel in the device,
A high-speed serial transfer device test method characterized by comprising:

Images