JP5832800B2 - Semiconductor integrated circuit and test method for semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit and a method for testing a semiconductor integrated circuit.

  Some semiconductor integrated circuits have a plurality of mega macros having the same circuit configuration. As such a macro macro, for example, a parallel-serial converter that converts a parallel signal into a serial signal and an A / D converter that converts an analog signal into a digital signal are known (see, for example, cited document 1). .

  A semiconductor integrated circuit is subjected to a test for detecting a circuit abnormality caused by a defect in circuit formation or a defect in design after manufacture.

  For example, in Cited Document 1, in a semiconductor integrated circuit equipped with a plurality of A / D converters that are mega macros of the same configuration, test signals are simultaneously input to these mega macros, and output signals from a plurality of mega macros are A configuration including a circuit for comparing the two and outputting the comparison result is shown.

  In the test of the semiconductor integrated circuit provided with a plurality of parallel-serial conversion circuits by applying the technique shown in the cited document 1, the same test signal is simultaneously input to the plurality of parallel-serial conversion circuits. A method is conceivable in which the output signals are compared with each other and if they do not match, it is determined as defective. However, in this case, if an error occurs in the processing of a bit at a specific position due to an error in the design of the original parallel-serial conversion circuit, the output signals of multiple parallel-serial conversion circuits in the semiconductor integrated circuit are incorrect. Matches. For this reason, a defect cannot be detected even if the output signals are compared.

  Therefore, it is conceivable to test each of the plurality of parallel-serial conversion circuits independently.

  FIG. 1 is a block diagram showing an example of a test in the prior art. Part (A) of FIG. 1 shows an example in which a test target semiconductor integrated circuit 7 having a parallel-serial conversion circuit (paraserial conversion circuit) 71 is tested.

  The semiconductor integrated circuit 7 includes a parallel-to-serial conversion circuit 71 that converts a parallel signal into a serial signal, a PRBS (Psudo Random Bit Sequence) generation circuit 72 that generates a test sequence, and a signal amplitude of the waveform Is provided with a buffer circuit 73 for adjusting the above. When testing the semiconductor integrated circuit 7 shown in Part (A) of FIG. 1, a test jig 8 is connected to the semiconductor integrated circuit 7. The test jig 8 includes a buffer circuit 81 that adjusts the signal amplitude, a serial / parallel conversion circuit (serial-parallel conversion circuit) 82 that converts a serial signal into a parallel signal, and a PRBS checker 83. The PRBS checker 83 can generate a sequence having the same contents as the test sequence generated by the PRBS generation circuit 72 in the semiconductor integrated circuit 7 and can compare it with the output of the serial / parallel conversion circuit 82.

  In the test shown in Part (A) of FIG. 1, the PRBS generation circuit 72 generates a test sequence that is a parallel signal in the semiconductor integrated circuit 7 and supplies it to the parallel-serial conversion circuit 71. The parallel / serial conversion circuit 71 converts the test sequence into a serial signal and outputs the serial signal via the buffer circuit 73. In the test jig 8, the serial / parallel conversion circuit 82 converts the serial signal supplied via the buffer circuit 81 into a parallel signal. The PRBS checker 83 generates a sequence having the same contents as the test sequence generated by the PRBS generation circuit 72 in the semiconductor integrated circuit 7 and compares it with the output of the serial / parallel conversion circuit 82. As a result of the comparison, if the two match, the parallel-serial conversion circuit 71 is determined to be a non-defective product, and if the two do not match, it is determined to be a defective product.

  The semiconductor integrated circuit 9 shown in part (B) of FIG. 1 includes a PRBS checker 94 in addition to the parallel-serial conversion circuit 91, the PRBS generation circuit 92, and the buffer circuit 93. Although not shown, the PRBS checker 94 corresponds to a combination of the serial-parallel conversion circuit 82 and the PRBS checker 83 shown in part (A) of FIG.

JP-A-8-122413

  However, in the test shown in Part (A) of FIG. 1, it is necessary to output a serial signal from the semiconductor integrated circuit 7 to the outside and input it to the test jig 8 via the wiring on the board. For this reason, it is difficult to cope with the case where the serial signal is increased in speed. On the other hand, in the semiconductor integrated circuit 9 shown in Part (B) of FIG. 1, it is not necessary to output a serial signal to the outside of the semiconductor integrated circuit, and it is possible to cope with high speed. However, since it is necessary to incorporate an unnecessary PRBS checker 94 in actual operation, when the number of parallel serial conversion circuits (number of channels) provided in the semiconductor integrated circuit increases, the scale of the entire circuit including the circuit in the test Increases significantly.

  On the other hand, it is also conceivable to test the plurality of parallel-serial conversion circuits one by one by sequentially switching the signals from the plurality of parallel-serial conversion circuits and supplying the signals to one PRBS checker. However, in this case, if the number of switching increases, a serial signal timing shift occurs due to a delay shift caused by the switching circuit, making it difficult to test including the timing.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit and a method for testing a semiconductor integrated circuit capable of reliably testing a plurality of parallel-serial conversion circuits with a small circuit scale. .

The semiconductor integrated circuit of the present invention that achieves the above object is as follows.
1st and 2nd parallel serial which receives the parallel data sequence which consists of parallel data of a predetermined | prescribed bit width, and converts each parallel data bit which comprises this parallel data sequence into the serial data arranged in the predetermined order A conversion circuit;
Based on the common test parallel data string having the predetermined bit width, a first test parallel data string supplied to the first parallel-serial conversion circuit and a second parallel-serial conversion circuit supplied to the second parallel-serial conversion circuit A test parallel data string generation circuit for generating two test parallel data strings;
The first parallel-serial conversion circuit converts the first test parallel data string, the first serial data bit, and the second serial-parallel conversion circuit converts the second test parallel data string. A semiconductor integrated circuit comprising a detection circuit for detecting coincidence / mismatch with a bit of the second serial data,
The test Parallel data string generating circuit, the bits of each parallel data constituting the common test parallel data for row, in turn, first in a direction in which later in the predetermined order of less than the predetermined bit width 1 And a parallel bit shift circuit for generating the second test parallel data string by shifting the overflow bits to the previous position in the predetermined order of the next parallel data. Thus, the first test parallel data sequence and the second test parallel data sequence in which the positions in the parallel data of the bits corresponding to the same bits of the common test parallel data sequence are mutually shifted, Produces
When the detection circuit is supplied from the comparison circuit for comparing the bit of the first serial data and the bit of the second serial data inputted at the same timing, and the test parallel data generation circuit In accordance with the shift, at least one bit of the first serial data and the second serial data is shifted, and the first serial data corresponding to the same bit of the common test parallel data string is shifted. And a serial bit shift circuit for aligning the timing at which the bit and the bit of the second serial data are input to the comparison circuit.

  In the semiconductor integrated circuit of the present invention, the first test parallel data string and the second test parallel data string that are shifted by the first number of bits are used as the first and second parallel / serial conversion circuits. Each serial data is supplied, and serially converted serial data is shifted by a serial bit shift circuit by an amount corresponding to the first number of bits and then compared. As a result, the shift in the parallel data string is returned at the time of comparison. Therefore, if the two serial data match, it is determined as a non-defective product, and if they do not match, it is determined as a defective product. Further, for example, even if a defect in design causes an error in the processing of the bit at the same position in both the first and second parallel / serial conversion circuits, the two serials to be shifted back and compared are compared. Since the error position in the data is shifted, a defect is detected. Furthermore, there is no need to incorporate a PRBS checker for testing. Therefore, both the first and second parallel / serial conversion circuits can be tested by simply adding a parallel shift circuit and a serial shift circuit to one test parallel data string generation circuit. Therefore, a plurality of parallel-serial conversion circuits can be reliably tested with a small circuit scale.

  Here, in the semiconductor integrated circuit according to the present invention, when the detection circuit detects a mismatch, any one of the first parallel-serial conversion circuit and the second parallel-serial conversion circuit is detected. It is preferable to include a detection signal generation circuit that generates a detection signal indicating a failure.

  By including the detection signal generation circuit, it is possible to determine the failure of either the first parallel-serial conversion circuit or the second parallel-serial conversion circuit only by examining the detection signal output from the semiconductor integrated circuit.

  According to another aspect of the present invention, there is provided a semiconductor integrated circuit testing method that uses the semiconductor integrated circuit of the present invention, and at least one of the first and second parallel / serial conversion circuits depending on whether the detection signal is generated. One of the defects is detected.

  The test method of the present invention can reliably test a plurality of parallel-serial conversion circuits with a small circuit scale.

  As described above, according to the present invention, a semiconductor integrated circuit and a test method for a semiconductor integrated circuit capable of reliably testing a plurality of parallel-serial conversion circuits with a small circuit scale are realized.

It is a block diagram which shows the example of the test in a prior art. It is a block diagram which shows the structure of the semiconductor integrated circuit which is one Embodiment of this invention. FIG. 3 is a circuit diagram showing a configuration of a parallel bit shift circuit shown in FIG. 2. It is a figure explaining the arrangement | sequence of the input-output data of a 1st and 2nd parallel-serial conversion circuit. It is a timing chart which shows the output data of the 1st and 2nd parallel-serial conversion circuit, and the data after passing through the serial bit shift register of a detection circuit. It is a figure explaining the arrangement | sequence of the input-output data of a 1st and 2nd parallel-serial conversion circuit. 7 is a timing chart showing output data of the first and second parallel-serial conversion circuits and data after passing through the serial bit shift register of the detection circuit when there is an abnormality shown in FIG. 6. It is a figure explaining the arrangement | sequence of the input-output data of the 1st and 2nd parallel-serial conversion circuit of the reference example in which both the shift in a 2-bit shift circuit and the shift in a serial bit shift register are not implemented.

  Embodiments of the present invention will be described below with reference to the drawings.

[Semiconductor integrated circuit]
FIG. 2 is a block diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

  A semiconductor integrated circuit 1 shown in FIG. 2 includes a first parallel-serial conversion circuit 11, a second parallel-serial conversion circuit 12, a test parallel data string generation circuit 13, a detection circuit 14, a first output buffer 15, and A second output buffer 16 is provided. Hereinafter, the “parallel-serial conversion circuit” is also referred to as “parasiri conversion circuit” for short.

  The first parallel-serial conversion circuit 11 and the second parallel-serial conversion circuit 12 receive a parallel data string composed of 8-bit parallel data and convert it into serial data. The first and second parallel-serial conversion circuits 11 and 12 have shift registers, and the eight bits of each parallel data constituting the parallel data string are arranged in the LSB (Least Significant Bit) head order (LSB first). Convert to serial data. Input of 8-bit parallel data in the first and second parallel-serial conversion circuits 11 and 12 is synchronized with a parallel clock (not shown), and an output for each bit of serial data is synchronized with a serial clock (not shown). In normal operation other than the test, the first and second parallel-serial conversion circuits 11 and 12 receive two systems of parallel input data INDATA 1 and 2 supplied from the outside of the semiconductor integrated circuit 1. However, the semiconductor integrated circuit of the present invention is not limited to this, and includes, for example, two data processing circuits that perform data processing and the like, and the first and second parallel-serial conversion circuits described above include two data processing circuits. The parallel data output from may be converted into serial data.

The serial data output from the first and second parallel-serial conversion circuits 11 and 12 are output to the outside of the semiconductor integrated circuit 1 via the first and second output buffers 15 and 16, respectively.

  The test parallel data string generation circuit 13 and the detection circuit 14 are circuits used for testing the first and second parallel-serial conversion circuits 11 and 12.

[Parallel data string generator for testing]
The test parallel data string generation circuit 13 includes a first test parallel data string TEST1 supplied to the first parallel-serial conversion circuit 11 and a second test parallel data string TEST2 supplied to the second parallel-serial conversion circuit 12. And generate The first test parallel data string TEST1 and the second test parallel data string TEST2 are generated based on the common test parallel data TEST0.

  The test parallel data string generation circuit 13 includes a PRBS generation circuit 131, a parallel bit shift circuit 132, and test changeover switches 133 and 134.

  When the first and second parallel-serial conversion circuits 11 and 12 are tested, the test changeover switches 133 and 134 replace the parallel input data INDATA1 and 2 from the outside of the semiconductor integrated circuit 1 with the first and second test switches. This is a switch for supplying parallel data strings TEST1, TEST2. The switching is executed in accordance with, for example, a control signal (not shown) supplied from the outside. In the following, the test case will be described.

  The PRBS generation circuit 131 generates common test parallel data TEST0. The common test parallel data string TEST0 has an 8-bit width. That is, the PRBS generation circuit 131 sequentially outputs 8-bit pseudo random numbers in a parallel data format as a common test parallel data string TEST0.

  The parallel bit shift circuit 132 latches the data in the common test parallel data string TEST0, and the 2-bit shift circuit 1322 shifts the latched common test parallel data string TEST0 by 2 bits. And have.

  Here, the operation of the parallel data string will be described with reference to FIG. FIG. 4 is a diagram illustrating the arrangement of input / output data of the first and second parallel-serial conversion circuits. However, the entire description of FIG. 4 will be given later.

  FIG. 4 shows a first test parallel data string TEST1 and a second test parallel data string TEST2. The first test parallel data string TEST1 includes three 8-bit parallel data w1, w2, and w3. The number given in the frame of each parallel data w1, w2, and w3 is a number for identifying each bit. For example, among the parallel data w1, w2, and w3, the 8-bit parallel data w1 that is first input to the first parallel-serial conversion circuit 11 is 8 bits from “10” that is LSB to “17” that is MSB. It is composed of data. The next input parallel data w2 is composed of 8-bit data from “20” which is LSB to “27” which is MSB. The same applies to the parallel data w3 input next.

  On the other hand, in the second test parallel data string TEST2, the parallel bit shift circuit 132 shifts the first test parallel data string TEST1 by 2 bits toward the MSB. The 2-bit data overflowed by the shift is arranged on the LSB side of the next parallel data.

  FIG. 3 is a circuit diagram showing a configuration of the parallel bit shift circuit shown in FIG. FIG. 3 shows the latch unit 1321 and the 2-bit shift circuit 1322 of the parallel bit shift circuit 132.

  Signals O [0] to O [7] in FIG. 3 indicate each bit of 8-bit parallel data constituting a common test parallel data string TEST0 (see FIG. 2). The latch unit 1321 includes eight flip-flops F1 that hold bit values with a parallel clock.

  Signals a [0] to a [7] in FIG. 3 indicate each bit of 8-bit parallel data constituting the first test parallel data string TEST1 (see FIG. 2). The parallel bit shift circuit 132 outputs the value of each bit of the common test parallel data string TEST0 as it is without shifting as the first test parallel data string TEST1.

  Signals b [0] to b [7] in FIG. 3 indicate each bit of 8-bit parallel data constituting the second test parallel data string TEST2 (see FIG. 2). The 2-bit shift circuit 1322 shifts the bits of the parallel data constituting the common test parallel data string TEST0 latched by the latch unit 1321 by 2 bits in the MSB (Most Significant Bit) direction, that is, two digits. And output the overflowing 2-bit value to the LSB side of the parallel data via the flip-flop F2, thereby generating the second test parallel data string TEST2 (signals b [0] to b [7]). Is generated. Here, the MSB is a bit that is output later when converted into serial data in the first and second parallel-serial conversion circuits 11 and 12, and the LSB is the first and second parallel-serial conversion circuits 11 and 12. When converted to serial data in, it means the bit output first. That is, the second test parallel data string TEST2 (signals b [0] to b [7]) is on the LSB side of the first test parallel data string TEST1 (signals a [0] to a [7]). The 6 bits are shifted to the MSB side by 2 bits, and the 2 bits on the MSB side are the 2 bits on the LSB side of the next parallel data. In this way, the parallel bit shift circuit 132 shown in FIG. 2 generates the first test parallel data string TEST1 and the second test parallel data string TEST2 in which the positions of the respective bits are mutually shifted. .

[Detection circuit]
The detection circuit 14 includes a first serial data bit SER1 obtained by the first parallel-serial conversion circuit 11 converting the first test parallel data string TEST1, and a second serial-parallel conversion circuit 12 configured as a second test parallel. A match / mismatch with the second serial data bit SER2 obtained by converting the data string TEST2 is detected.

  The detection circuit 14 includes a serial bit shift register 141, a comparison circuit 142, and a detection signal generation circuit 143.

  The serial bit shift register 141 includes two flip-flops (not shown) that are connected in series and operate with a serial clock, and according to the 2-bit shift of the parallel bit shift circuit 132 in the test parallel data string generation circuit 13. The first serial data bit SER1 is shifted by 2 bits. By the shift of the serial bit shift register 141, the bit of the first serial data SER1 and the bit of the second serial data SER2 corresponding to the same bit in the common test parallel data string TEST0 are input to the comparison circuit 142. The timing is aligned.

  The comparison circuit 142 compares the bit of the first serial data SER1 and the bit of the second serial data SER2 input at the same timing.

  The detection signal generation circuit 143 generates a detection signal indicating that either the first parallel-serial conversion circuit 11 or the second parallel-serial conversion circuit 12 is defective when the comparison circuit 142 detects a mismatch. To do.

  Here, the serial bit shift register 141 corresponds to an example of a serial bit shift circuit according to the present invention.

[Test behavior]
Next, a test operation in the semiconductor integrated circuit 1 will be described with reference to FIGS.

  The first test parallel data string TEST1 shown in FIG. 4 is an input of the first parallel-serial conversion circuit 11, and the second test parallel data string TEST2 is an input of the second parallel-serial conversion circuit 12. Three 8-bit parallel data w1, w2, and w3 included in the first test parallel data string TEST1 are sequentially supplied to the first parallel-serial conversion circuit 11. When the first parallel data w1 is first input to the first parallel-serial conversion circuit 11, the first parallel-serial conversion circuit 11 sequentially outputs bit values as serial data from the LSB. In FIG. 4, as the output of the first parallel-serial conversion circuit 11, the first 8 bits of data in the first serial data bit SER1 are shown together with the bit identification number. As time elapses, 8-bit data values from “10” to “17” constituting the parallel data w1 are sequentially output bit by bit.

  On the other hand, three 8-bit parallel data w1, w2, and w3 included in the second test parallel data string TEST2 are sequentially supplied to the second parallel-serial conversion circuit 12. In the second test parallel data string TEST2, the data is shifted by 2 bits toward the MSB with respect to the first test parallel data string TEST1 by the parallel bit shift circuit 132 (see FIG. 2). The 2-bit data overflowed by the shift is arranged on the LSB side of the next parallel data. When the first parallel data w1 is input to the second parallel-serial conversion circuit 12, the second parallel-serial conversion circuit 12 outputs bit values as serial data in order from the LSB. FIG. 4 shows the first 8-bit data in the second serial data bit SER2 as the output of the second parallel-serial conversion circuit 12. The second serial data bit SER2 is delayed by two clocks with respect to the first serial data bit SER1. That is, the values from “10” to “15” included in the parallel data w1 at the beginning are sequentially output bit by bit. After this, the values “16”, “17,” “20” to “25” of each bit of the next input parallel data w2 are continued.

  FIG. 5 is a timing chart showing the output data of the first and second parallel-serial conversion circuits and the data after passing through the serial bit shift register of the detection circuit. In the upper part of FIG. 5, the output data SER1 and SER2 of the first and second parallel-serial conversion circuits are shown along the time axis. As described with reference to FIG. 4, the second serial data bit SER2 has a value delayed by two stages, that is, by two clocks in the serial clock with respect to the first serial data bit SER1. The lower part of FIG. 5 shows a state in which the output data SER1 and SER2 of the first and second parallel-serial conversion circuits are input to the comparison circuit 142 via the serial bit shift register 141 of the detection circuit. The serial bit shift register 141 shifts the first serial data bit SER1 by 2 bits. By this shift, the timing at which each bit corresponding to the bit of the common test parallel data TEST0 in the output data SER1 and SER2 of the first and second parallel-serial conversion circuits is input to the comparison circuit 142 is aligned.

  If there is no abnormality in the first and second parallel-serial conversion circuits, the values of the bits of the two serial data input to the comparison circuit 142 have the same contents at the same time as shown in the lower part of FIG. It becomes. The comparison circuit 142 simply compares the coincidence / non-coincidence of two input signals for each bit, that is, for each serial clock. Therefore, the PRBS checker is not necessary for the portion that checks the output data of the first and second parallel-serial conversion circuits.

[Defect detection]
Next, the operation when the first and second parallel-serial conversion circuits 11 and 12 are abnormal will be described.

  FIG. 6 is a diagram for explaining the arrangement of input / output data of the first and second parallel-serial conversion circuits. FIG. 6 shows a first test parallel data string TEST1 and a second test parallel data string TEST2, as in FIG. Here, for example, it is assumed that both the first and second parallel-serial conversion circuits 11 and 12 have the same type of abnormality. In the example shown in FIG. 6, it is assumed that both the first and second parallel-serial conversion circuits 11 and 12 fail to convert the sixth bit from the LSB of the 8-bit parallel data.

  In this case, in the first and second serial data bits SRE1 and SER2, which are the outputs of the first and second parallel-serial conversion circuits 11 and 12, data appears abnormal at the same timing.

  FIG. 7 is a timing chart showing the output data of the first and second parallel-serial conversion circuits and the data after passing through the serial bit shift register of the detection circuit when there is an abnormality shown in FIG. The serial bit shift register 141 shifts the first serial data bit SER1 by 2 bits. By this shift, the timing at which each bit corresponding to the bit of the common test parallel data TEST0 in the output data SER1 and SER2 of the first and second parallel-serial conversion circuits is input to the comparison circuit 142 is aligned. This shift shifts the positions of bits for which conversion failed. In the example shown in FIG. 7, in the two serial data bits input to the comparison circuit 142, mismatch is detected at the fourth, sixth, eleventh, fourteenth, etc. from the beginning. As a result, in the detection signal generation circuit 143, when the comparison circuit 142 detects a mismatch, the detection signal generation circuit 143 indicates that one of the first parallel-serial conversion circuit 11 and the second parallel-serial conversion circuit 12 is defective. A signal is generated. Therefore, the defect of the semiconductor integrated circuit 1 can be easily determined.

  Thus, according to the semiconductor integrated circuit 1 of the present embodiment, for example, due to a design defect, as described with reference to FIG. 7, both the first and second parallel serial conversion circuits have the same position. Even if an error occurs in the bit processing, the error position in the two serial data to be shifted back and compared is shifted, so that a defect is detected. The test parallel data string generation circuit of this embodiment is shared by the first and second parallel / serial conversion circuits. Therefore, both the first and second parallel / serial conversion circuits can be tested by simply adding a parallel shift circuit and a serial shift circuit to one test parallel data string generation circuit. Therefore, a plurality of parallel-serial conversion circuits can be reliably tested with a small circuit scale.

  FIG. 8 is a diagram for explaining the arrangement of input / output data of the first and second parallel-serial conversion circuits in a reference example in which both the shift in the 2-bit shift circuit and the shift in the serial bit shift register are not performed.

  Also in this reference example, as in FIG. 6, it is assumed that both the first and second parallel-serial conversion circuits fail to convert the sixth bit from the LSB of the 8-bit parallel data. In this case, in the first and second serial data bits that are the outputs of the first and second parallel-serial conversion circuits, an abnormality appears in the data at the same timing. That is, it always has a value of “1” or “0” regardless of the input test parallel data. When the first and second serial data bits are compared, the abnormal state is the same, so that no data mismatch is detected.

  On the other hand, according to the semiconductor integrated circuit 1 of the present embodiment, as described with reference to FIG. 7, an error occurs in the processing of the bit at the same position in both the first and second parallel / serial conversion circuits. Even in such a case, since the error position in the two serial data to be compared is returned and compared, a defect is reliably detected.

  In the above-described embodiment, as an example of the first and second parallel-serial conversion circuits according to the present invention, the first and second parallel-serial conversion circuits 11 that convert serial data in the order of LSB first (LSB first). , 12 are shown. However, the present invention is not limited to this, and the predetermined order in the present invention may be, for example, the MSB head.

  In the above-described embodiment, the second test parallel data string TEST2 supplied to the second parallel-serial conversion circuit 12 is shifted, and the first serial data bit SER1 that is the output of the first parallel-serial conversion circuit 11 is shifted. Is shifting. However, the present invention is not limited to this, as long as it shifts at least one bit of the first serial data and the second serial data. For example, the second parallel-serial conversion circuit is provided after shifting the second test parallel data string supplied to the second parallel-serial conversion circuit and delaying the input of the first parallel-serial conversion circuit by one cycle of the parallel clock. It is also possible to align both output timings by shifting the outputs.

  Further, in the above-described embodiment, only one of the inputs of the first and second parallel-serial conversion circuits 11 and 12 is shifted to shift the bit in the parallel data, and then the first and second parallel-serial conversion circuits. An example is described in which only one of the outputs of 11 and 12 is shifted to align the timing. However, the present invention is not limited to this, and both the inputs of the first and second parallel-serial conversion circuits are shifted by a different number of bits, and both the outputs of the first and second parallel-serial conversion circuits are appropriately adapted. The number of bits may be shifted.

  In the above-described embodiment, an example in which parallel data has an 8-bit width is described. However, the present invention is not limited to this, and the number of bits of parallel data may be other than 8 bits.

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 11, 12 Parallel serial conversion circuit 14 Detection circuit 141 Serial bit shift register 142 Comparison circuit 143 Detection signal generation circuit 131 PRBS generation circuit 132 Parallel bit shift circuit 1321 Latch part 1322 2 bit bit shift circuit

Claims (4)

First and second parallel serials for receiving a parallel data string composed of parallel data having a predetermined bit width and converting the bits of the parallel data constituting the parallel data string into serial data arranged in a predetermined order A conversion circuit;
A first test parallel data string supplied to the first parallel-serial conversion circuit and a second parallel-serial conversion circuit supplied to the first parallel-serial conversion circuit based on the common test parallel data string having the predetermined bit width. A test parallel data string generation circuit for generating two test parallel data strings;
The first parallel-serial conversion circuit converts the first test parallel data string, the first serial data bit, and the second parallel-serial conversion circuit converts the second test parallel data string A semiconductor integrated circuit comprising a detection circuit for detecting coincidence / mismatch with a bit of the second serial data,
The test parallel data string generation circuit sets the bits of the parallel data constituting the common test parallel data string in a first order less than the predetermined bit width in a direction that is later in the predetermined order. And a parallel bit shift circuit for generating the second test parallel data string by shifting the overflowed bits to the previous position in the predetermined order of the next parallel data. Thus, the first test parallel data sequence and the second test parallel data sequence in which the positions in the parallel data of the bits corresponding to the same bits of the common test parallel data sequence are mutually shifted, Produces
When the detection circuit is supplied from a comparison circuit that compares the bit of the first serial data and the bit of the second serial data input at the same timing, and the test parallel data generation circuit In response to the shift, at least one bit of the first serial data and the second serial data is shifted, and the first serial data corresponding to the same bit of the common test parallel data string is shifted. And a serial bit shift circuit for aligning the timing at which the bit and the bit of the second serial data are input to the comparison circuit. The parallel bit shift circuit converts the bits of the parallel data constituting the common test parallel data sequence into a second number of bits less than the predetermined bit width in order in the predetermined order. And shifting the overflow bit to the previous position in the predetermined order of the next parallel data to generate the first test parallel data string,
2. The semiconductor integrated circuit according to claim 1, wherein the first and second bit numbers are different from each other . Detection in which the detection circuit generates a detection signal indicating that either the first parallel-serial conversion circuit or the second parallel-serial conversion circuit is defective when the comparator detects a mismatch. 3. The semiconductor integrated circuit according to claim 1, further comprising a signal generation circuit.   4. A test method for a semiconductor integrated circuit, comprising: using the semiconductor integrated circuit according to claim 3; and detecting at least one defect of the first and second parallel / serial conversion circuits based on whether or not the detection signal is generated. .

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