JP6243210B2 - Serial data transmission device, serial data reception device, serial data transmission method, and serial data transmission program - Google Patents

Description

  The present invention relates to a serial data transmission apparatus that transmits data to another apparatus in a system that performs communication using a serial data communication path while synchronizing clocks between apparatuses.

  A large-scale computer system in recent years includes a large number of devices, and the devices operate in cooperation with each other by communicating with each other. A serial data communication path is often used as a communication path for communication between apparatuses. When performing serial data communication between devices, it is necessary to perform synchronous control on a clock for operating the transmission side device and the reception side device so that the reception side device does not miss communication data. In order to perform the synchronization control, it is necessary to transmit a signal related to the clock together with the communication data body from the transmission side device to the reception side device. At this time, for example, there is a method of transmitting a clock by providing a communication path separately from the communication path for transmitting the communication data main body, such as I2C (Inter-Integrated Circuit) (registered trademark) communication. However, in this system, the data transmission efficiency per communication path is halved. Therefore, there is an increasing expectation for a technique for multiplexing a communication data body and a signal related to a clock and transmitting them through the same communication path. In addition, as the communication distance between devices becomes longer or the clock becomes faster, communication errors due to signal distortion and the like are more likely to occur, so there is an increasing expectation for a technology that improves the reliability of high-speed serial communication. .

  As a technique related to the above-described technique, Patent Document 1 discloses that a transmission-side apparatus bundles a plurality of digital signals having different frequency information and transmits them at high speed without depending on data contents. A system that reproduces and separates a plurality of digital signals while maintaining the above is disclosed.

  Further, Patent Document 2 discloses a system that can correctly transmit and receive data by avoiding an insertion loss that occurs when a signal passes through a communication path when performing high-speed serial communication between devices having a long communication distance. Is disclosed.

JP 2013-062687 JP 2012-169946

  In the technique disclosed in Patent Document 1, it is necessary that the transmission-side apparatus includes a multiplexer that multiplexes a plurality of data blocks, and the reception-side apparatus includes a demultiplexer that separates individual data blocks from the multiplexed data. There is a problem that hardware increases. Further, in the technology disclosed in Patent Document 2, since it is necessary to provide a relay device between devices that perform communication, there is a problem that hardware increases as in Patent Document 1. Therefore, it becomes a problem for a device that performs serial data communication to perform accurate synchronization control regarding a clock with a simple configuration.

  A main object of the present invention is to provide a serial data transmission device, a serial data reception device, a serial data transmission method, and a serial data transmission program that solve this problem.

  The serial data transmission device according to the present invention is configured to flow through one of the plurality of serial data communication paths when transmitting data to the serial data reception apparatus using a plurality of serial data communication paths operating in synchronization. Control bit insertion means for inserting synchronization control bits so as to be distributed between the plurality of serial data communication paths at predetermined time intervals in time series with respect to data, and the serial data receiving device, When adjusting the timing to capture the plurality of bits using the result of performing a predetermined logical calculation based on the value indicated by the plurality of bits received at the first clock timing via the serial data communication path, The synchronization control bit transmitted at the second clock timing, and a value indicated by one or more bits excluding the synchronization control bit The synchronization control so that the result of performing the predetermined logic calculation is inverted from the result of performing the predetermined logic calculation based on a plurality of bits transmitted at the clock timing immediately before the second clock timing. And generating means for generating bits.

  The serial data receiving device according to the present invention receives the same clock via the plurality of serial data communication paths when receiving data from the serial data transmission device via the plurality of serial data communication paths operating in synchronization. Synchronous timing detection means for generating a signal for adjusting a clock timing for fetching the plurality of bits based on a timing at which a result of performing a predetermined logical calculation based on values indicated by the plurality of bits received at the timing is inverted. It is characterized by that.

  In another aspect of achieving the above object, the serial data transmission method according to the present invention provides a method for transmitting data to a serial data receiving apparatus using a plurality of serial data communication paths operating in synchronization by an information processing apparatus. , With respect to the data flowing through any one of the plurality of serial data communication channels, inserting synchronization control bits so as to be distributed among the plurality of serial data communication channels at a predetermined time interval of the bit sequence, The serial data receiving device uses the result obtained by performing a predetermined logical calculation based on values indicated by the plurality of bits received at the first clock timing via the plurality of serial data communication paths, and the plurality of bits. When adjusting the timing to capture the clock, the synchronization control bit transmitted at the second clock timing and the synchronization control bit As a result of performing the predetermined logical calculation based on a value indicated by one or more bits excluding, the predetermined logical calculation is performed based on a plurality of bits transmitted at the clock timing immediately before the second clock timing. The synchronization control bit is generated so as to be inverted from the result.

  Further, in a further aspect to achieve the above object, the serial data transmission program according to the present invention is configured to transmit the data to the serial data receiving device using a plurality of serial data communication paths that operate in synchronization. Control bit insertion processing for inserting synchronization control bits into the data flowing through one of a plurality of serial data communication paths so as to be distributed among the plurality of serial data communication paths at predetermined time-series bit intervals And the serial data receiving device uses a result obtained by performing a predetermined logical calculation based on values indicated by a plurality of bits received at a first clock timing via the plurality of serial data communication paths. The synchronization control bit transmitted at the second clock timing when adjusting the timing of capturing a plurality of bits; and The result of performing the predetermined logic calculation based on a value indicated by one or more bits excluding the synchronization control bit is based on a plurality of bits transmitted at a clock timing immediately before the second clock timing. A generation process for generating the synchronization control bit is executed by a computer so as to be inverted from a result of the logical calculation.

  Furthermore, the present invention can be realized by a computer-readable non-volatile storage medium in which such an information reading program (computer program) is stored.

  The present invention makes it possible to accurately perform synchronous control related to a clock between devices performing serial data communication with a simple configuration.

It is a block diagram which shows the structure of the serial data transmission / reception system which concerns on 1st Embodiment of this invention. It is a flowchart (1/2) which shows operation | movement of the serial data transmission / reception system which concerns on 1st Embodiment of this invention. It is a flowchart (2/2) which shows operation | movement of the serial data transmission / reception system which concerns on 1st Embodiment of this invention. It is a figure which illustrates the function of the transmission data division part and P / S conversion part which concern on 1st Embodiment of this invention. It is a figure which illustrates the serial data by which the synchronous control bit was inserted by the control bit insertion part which concerns on 1st Embodiment of this invention. It is a figure which illustrates the truth table regarding the synchronous control bit which the production | generation part which concerns on 1st Embodiment of this invention produces | generates. It is a figure which illustrates the synchronous control bit production | generation circuit with which the production | generation part which concerns on 1st Embodiment of this invention is provided. It is a figure which illustrates the frame head data which the frame head insertion part which concerns on 1st Embodiment of this invention inserts. It is a figure which illustrates the function of the S / P conversion part which concerns on 1st Embodiment of this invention. It is a figure which illustrates the function of the reception data integration part which concerns on 1st Embodiment of this invention. It is a figure which illustrates the serial data in which the synchronous control bit was inserted in case the 1st Embodiment of this invention is provided with three serial data communication paths. It is a block diagram which shows the structure of the serial data transmission / reception apparatus which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the information processing apparatus which can execute the serial data transmission apparatus of each embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment>
FIG. 1 is a block diagram conceptually showing the configuration of the serial data transmission / reception system 1 of the first embodiment. The serial data transmission / reception system 1 according to the present embodiment includes a serial data transmission device 10 and a serial data reception device 20. The serial data transmission device 10 transmits serial data to the serial data reception device 20 via the two serial data communication paths 108 to 109.

  The serial data transmission device 10 includes a transmission data division unit 11, a P / S (parallel / serial) conversion unit 12, a control bit insertion unit 13, a generation unit 14, a frame head insertion unit 15, a transmission clock 1 supply unit 16, and The transmission clock 2 supply unit 17 is provided. The transmission data division unit 11, the P / S conversion unit 12, the control bit insertion unit 13, the generation unit 14, and the frame head insertion unit 15 may be an electronic circuit or a computer program and a processor that operates according to the computer program. It may be realized by. The transmission clock 1 supply unit 16 and the transmission clock 2 supply unit 17 are electronic devices including a clock generator (not shown).

  The functions of the transmission data division unit 11 and the P / S conversion unit 12 are shown in FIG. The transmission data dividing unit 11 includes the bits 111 to 126 included in the 16-bit parallel data received via the parallel data communication path 101, the bits 111 to 119 and the bits 120 to Divided into 126. The transmission data dividing unit 11 inputs the bits 111 to 119 and the bits 120 to 126 to the P / S conversion unit 12 via the parallel data communication paths 102 to 103, respectively.

  The P / S conversion unit 12 converts bits 111 to 119 and bits 120 to 126, which are two input 8-bit parallel data, into serial data. The P / S conversion unit 12 inputs the converted 8-bit serial data to the control bit insertion unit 13 and the generation unit 14 via the serial data communication paths 104 to 105, respectively.

  The control bit insertion unit 13 inserts a synchronization control bit at a predetermined position with respect to the two systems of 8-bit serial data input from the P / S conversion unit 12, and the serial data into which the synchronization control bit is inserted The data is input to the frame head insertion unit 15 via the serial data communication paths 106 to 107. Such a synchronization control bit is a bit inserted into serial data to be transmitted so that the serial data receiving device 20 can accurately perform synchronization control with the serial data transmitting device 20 regarding the clock. FIG. 4 shows an example of serial data in which the synchronization control bit is inserted by the control bit insertion unit 13.

  4A to 4B show serial data 1060 flowing through the serial data communication path 106 and serial data 1070 flowing through the serial data communication path 107, respectively. As shown in FIG. 4A, the control bit insertion unit 13 inserts two synchronization control bits A and B into the bits 111 to 118 that are 8-bit serial data. Similarly, as shown in FIG. 4B, the control bit inserting unit 13 inserts two synchronization control bits C and D into bits 119 to 126 which are 8-bit serial data.

  As shown in FIGS. 4A to 4B, the serial data communication apparatus 10 according to the present embodiment adds 20 synchronization control bits A to D to the input 16-bit parallel data. The bit serial data is transmitted to the serial data receiving device 20. In this case, the cycle of the transmission clock 1 related to the parallel data processing supplied from the transmission clock 1 supply unit is the transmission clock related to the serial data processing supplied from the transmission clock 2 supply unit. 10 times the period of 2.

  The control bit insertion unit 13 inserts the synchronization control bit A at the head of the bits 111 to 118 constituting the first system serial data, and the second system serial data at a position 3 bits after the synchronization control bit A. The synchronization control bit C is inserted into the bits 119 to 126 constituting the same. The control bit insertion unit 13 inserts the synchronization control bit B into the bits 111 to 118 constituting the first-system serial data at a position 3 bits after the synchronization control bit C. The control bit insertion unit 13 inserts the synchronization control bit D into the bits 119 to 126 constituting the second system serial data at a position 3 bits after the synchronization control bit B. That is, the control bit insertion unit 13 alternately inserts synchronization control bits into the two systems of serial data every 3 bits in the time series. The control bit insertion unit 13 obtains information on whether “0” or “1” is inserted as the synchronization control bits A to D from the generation unit 14.

  The generation unit 14 generates synchronization control bits based on the two systems of 8-bit serial data input from the P / S conversion unit 12 and inputs information about the generated synchronization control bits to the control bit insertion unit 13. To do.

  The serial data receiving device 20 according to the present embodiment calculates EXOR (exclusive OR) for each bit in two systems of serial data, and based on the timing at which the value indicated by the calculated EXOR is inverted, the serial data transmitting device Synchronous control related to the clock is performed. Note that the serial data receiving device 20 may perform a logical calculation other than EXOR for each bit in the two systems of serial data. The serial data 1080 obtained by EXORing the serial data flowing through the serial data communication paths 106 to 107, which is the result of EXORing the serial data shown in FIGS. 4A to 4B, is shown in FIG. Shown in The value indicated by T to Z in FIG. 4C is either “0” or “1”. In FIG. 4C, for example, a value indicated by Y is a value indicated by EXOR of bit 111 and bit 120, and a value indicated by X is a value indicated by EXOR of bit 112 and bit 121.

  As shown in FIG. 4C, the values indicated by EXOR of bit 113 and synchronization control bit C are values obtained by inverting X, which is the value indicated by EXOR of bits 112 and 121. The values indicated by EXOR of bit 124 and synchronization control bit B are values obtained by inverting V, which is the value indicated by EXOR of bits 115 and 123. Similarly, the value indicated by EXOR of bit 118 and synchronization control bit D is a value obtained by inverting T, which is the value indicated by EXOR of bits 117 and 126. That is, in the serial data 1080 obtained by EXORing the serial data flowing through the serial data communication paths 106 to 107, the value indicated by the bit related to the synchronization control bit is a value obtained by inverting the previous bit.

  The generation unit 14 generates each control bit so that the serial data 1080 obtained by performing EXOR of the serial data flowing through the serial data communication paths 106 to 107 has the above-described value. A truth table 1090 regarding the synchronization control bit C is shown in FIG. The generation unit 14 generates the synchronization control bit C based on the values indicated by the bits 113 and X according to the logic indicated by the truth table 1090 regarding the synchronization control bit C.

  FIG. 6 shows a synchronization control bit generation circuit 140 that realizes the logic indicated by the truth table 1090 regarding the synchronization control bit C. The synchronization control bit generation circuit 140 includes an EXOR gate 141 and an EXNOR (negative exclusive OR) gate 142. The EXOR gate 141 generates X that is a value indicated by EXOR of the bits 112 and 121. The EXNOR gate 142 generates a synchronization control bit C that is a value indicated by EXNOR of X and bit 113. The generation unit 14 includes a synchronization control bit generation circuit 140, and similarly includes a generation circuit that generates synchronization control bits A, B, and D.

  The frame head insertion unit 15 inserts the frame head data into the two systems of serial data input from the control bit insertion unit 13 at a predetermined constant interval (for example, every 10 milliseconds). The frame head insertion unit 15 may insert frame head data at a specific timing instead of a predetermined fixed interval. The frame head data is data that is inserted so as to be distinguishable from the normal data so that the start of capturing related to the data received by the serial data receiving device 20 can be determined.

  An example of the frame head data inserted by the frame head insertion unit 15 is shown in FIG. FIG. 7A shows an example of the frame head data 1100 flowing through the serial data communication path 108 inserted into the serial data including the bits 111 to 118. FIG. 7B is an example of the frame head data 1110 flowing in the serial data communication path 109 inserted into the serial data including the bits 119 to 126. The frame head data in this embodiment is 20 bits.

  FIG. 7C is an example of serial data 1120 obtained by performing EXOR of the frame head data flowing through the serial data communication paths 108 to 109. As shown in FIG. 7C, the serial data 1120 obtained by taking the EXOR of the frame head data flowing through the serial data communication channels 108 to 109 repeats inversion every 3 bits in the time series. That is, the frame head insertion unit 15 uses a predetermined logic so that the serial data 1120 obtained by EXORing the frame head data flowing through the serial data communication channels 108 to 109 repeats inversion every 3 bits in time series. Generate data and insert into serial data.

  FIG. 7D is an example of serial data 1130 obtained by performing an EXOR of normal data flowing through the serial data communication paths 108 to 109. The serial data 1130 obtained by EXORing the normal data flowing through the serial data communication paths 108 to 109 is 20-bit data obtained by connecting two serial data shown in FIG. The bit described as “control” in FIG. 7D is a bit related to the synchronization control bit, and as described above, its value is a value obtained by inverting the previous bit.

  As shown in FIGS. 7C to 7D, the serial data 1120 obtained by taking the EXOR of the frame head data flowing through the serial data communication paths 108 to 109 and the EXOR of the normal data flowing through the serial data communication paths 108 to 109 are used. The value is different from the serial data 1130 taken.

  The frame head insertion unit 15 transmits the two systems of serial data into which the frame head data is inserted to the synchronization timing detection unit 24 in the serial data receiving device 20 via the serial data communication paths 108 to 109.

  The serial data receiving device 20 includes a reception data integration unit 21, an S / P conversion unit 22, a frame head detection unit 23, a synchronization timing detection unit 24, a reception clock 1 supply unit 25, and a reception clock 2 supply unit 26. I have. The reception data integration unit 21, the S / P conversion unit 22, the frame head detection unit 23, and the synchronization timing detection unit 24 may be an electronic circuit, or may be realized by a computer program and a processor that operates according to the computer program. In some cases. The reception clock 1 supply unit 25 and the reception clock 2 supply unit 26 are electronic devices including a clock oscillator.

  The synchronization timing detection unit 24 inputs the two systems of serial data received from the serial data transmission device 10 to the frame head detection unit 23 via the serial data communication paths 206 to 207. The synchronization timing detection unit 24 calculates a 2-bit EXOR received at the same clock timing for the received two systems of serial data. The synchronization timing detection unit 24 generates a synchronization control signal for adjusting the clock timing for capturing serial data based on the timing at which the 2-bit EXOR is inverted, and inputs the synchronization control signal to the reception clock 2 supply unit.

  The reception clock 2 supply unit 2 includes a PLL (Phase Locked Loop) circuit, and performs synchronization control on the reception clock 2 by the PLL circuit based on the synchronization control signal input from the synchronization timing detection unit 24. The period of the reception clock 2 is equivalent to the period of the transmission clock 2 in the serial data transmission device 10. The reception clock 2 supply unit 2 distributes the synchronization-controlled reception clock 2 to the synchronization timing detection unit 24, the frame head detection unit 23, and the S / P conversion unit 22.

  The frame head detection unit 23 checks whether the EXOR of the two systems of serial data input from the synchronization timing detection unit 24 has the pattern shown in FIG. When the EXOR of the two systems of serial data has the pattern shown in FIG. 7C, the frame head detector 23 determines that the input 20-bit serial data is the frame head data, and receives the received serial data. Decide to start capturing data. When the EXOR of the two systems of serial data does not have the pattern shown in FIG. 7C, the frame head detection unit 23 uses the input serial data as it is through the serial data communication paths 204 to 205 as S / P. Input to the converter 22.

  The function of the S / P converter 22 is shown in FIG. The S / P converter 22 converts the input two systems of serial data into parallel data. As shown in FIG. 8, the S / P converter 22 discards the synchronization control bits A and B from the serial data 2040 flowing through the serial data communication path 204, and then converts the serial data 2040 into an 8-bit parallel including bits 111 to 118. Convert to data. The S / P converter 22 also converts serial data flowing through the serial data communication path 205 into 8-bit parallel data including bits 119 to 126 by the same procedure.

  Note that the period of the reception clock 1 related to the parallel data processing is 10 times the period of the reception clock 2 related to the serial data processing. That is, the cycle of the reception clock 2 is equivalent to the cycle of the transmission clock 1 in the serial data transmission device 10. The reception clock 1 is distributed from the reception clock 1 supply unit 25. The S / P conversion unit 22 inputs two systems of 8-bit parallel data obtained by converting two systems of 8-bit serial data to the reception data integration unit 21 via the parallel data communication paths 202 to 203.

  The function of the reception data integration unit 21 is shown in FIG. The reception data integration unit 21 integrates the two systems of input 8-bit parallel data into 16-bit parallel data including bits 111 to 126, and the 16-bit parallel data is connected via the parallel data communication path 201. Output to the outside.

  Next, the operation (processing) of the serial data transmission / reception system 1 according to the present embodiment will be described in detail with reference to the flowcharts of FIGS. 2A to 2B.

  The transmission data dividing unit 11 divides 16-bit parallel data received from the outside into two systems of 8-bit parallel data, and inputs them to the P / S conversion unit 12 (step S101). The P / S conversion unit 12 converts the two systems of 8-bit parallel data into serial data, and inputs the serial data to the control bit insertion unit 13 and the generation unit 14 (step S102). The generation unit 14 generates a synchronization control bit from the two systems of 8-bit parallel data, and inputs the generated synchronization control bit to the control bit insertion unit 13 (step S103). The control bit insertion unit 13 inserts a synchronization control bit at a predetermined position in the two systems of serial data, and inputs the two systems of serial data with the synchronization control bit inserted into the frame head insertion unit 15 (step S104). .

  When the serial data to be transmitted is the top data (Yes in step S105), the frame head insertion unit 15 inserts the frame head data into each of the two systems of serial data, and detects the synchronization data of the two systems of serial data. It transmits to the part 24 (step S106). If the serial data to be transmitted is not the top data (No in step S105), the frame head insertion unit 15 transmits the two systems of serial data as they are to the synchronization timing detection unit 24 (step S107).

  The synchronization timing detection unit 24 generates a synchronization control signal at the timing when the exclusive OR of 2 bits in the received two systems of serial data is inverted, and inputs the synchronization control signal to the reception clock 2 supply unit 26 (step S108). The reception clock 2 supply unit 26 performs synchronization control on the clock by the PLL circuit based on the synchronization control signal, and the synchronization-controlled clock is transmitted to the synchronization timing detection unit 24, the frame head detection unit 23, and the S / P conversion. Distribute to the unit 22 (step S109). The synchronization timing detection unit 24 inputs the received two systems of serial data to the frame head detection unit 24 as they are (step S110).

  The frame head detection unit 24 checks whether the serial data is frame head data (step S111). When the serial data is the frame head data (Yes in Step S112), the frame head detection unit 24 determines the start of capturing the serial data (Step S113). When the serial data is not the frame head data (No in step S112), the frame head detection unit 24 inputs the serial data as it is to the S / P conversion unit 22 (step S114).

  The S / P conversion unit 22 discards the synchronization control bits from the received two systems of serial data, converts each serial data into 8-bit parallel data, and inputs the data to the reception data integration unit 21 (step S115). . The reception data integration unit 21 integrates the two systems of 8-bit parallel data into 16-bit parallel data and outputs the data to the outside (step S116), and the entire process ends.

  The serial data transmission / reception system 1 according to the present embodiment can accurately perform synchronous control related to a clock between devices performing serial data communication with a simple configuration. The reason is that the serial data receiving device 20 transmits the serial data when the control bit insertion unit 13 inserts the synchronization control bit generated by the generation unit 14 with simple logic at a predetermined position in the two systems of serial data. This is because the synchronization control regarding the clock is accurately performed with the apparatus 10.

  When two devices perform serial data communication, there is a possibility that the receiving side device may miss communication data if the clocks in the transmitting side device and the receiving side device are not synchronized. Various methods are known as a method for performing synchronization control regarding the clock between the transmission side device and the reception side device, but it is desirable to perform synchronization control accurately with a simple configuration.

  The synchronization timing detection unit 24 in the serial data receiving apparatus 20 according to the present embodiment has a receiving clock 2 supply unit when the EXOR of the bits received at the same clock timing via two serial data communication paths is inverted. 26 generates a signal for instructing the synchronous control. At this time, for example, when the same value continues for a long period of time when the data received via the two serial data communication paths continues for a long period, the synchronization timing detection unit 24 performs the EXOR of the bits received at the same clock timing for a long period of time. Without inversion, it becomes impossible to generate a signal for instructing synchronous control over a long period of time. Therefore, in this case, the serial data receiving device 20 cannot perform synchronization control regarding the clock with the serial data transmitting device 10 for a long period of time, and there is a high possibility of missing communication data.

  The control bit insertion unit 13 in the serial data transmission device 10 according to the present embodiment distributes the communication data transmitted through the plurality of serial data communication channels equally among the plurality of serial data communication channels every three bits in time series. Thus, the synchronization control bit is inserted. Then, the generation unit 14 generates the synchronization control bits so that the value indicated by EXOR regarding the bits transmitted at the same clock timing via the plurality of serial data communication paths is inverted from the value at the immediately preceding clock timing. .

  Therefore, in this embodiment, the synchronization timing detection unit 24 can generate a signal instructing synchronization control at a frequency of once or more within 3 clock timings. Generally, it is desirable to perform synchronization control at a frequency of at least once within at least 3 clock timings. The control bit insertion unit 13 according to the present embodiment performs synchronization control bits every 3 bits in time series. Therefore, accurate synchronization control can be performed with a simple configuration. Note that the control bit insertion unit 13 may insert a synchronization control bit every two bits in the time series according to environmental conditions such as the distance between devices or the clock frequency, with a stricter standard than in this embodiment. Alternatively, the synchronization control bits may be inserted every 4 bits or more by loosening the reference from this embodiment.

  The serial data transmitting apparatus 10 according to the present embodiment divides 16-bit parallel data and transmits the 16-bit parallel data to the serial data receiving apparatus 20 through two systems of serial data communication paths. The serial data receiving apparatus 20 includes two systems of serial data. Data received via the data communication path is integrated into the original 16-bit parallel data. In this case, the synchronization control bits inserted per serial data system are every 6 bits. On the other hand, when 16-bit parallel data is transmitted through one system serial data communication path without being divided, the synchronization control bits inserted per serial data system are every 3 bits. Therefore, the serial data transmission / reception system 1 can avoid a significant decrease in data transfer efficiency when performing clock synchronization control between devices.

  In addition, since the frame head portion insertion unit 15 according to the present embodiment inserts frame head data that is distinguishable from normal data, the serial data receiving device 20 may determine the start of capturing the received serial data. it can.

  Although the serial data transmission / reception system 1 according to the present embodiment inputs / outputs 16-bit parallel data, parallel data of 8-bit width or 32-width can be processed in the same manner. Further, the serial data transmission / reception system 1 may communicate using three or more serial data communication paths. FIG. 10 shows an example of serial data in which a synchronization control bit is inserted when the serial data transmission / reception system 1 includes three serial data communication paths. In this case, the serial data transmission / reception system 1 transmits / receives bits 127 to 134 in addition to the bits 111 to 126.

  FIG. 10A is an example of serial data 1160 that flows through the serial data communication path of the first system. FIG. 10B is an example of serial data 1170 flowing through the second serial data communication path. FIG. 10C is an example of serial data 1180 that flows through the serial data communication path of the third system. FIG. 10D is an example of serial data 1190 obtained by taking an EXOR of serial data flowing through three systems of serial data communication paths. The synchronization control bits A to C are inserted into serial data of the first system to the third system, respectively, every 3 bits in the time series. As shown in FIG. 10D, the values indicated by EXOR of bits 113 and 130 and the synchronization control bit B are values obtained by inverting X, which is the value indicated by EXOR of bits 112, 121, and 129. Similarly, the values indicated by EXOR of bits 116 and 124 and synchronization control bit C are values obtained by inverting V, which is the value indicated by EXOR of bits 115, 123 and 132. In this case, the serial data communication path provided in the serial data transmission / reception system 1 is increased by one, but the synchronization control bit inserted per serial data system is every 9 bits, and the degree of decrease in data transfer efficiency. Can be further reduced.

<Second Embodiment>
FIG. 11 is a block diagram conceptually showing the configuration of the serial data transmitting apparatus 30 of the second embodiment.

  The serial data transmission device 30 of this embodiment includes a control bit insertion unit 33 and a generation unit 34.

  The control bit insertion unit 33 uses any one of the serial data communication paths 308 to 309 when transmitting data to the serial data receiving device 40 using a plurality of, for example, two serial data communication paths 308 to 309 operating in synchronization. Synchronization control bits are inserted into the data flowing through the serial data communication paths 308 to 309 at predetermined time intervals in time series.

  The generation unit 34 uses the result of the predetermined logical calculation performed by the serial data receiving device 40 based on the value indicated by 2 bits received at the first clock timing via the serial data communication paths 308 to 309. When adjusting the timing of taking in the plurality of bits, a predetermined logical calculation was performed based on the synchronization control bit transmitted at the second clock timing and the value indicated by one or more bits excluding the synchronization control bit The synchronization control bits are generated so that the result is inverted from the result of the predetermined logic calculation based on the two bits transmitted at the clock timing immediately before the second clock timing.

  The serial data transmission device 30 according to the present embodiment can accurately perform synchronous control related to a clock between devices performing serial data communication with a simple configuration. The reason is that the serial data receiving device 40 transmits the serial data when the control bit inserting unit 33 inserts the synchronization control bit generated by the generating unit 34 with simple logic into a predetermined position in the two systems of serial data. This is because the synchronization control regarding the clock is accurately performed with the device 30.

<Hardware configuration example>
In each embodiment described above, each unit of the serial data transmission devices 10 and 30 shown in FIG. 1 and FIG. 11 can be regarded as a function (processing) unit (software module) of a software program (including a hardware configuration). (Excluding the transmission data dividing unit 11, the P / S conversion unit 12, the claim head insertion unit 15, the transmission clock 1 supply unit 16, and the transmission clock 2 supply unit 17 shown in FIG. 1). However, the division of each part shown in these drawings is a configuration for convenience of explanation, and various configurations can be assumed for mounting. An example of the hardware environment in this case will be described with reference to FIG.

  FIG. 12 is a diagram illustrating an exemplary configuration of an information processing apparatus 900 (computer) that can execute the serial data transmission apparatus according to the exemplary embodiment of the present invention. That is, FIG. 12 shows a configuration of a computer (information processing apparatus) that can realize the serial data transmission apparatus shown in FIGS. 1 and 11, and a hardware environment that can realize each function in the above-described embodiment. Represents.

  The information processing apparatus 900 illustrated in FIG. 12 includes a CPU 901 (Central_Processing_Unit), a ROM 902 (Read_Only_Memory), a RAM 903 (Random_Access_Memory), a hard disk 904 (storage device), and a communication interface 905 (Interface: “I / F” hereinafter). A reader / writer 908 capable of reading and writing data stored in a storage medium 907 such as a CD-ROM (Compact_Disc_Read_Only_Memory), and an input / output interface 909. These components are connected via a bus 906 (communication line). It is a general computer connected.

  The present invention described with the above-described embodiment as an example is a block configuration diagram (FIGS. 1 and 11) or a flowchart referred to in the description of the information processing apparatus 900 shown in FIG. This is achieved by supplying a computer program capable of realizing the functions (FIGS. 2A to 2B), reading the computer program to the CPU 901 of the hardware, and interpreting and executing the computer program. The computer program supplied to the apparatus may be stored in a readable / writable volatile storage memory (RAM 903) or a nonvolatile storage device such as the hard disk 904.

  In the above-described case, the computer program can be supplied to the hardware by a method of installing in the apparatus via various storage media 907 such as a CD-ROM, or an external method via a communication line such as the Internet. A general procedure can be adopted at present, such as a method of downloading more. In such a case, it can be understood that the present invention is configured by a code constituting the computer program or a storage medium 907 in which the code is stored.

  The present invention has been described above using the above-described embodiment as an exemplary example. However, the present invention is not limited to the above-described embodiment. That is, the present invention can apply various modes that can be understood by those skilled in the art within the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Serial data transmission system 10 Serial data transmission apparatus 11 Transmission data division part 12 P / S conversion part 13 Control bit insertion part 14 Generation part 140 Synchronization control bit generation circuit 141 EXOR gate 142 EXNOR gate 15 Frame head insertion part 16 Transmission clock DESCRIPTION OF SYMBOLS 1 Supply part 17 Transmission clock 2 supply part 20 Serial data receiver 21 Reception data integration part 22 S / P conversion part 23 Frame head detection part 24 Synchronization timing detection part 25 Reception clock 1 supply part 26 Reception clock 2 supply part 30 serial data transmission device 33 control bit insertion unit 34 generation unit 40 serial data reception device 101 16-bit parallel data communication path 102 to 103 8-bit parallel data communication path 104 to 105 serial data communication path 106 to 107 serial data communication path 108 to 109 serial data communication path 111 to 126 bit 127 to 134 bit 201 16 bit parallel data communication path 202 to 203 8-bit parallel data communication path 204 to 205 serial data communication path 206 to 207 serial data communication path 308 to 309 Serial data communication path 900 Information processing apparatus 901 CPU
902 ROM
903 RAM
904 Hard disk 905 Communication interface 906 Bus 907 Storage medium 908 Reader / writer 909 I / O interface 1060 Serial data flowing through serial data communication path 106 1070 Serial data flowing through serial data communication path 107 1080 Serial data flowing through serial data communication paths 106 to 107 EXORed serial data 1090 Truth table for synchronization control bit C 1100 Frame head data flowing through serial data communication path 108 1110 Frame head data flowing through serial data communication path 109 1120 Frame head data flowing through serial data communication paths 108 to 109 EXOR of serial data 1130 of normal data flowing through serial data communication paths 108 to 109 XORed serial data 1160 Serial data flowing through the first serial data communication path 1170 Serial data flowing through the second serial data communication path 1180 Serial data flowing through the third serial data communication path 1190 Three systems of serial data Serial data 2040 obtained by EXORing serial data flowing through the data communication path 2040 Serial data flowing through the serial data communication path 204

Claims (10)

When transmitting data to a serial data receiving device using a plurality of serial data communication paths that operate in synchronization, the data flowing through any of the plurality of serial data communication paths is time-sequential Control bit insertion means for inserting synchronization control bits so as to be distributed among the plurality of serial data communication paths for each bit interval;
The serial data receiving device uses a result obtained by performing a predetermined logical calculation based on values indicated by a plurality of bits received at a first clock timing via the plurality of serial data communication paths. Result of performing the predetermined logical calculation based on the value indicated by the synchronization control bit transmitted at the second clock timing and one or more bits excluding the synchronization control bit when adjusting the timing of fetching bits Generating means for generating the synchronization control bit so as to be inverted from the result of the predetermined logic calculation based on a plurality of bits transmitted at the clock timing immediately before the second clock timing;
A serial data transmission device. After dividing parallel data into a plurality of parallel data sets, each of the plurality of parallel data sets is converted into serial data to be transmitted using the plurality of serial data communication paths, respectively.
The serial data transmission device according to claim 1, further comprising: For the data to be transmitted using the plurality of serial data communication paths, a frame head data is generated and inserted with a predetermined generation logic at a predetermined timing to indicate frame head data indicating the head of the data. Insertion means
The serial data transmission device according to claim 1, further comprising: The frame head insertion means is configured to calculate the predetermined logical calculation based on values indicated by the plurality of bits transmitted at the second clock timing for the frame head data transmitted using the plurality of serial data communication paths. The frame head data is generated so that the result of performing repetitive inversion after maintaining the value over a predetermined bit interval,
The serial data transmission device according to claim 3. The generating means performs an exclusive OR as the predetermined logical calculation.
The serial data transmission device according to claim 1. A value indicated by a plurality of bits received at the same clock timing via the plurality of serial data communication paths when receiving data from the serial data transmission device via the plurality of serial data communication paths operating in synchronization A synchronous timing detecting means for generating a signal for adjusting a clock timing for fetching the plurality of bits based on a timing at which a result of performing a predetermined logical calculation based on the timing is inverted;
A serial data receiving device. A conversion integration means for integrating serial data received via the plurality of serial data communication paths into parallel data sets, and then integrating the plurality of parallel data sets into one,
The serial data receiving device according to claim 6, further comprising: Frame head detection means for detecting the frame head data based on a predetermined detection logic from the data including the frame head data indicating the head received via the plurality of serial data communication paths,
The serial data receiving device according to claim 6 or 7, further comprising: Depending on the information processing device,
When transmitting data to a serial data receiving device using a plurality of serial data communication paths that operate in synchronization, the data flowing through any of the plurality of serial data communication paths is time-sequential Inserting synchronization control bits so as to be distributed among the plurality of serial data communication paths every bit interval,
The serial data receiving device uses a result obtained by performing a predetermined logical calculation based on values indicated by a plurality of bits received at a first clock timing via the plurality of serial data communication paths. Result of performing the predetermined logical calculation based on the value indicated by the synchronization control bit transmitted at the second clock timing and one or more bits excluding the synchronization control bit when adjusting the timing of fetching bits Generating the synchronization control bit so as to be inverted from the result of performing the predetermined logic calculation based on a plurality of bits transmitted at the clock timing immediately before the second clock timing.
Serial data transmission method. When transmitting data to a serial data receiving device using a plurality of serial data communication paths that operate in synchronization, the data flowing through any of the plurality of serial data communication paths is time-sequential Control bit insertion processing for inserting synchronization control bits so as to be distributed among the plurality of serial data communication paths for each bit interval;
The serial data receiving device uses a result obtained by performing a predetermined logical calculation based on values indicated by a plurality of bits received at a first clock timing via the plurality of serial data communication paths. Result of performing the predetermined logical calculation based on the value indicated by the synchronization control bit transmitted at the second clock timing and one or more bits excluding the synchronization control bit when adjusting the timing of fetching bits Generating processing for generating the synchronization control bits so as to be inverted from the result of performing the predetermined logic calculation based on a plurality of bits transmitted at the clock timing immediately before the second clock timing;
Serial data transmission program that causes a computer to execute.

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