JPH04216233A - Frame synchronizing device - Google Patents

Abstract

PURPOSE:To shorten time for the acquisition of synchronism when synchronizing frames on the reception side at a transmitter to transmit information in an mBIC1 code form. CONSTITUTION:A frame synchronizing signal generating circuit 12 and (2:1) selector circuits 13 and 14 are provided on the transmission side, and one frame period is divided into plural sub frame period. Then, the bit value of a frame synchronizing signal and a non-complementary bit are alternately inserted to the leading bit position of each sub frame period and transmitted and on the reception side, synchronism is established by investigating the leading bit position of each sub frame period by a frame synchronizing circuit.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a frame synchronization device used in a backbone transmission system, a subscriber system transmission system, a digital transmission system such as a LAN, and more specifically, a second lane signal sequence, an m-th (where m is any integer) lane signal sequence, and a signal sequence of complementary bits of each bit constituting the m-th lane signal sequence. a multiplex conversion circuit that receives a complement lane signal series in parallel and converts it into a serial signal and outputs the same; In a transmission device comprising a demultiplexing circuit that separates a lane signal sequence, an m-th lane signal sequence, and the complementary lane signal sequence, a transmission side (multiplex conversion circuit side) and a reception side (demultiplex This invention relates to a frame synchronization device for synchronizing frames with the circuit (circuit side).

0002

[Background Art] The transmission speed of optical fiber transmission systems, which have excellent characteristics as a transmission medium, has improved dramatically, and transmission systems with transmission speeds of several Gb/s are being actively studied. ing.

[0003] One such transmission system uses mB1C code as a transmission line code, and detects code rule violation (Co
By detecting RuleViolation (CRV), synchronization is achieved for every (m+1) bits,
(m+1) low-speed information sequences (hereinafter referred to as lanes)
A method has been proposed that attempts to simplify processing and reduce the size of the circuit by dividing the circuit into two parts and reducing the subsequent processing speed. Regarding this technology, "Study of ultrahigh-speed multiplexing and demultiplexing circuits" published by Osamu Yokota et al. in Volume 3 of the 1990 IEICE General Conference National Conference Proceedings, p. 3-352.

[0004] Here, the mBC1 code will be briefly explained. Assume that m serial information bits (m is any integer) are selected from a series of serial information bits. In this m-bit information string, if the m-th bit is 1, its complement is 0;
Then, by creating 1 as its complement as a complementary code (C bit) and adding it as the (m+1)th bit to the end of the m-bit information string, the total number is (m+1).
When we create a code consisting of bits, we call this code mB1
It is called the C code. Information transmission using the mB1C code format is used for reasons such as realizing perfect operation of repeaters on the transmission path.

When transmitting information as a series of mB1C codes, a bit that is not a complementary code (a bit with the same logical value as the m-th bit) is intentionally inserted into the bit position where the complementary code (C bit) should normally be. As described above, a violation of the coding rule is caused on the transmitting side, and the receiving side detects the bit position of the violation of the coding rule and synchronizes with the transmitting side.

Now, in the method described above, as a synchronization method for synchronizing frames when digital transmission is performed by time division multiplexing in each lane after dividing into lanes, the Institute of Electronics, Communication and Information Engineers technique CS89-55 is used. m
As an example, the configuration diagram when applying the frame synchronization method using CRV published by Hideo Tatsuno and others in ``Study of Cell Synchronization Method Using B1C Code Violation'', p. 13-18, is given as m= Case 3 is shown in FIG.

In FIG. 4, 1a is the first lane input signal, 1b is the second lane input signal, 1c is the third lane input signal, 1d is the fourth lane input signal, and 1e is the complement of the third lane input signal 1c. C bit as, 2 is inverter,
3 is a (2:1) selector, 3a is a (2:1) selector 3
3b is the second input terminal of (2:1) selector 3.
3c is the control input terminal for switching the input terminal of the (2:1) selector 3, 3d is the output terminal of the (2:1) selector 3, 4 is the multiplex conversion circuit, and 4a is the multiplex conversion circuit 4. The first input terminal 4b is the second input terminal of the multiplex conversion circuit 4.
4c is the third input terminal of the multiplex conversion circuit 4,
4d is a fourth input terminal of the multiplex conversion circuit 4, 4e is an output terminal of the multiplex conversion circuit 4, and 5 is a frame synchronization pulse.

6 is a transmission line, 7 is a demultiplexer circuit, 7a is a first output terminal of the demultiplexer circuit 7, and 7b is a demultiplexer circuit 7.
7c is the third output terminal of the demultiplexer circuit 7, 7d is the fourth output terminal of the demultiplexer circuit 7, 7e is the CRV output terminal of the demultiplexer circuit 7, and 7f is the third output terminal of the demultiplexer circuit 7. 8a is the first lane output signal of the demultiplexer circuit 7; 8b is the second lane output signal of the demultiplexer circuit 7;
c is the third lane output signal of the demultiplexer circuit 7, 8d is the fourth lane output signal (frame lane signal to be described later) of the demultiplexer circuit 7, 8e is the CRV, 9 is the frame synchronization circuit, 10
is the frame sync pulse.

The flow of this signal is as follows. FIG. 5 is a waveform diagram showing the relationship between signals of each lane to explain the conventional technique shown in FIG. In Figure 4, (2:1
) The frame synchronization pulse 5 applied to the control input terminal 3c of the selector 3 causes the third lane input signal 1c, which is the input signal to the input terminal 3b, to be output from the input terminal 3b at the first bit position of the frame every frame period. The selector 3 is controlled (2:1) so that it is output to the terminal 3d, and the third lane input signal 1c is output at bit positions other than the beginning of the frame.
The (2:1) selector 3 is controlled so that a signal as a complementary code obtained by inverting the logic of , that is, a C bit 1e which is the complement of the third lane input signal 1c is outputted.

As a result of the above control, the fourth lane input signal 1d which is the output of the selector 3, that is, the frame lane signal 1d consisting of a series of C bits, starts from a certain bit position and starts at a certain bit position, as shown in FIG. One frame is constructed, and in the first bit position of the frame, CRV (a bit that is not a complementary code,
In other words, bits that violate the coding rule are inserted. 1st lane input signal 1a to 3rd lane input signal 1c
After obtaining frame synchronization with the frame bit F in the frame lane signal 1d, the first to fourth lane signals are sequentially bit-multiplexed in the multiplex conversion circuit 4 and sent to the transmission line 6.

The bit-multiplexed lane input signal is inputted from the transmission line 6 to the demultiplexing circuit 7, where a sign rule check is performed between the third lane output signal 8c and the fourth lane output signal 8d, and multiplex conversion is performed. Lane synchronization is performed so that the correspondence between the lane input signal in the circuit 4 and the lane output signal in the demultiplexing circuit 7 is correct, and further synchronization is performed in the frame synchronization circuit 9.

The frame synchronization circuit 9 generates frame synchronization pulses by performing frame synchronization as follows. The frame synchronization circuit 9 uses the frame lane signal 8d after lane synchronization and the code rule inspection result performed between the third lane output signal 8c and the frame lane signal 8d in the demultiplexing circuit 7. A CRV 8e representing a code rule violation bit is input. With CRV 8e, ■ As mentioned above, when a CRV intentionally inserted at each frame period is detected on the transmitting side, and ■ When a code error occurs due to noise, disturbance, etc., it appears to be a CRV. It can be classified according to the case. The CRV generation interval (2) has a periodicity that occurs every frame period, and this periodicity is used to establish frame synchronization and generate the frame synchronization pulse 10. Regarding the apparent CRV that occurs due to the cause mentioned above, it is possible that it is a false CRV.
A rear protection circuit and a front protection circuit are installed to detect the

[0013]

[Problem to be solved by the invention] In the prior art,
Because of the above configuration, if the bit length of one frame is k and the length of one frame expressed in time is T, then by shifting one bit at a time within one frame, the corresponding bit in the adjacent frame and CRV are Since it is checked whether or not the points match, the worst case, that is, the maximum frame synchronization recovery time Ts is expressed by the following equation (1). Ts=kT (1)

0014
That is, with such a configuration, in order to detect a frame synchronization pattern, hunting for one frame is necessary at worst, and the time required for simultaneous acquisition is disadvantageous. SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art and to provide a frame synchronization device that takes a short time to acquire synchronization in a transmission device that uses the mB1C coding method.

[0015]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a first lane signal series, a second lane signal series, and an mth lane signal sequence (where m is an arbitrary integer). a multiplex conversion circuit that inputs a signal sequence and a complementary lane signal sequence consisting of a signal sequence of complementary bits of each bit constituting the m-th lane signal sequence in parallel, converts it into a serial signal, and outputs the serial signal; Receive the serial signal from the multiplex conversion circuit and separate it into a first lane signal series, a second lane signal series, an m-th lane signal series, and the complementary lane signal series. a demultiplexing circuit; a synchronizing signal generating means for generating a frame synchronizing signal having different logic values in the first half and the second half of one frame period; In a lane signal series, one frame period is divided into a plurality of subframe periods, and at each bit position of each subframe period, instead of the complement bit at the corresponding bit position, a signal corresponding to the corresponding bit position of the frame synchronization signal is added. A means is provided for alternately inserting a sample value at a bit position and a non-complement bit, and inputting the sample value and a non-complement bit to the multiplexing conversion circuit as a frame lane signal series, and the multiplexing/demultiplexing circuit receives a signal from the separated frame lane signal series. Detecting the sample value of the synchronization signal inserted at every other bit position of each subframe period in the subframe period, and detecting the first bit position at which it switches from one logical value to the other logical value. A means for establishing synchronization is provided.

[0016]

[Function] As a result, synchronization can be achieved with a smaller number of hunting operations, compared to the prior art that required hunting for one frame in the worst case, and the time required for synchronization has been significantly shortened.

[0017]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a portion 11 surrounded by a broken line shows the relationship between the C bits of the third lane output signal 8c and the fourth lane output signal 8d (
This is a part that performs lane synchronization so that the correspondence between the lane input signal in the multiplex conversion circuit 4 and the lane output signal in the demultiplexer circuit 7 is correct.
Since the configuration and operation are exactly the same as those of the prior art, the explanation will be omitted. The same numbers as in FIG. 4 indicate the same components.

In FIG. 1, as signals output from the frame synchronization circuit 9, 10a is a frame synchronization pulse;
0b is a double subframe period synchronization pulse, and 10c is a second subframe period synchronization pulse.

12 is a frame synchronization signal generation circuit; 12a;
is a frame synchronization signal, 12b is a frame synchronization pulse, 1
2c is a subframe period synchronization pulse, 12d is a double subframe period synchronization pulse, 13 is a first (2:1) selector, 13a is a first input terminal of the first (2:1) selector 13, 13b is the second input terminal of the first (2:1) selector 13, and 13c is the first (2:1) selector 13.
13d is the output terminal of the first (2:1) selector 13, 14 is the second (2:1) selector, and 14a is the second (2:1) selector. 14 first input terminal, 14b is the second (2:1)
The second input terminal of the selector 14, 14c, is the second input terminal (2:
1) A control input terminal for switching the input terminal of the selector 14; 14d is an output terminal of the second (2:1) selector 14;

FIG. 2 is a diagram showing the timing of the frame lane signal 1d and other signals for explaining one embodiment of the present invention shown in FIG. Comparing the frame lane signal 1d according to the present invention shown in FIG. 2 with the frame lane signal (fourth lane input signal) 1d according to the prior art shown in FIG. Then, one frame period is divided into multiple subframe periods (1, 2, 3, ..., n), and each bit position of each subframe period is replaced with the complement bit at that bit position, and the frame period described later is It will be recognized that the difference is that the sample value F at the bit position corresponding to the bit position of the synchronization signal and the non-complement bit CRV are inserted alternately.

Refer to FIGS. 1 and 2. The frame synchronization signal generation circuit 12 includes a frame synchronization signal 12a, a frame synchronization pulse 12b, and a subframe period synchronization pulse 12c.
and generates a double subframe period synchronization pulse 12d.

The double subframe period synchronization pulse 12d is transmitted to the first (2:1) selector 1 every double subframe period.
At the first bit position of the double subframe period (12d), the sample value F at the corresponding bit position of the frame synchronization signal 12a is applied to the control input terminal 13c of the frame synchronization signal 12a.
is output to its output terminal 13d, and at bit positions other than the beginning of the double subframe period, the third lane input signal 1
The first (
2:1) Control the selector 13.

The subframe period synchronization pulse 12c is applied to the control input terminal 14c of the second (2:1) selector 14 every subframe period, and at the beginning of the subframe, the input signal to the input terminal 14b, ie, The sample value of the frame synchronization signal 12a or the third lane input signal 1c is output to its output terminal 14d, and at bits other than the beginning of the subframe, a signal obtained by inverting the logic of the third lane input signal 1c, that is, the third lane input signal 1c, is outputted to the output terminal 14d. Input signal 1c
so that the C bit 1e as the complement signal of
A second (2:1) selector 14 is controlled.

That is, as a result of the above control, the frame lane signal 1d consisting of the C bit (complement signal), frame bit F and CRV becomes (m
+1) The configuration is divided into subframes for each bit (in this example, every 4 bits). To explain in more detail, the sample value F of the frame synchronization signal 12a is inserted into the first bit position of the odd-numbered subframe,
CRV is placed in the first bit position of even-numbered subframes.
will be inserted, and the C bit will be inserted into the other remaining bit positions. Therefore, a frame can be constructed by inserting a specific pattern as the frame synchronization signal 12a in FIG.

Hereinafter, in the present invention, the frame synchronization signal 12a
When adopting a signal that is "1" in the first half frame period from the beginning of the frame and "0" in the second half frame period, that is, the frame synchronization signal 12a changes from "0" to "0". A method for establishing frame synchronization will be described in the case where the timing at which the value changes to 1'' is recognized as the beginning of the frame.

The frame synchronization pulse 12b is generated at the time when the frame synchronization signal 12a changes from "0" to "1", and the first lane input signal 1a to third lane input signal 1c are synchronized with this frame synchronization pulse 12b. It is synchronized and transmitted.

The frame synchronization circuit 9 generates a frame synchronization pulse 10a to indicate the establishment of synchronization according to the flowchart shown in FIG. The frame synchronization circuit 9 uses the frame lane signal 8d after lane synchronization and the code rule inspection result performed between the third lane output signal 8c and the frame lane signal 8d in the demultiplexing circuit 7. A CRV 8e is input indicating a violation of the sign rule.

[0028] CRV 8e has the following functions: ■ When a CRV intentionally inserted at the start bit position of an even-numbered subframe on the transmitting side is detected every twice the subframe period, ■ CRV inserted at the start bit position of an odd-numbered subframe is detected. If the sample value of the frame synchronization signal inserted every double subframe period happens to be an apparent CRV due to its logical value, or ■ If a code error occurs due to noise, disturbance, etc. It can be classified if it becomes CRV. The CRV generation interval in (2) has a periodicity that occurs every double subframe period, and this periodicity is used to establish double subframe period synchronization and generate the double subframe period synchronization pulse 10b. generate. Here, since an apparent CRV may occur due to the causes of (1) and (2) above, it is of course necessary to provide a rear protection circuit and a front protection circuit to avoid errors caused by this.

In the frame synchronization circuit 9, as shown in step S1 in FIG. generates a second double subframe period synchronization pulse 10c shifted by π, and checks the bits of the frame lane signal 8d every period of this second double subframe period synchronization pulse 10c (
Step S2). The first test result after starting the test is “1”
In this case, expect 1/2 frame cycle (step S4
) to the second double subframe period synchronization pulse 10 again
The bit of the frame lane signal 8d is inspected every cycle c (step S5), and if the inspection result is "0", the next cycle's inspection is performed, and when the inspection result is "1", frame synchronization is performed. Generate pulse 10a to establish frame synchronization (
Step S7). Thereafter, a frame synchronization pulse is generated for each frame.

On the other hand, if the first test result after the start of the test (step S3) is "0", the bits of the frame lane signal 8d are checked again every cycle of the second double subframe period synchronization pulse 10c. (step S5), and if the test result is "0", the next cycle test is performed, and when the test result becomes "1" for the first time (step S6), a frame synchronization pulse 10a is generated to synchronize. Establishment (step S7
), and thereafter a frame synchronization pulse is generated for each frame. Frame synchronization is established as described above.

Since the configuration is as described above, if the bit length of one frame is k, the length of one frame expressed in time is T, and the number of subframes is n, the maximum frame synchronization recovery time Ts is as follows. It is expressed by equation (2). Ts = Double subframe period synchronization establishment time
+ When the first test result is “1” after starting the test 1/
Time to wait for 2 frames + time to check frame bits every second double subframe period = (T/n) x (k/n) + T/2
+(T/n)×(n/2) =(kT/
n2)+T

On the other hand, according to the above formula (1), when the conventional technique is applied, the maximum frame synchronization recovery time Ts
is kT, and it can be seen that the maximum frame synchronization recovery time can be significantly reduced by applying the present invention. In the above explanation, the case where m=3 was explained for convenience, but it is clear that the case where m is any integer also holds true.

[0033]

[Effects of the Invention] As explained above, according to the present invention,
There is an advantage that a frame synchronization device with a short frame synchronization recovery time can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing diagram showing the timing of each part signal in FIG. 1;

FIG. 3 is a flowchart showing operations performed by the frame synchronization circuit in FIG. 1;

FIG. 4 is a block diagram showing the configuration of a conventional frame synchronization device.

FIG. 5 is a timing diagram showing the timing of each part signal in FIG. 4;

[Explanation of symbols]

1a...First lane input signal 1b...Second lane input signal 1c...Third lane input signal 1d...Fourth lane input signal 1e...C bit of third lane input signal 2...Inverter 3...(2:1) selector 3a ...(2:1) Selector's first input terminal 3b...(2
:1) Second input terminal 3c of the selector...(2:1) Control input terminal 3d of the selector...(2:1) Output terminal 4 of the selector...Multiple conversion circuit 4a...First input terminal 4b of the multiple conversion circuit ...Second input terminal 4c of the multiplex conversion circuit...Third input terminal 4d of the multiplex conversion circuit...Fourth input terminal 4e of the multiplex conversion circuit...Output terminal 5 of the multiplex conversion circuit...Frame synchronization pulse 6...Transmission line 7 ...Demultiplexer circuit 7a...First output terminal 7b of the demultiplexer circuit...Second output terminal 7c of the demultiplexer circuit...Third output terminal 7d of the demultiplexer circuit...Fourth output terminal 7e of the demultiplexer circuit... CRV output terminal 7f of the demultiplexer circuit...Input terminal 8a of the demultiplexer circuit...First lane output signal 8b of the demultiplexer circuit...Second lane output signal 8c of the demultiplexer circuit...Third signal of the demultiplexer circuit
Lane output signal 8d...Fourth lane output signal of the demultiplexing circuit (frame lane output signal) 8e...CRV 9...Frame synchronization circuit 10...Frame synchronization pulse 10a...Frame synchronization pulse 10b...Double subframe period synchronization pulse 10c...th Second subframe period synchronization pulse 11...Multiple conversion circuit, transmission line and demultiplexing circuit 12...Frame synchronization signal generation circuit 12a...Frame synchronization signal 12b...Frame synchronization pulse 12c...Subframe period synchronization pulse 12d...Double subframe period Synchronous pulse 13...first (2:1) selector 13a...first input terminal 1 of first (2:1) selector
3b...Second input terminal 13 of the first (2:1) selector
c... Control input terminal 13d of the first (2:1) selector...
Output terminal 14 of the first (2:1) selector...second (2:1) selector
:1) Selector

Claims (1)

[Claims] Claim 1: A first lane signal sequence, a second lane signal sequence, an m-th (where m is any integer) lane signal sequence, and the m-th lane signal sequence are configured. a complementary lane signal series consisting of a signal series of complementary bits of each bit, and a multiplex conversion circuit that is input in parallel and converts it into a serial signal and outputs it; a th lane signal sequence, a second lane signal sequence, an mth lane signal sequence,
In a transmission device comprising the complementary lane signal sequence and a multiplexing/demultiplexing circuit that separates it into two, a frame synchronization signal whose logical value is different in the first half and the second half of one frame period is provided on the multiplex conversion circuit side. a synchronization signal generating means for generating, and in the complement lane signal sequence, one frame period is divided into a plurality of subframe periods, and at each bit position in each subframe period, in place of the complement bit at the bit position, means for alternately inserting a sample value at a bit position corresponding to the bit position of the frame synchronization signal and a non-complement bit, and inputting the sample value to the multiplex conversion circuit as a frame lane signal series; , from the separated frame lane signal sequence, detect the sample value of the synchronization signal inserted at every other bit position in each subframe period therein, and the sample value of the synchronization signal is changed from one logical value to the other. A frame synchronization device comprising means for establishing synchronization by detecting the first bit position that switches to a logical value.