RU2205445C1 - For data transmission device - Google Patents

Abstract

FIELD: synchronous telecommunication systems. SUBSTANCE: device has data receiving unit and data transmitting unit; data transmitting unit has sync signal generator, shift register, EXCLUSIVE OR gate, flip-flop, and two amplifiers; data receiving unit has two amplifiers, two pulse shapers, OR gate, phase-locked-loop frequency control unit, and flip-flop. EFFECT: enhanced data transmission speed. 1 cl, 9 dwg

Description

 The invention relates to devices for processing digital data using electrical devices, in particular to devices for transmitting data.

 A device [1] for transmitting data is known, comprising a data transmission unit and a data receiving unit connected to opposite sides of the communication channel, the data transmission unit comprises a clock signal generator, first and second shift registers and a multiplexer, outputs of the first and second shift registers are connected to the first via the multiplexer communication channel lines, the outputs of the clock generator are connected to the second communication channel line, to the control inputs of the first and second shift registers and the multiplexer, and are the first and second device synchronization outputs, parallel inputs of the first and second shift registers are the first and second groups of device data inputs, the data receiving unit contains the third and fourth shift registers and a clock generator, the input of which is connected to the second line of the communication channel, the serial data inputs of the third and fourth shift registers connected to the first line of the communication channel, the outputs of the shaper of the clock signals are connected to the control inputs of the third and fourth shift registers and are With the third and fourth outputs of the device synchronization, the parallel outputs of the third and fourth shift registers are the first and second groups of device data outputs.

 The device [1] is intended for synchronous data transmission over a communication channel. The data signal is transmitted along the first line of the communication channel, and the synchronization signal is transmitted along the second. The signals in the first and second lines of the communication channel are represented by two levels. The first level corresponds to the log. 0, the second is the log. 1. The data transmission unit generates a bit stream by sequentially issuing serial data from the first and second shift registers. In this case, the truth of the data bits transmitted to the communication channel is confirmed alternately by the positive and negative edges of the synchronization signal. The data receiving unit, in turn, receives bits in the third and fourth shift registers under the control of the positive and negative edges of the clock signal received from the communication channel.

 The disadvantages of the device [1] are the low data transfer rate and the increased level of generated crosstalk. With a clock frequency of F (Hz), the data rate is 2F (bit / s). The increased level of generated crosstalk is due to the fact that the frequency component F dominates in the energy spectrum of the clock signal. This component is transmitted to adjacent cable wires due to the presence of capacitive and inductive spurious connections and leads to the appearance of induced interference signals.

 A device [2] for data transmission, comprising a data transmission unit and a data receiving unit connected to opposite sides of the communication channel, the data transmission unit comprises a clock generator, a shift register, an exclusive OR element, a first trigger, first and second amplifiers, a first output of a clock generator is the first synchronization output of the device, the second output of the clock generator is connected to the inputs of the synchronization of the shift register and the first trigger, the data input of the shift register is the first input of the device data, the first output of the shift register is connected to the first input of the exclusive-OR element and through the first amplifier to the first line of the communication channel, the second output of the shift register is connected to the second input of the exclusive-OR element, the single output of the first trigger through the second amplifier is connected to the second line the communication channel, the data receiving unit contains the third and fourth amplifiers, the first and second pulse shapers, the first OR element, the phase-locked loop and the second trigger, the inputs of the third and h fourth amplifiers are connected to the first and second lines of the communication channel, the outputs of the third and fourth amplifiers through the first and second pulse shapers are connected to the inputs of the first OR element, the output of which is connected to the input of the phase-locked loop, the output of which is the second synchronization output of the device and connected to the input synchronization of the second trigger, the single output of which is the first data output of the device, the data input of the second trigger is connected to the output of the third amplifier.

 The device [2] is intended for synchronous data transmission over a communication channel. The data signal is transmitted along the first line of the communication channel, and the synchronization signal is transmitted along the second. The signals in the first and second lines of the communication channel are represented by two levels. The first level corresponds to the log. 0, the second is the log. 1. The data transmission unit generates a bit stream by issuing serial data from the shift register. In this case, the clock signal is formed in such a way that its edges determine the boundaries of the bit intervals during the transmission of the same name bits. The data receiving unit restores the original clock signal from the set of signal edges in the lines of the communication channel.

 The disadvantage of the device [2] is the low data rate. The maximum frequency of signals in the first or second lines of the communication channel is F (Hz), the minimum frequency is zero. In this case, the signals complement each other. The data rate is constant and equal to 2F (bit / s).

 The purpose of the invention is to increase the data transfer rate.

 The goal is achieved in that in a device for transmitting data comprising a data transmission unit and a data receiving unit connected to opposite sides of the communication channel, the data transmission unit comprises a clock signal generator, a shift register, an exclusive OR element, a first trigger, first and second amplifiers, a first output the clock generator is the first synchronization output of the device, the second output of the clock generator is connected to the synchronization inputs of the shift register and the first trigger, the data input of the shift reg the country is the first input of the device data, the first output of the shift register is connected to the first input of the Exclusive OR element and through the first amplifier to the first line of the communication channel, the second output of the shift register is connected to the second input of the Exclusive OR element, the single output of the first trigger through the second amplifier is connected to the second line of the communication channel, the data receiving unit contains the third and fourth amplifiers, the first and second pulse shapers, the first OR element, the phase-locked loop and the second trigger, input The odes of the third and fourth amplifiers are connected to the first and second lines of the communication channel, the outputs of the third and fourth amplifiers are connected through the first and second pulse shapers to the inputs of the first OR element, the output of which is connected to the input of the phase-locked loop, the output of which is the second synchronization output of the device and connected to the synchronization input of the second trigger, a single output of which is the first data output of the device, the data input of the second trigger is connected to the output of the third amplifier, the data transfer unit additionally contains a third trigger, an AND element and a multiplexer, the output of the Exclusive OR element is connected to the data input of the third trigger, the output of which is connected to the control input of the multiplexer and to the first input of the And element, the output of which is the third synchronization output of the device, the first data input of the multiplexer is the second data input of the device, the second data input of the multiplexer is connected to the zero output of the first trigger, the data input of which is connected to the output of the multiplexer, the first you the clock generator path is connected to the second input of the And element, the third output of the clock generator is connected to the synchronization input of the third trigger, the data receiving unit further comprises a third pulse shaper, a fourth, fifth and sixth triggers and a second OR element, the output of which is the fourth synchronization output of the device, inputs of the second OR element are connected to the outputs of the fourth and fifth triggers, the zero-setting inputs of which are connected to the output of the third pulse shaper, and the synchronization inputs and - with the single and zero outputs of the second trigger, the data inputs of the fourth and fifth triggers are connected to the positive voltage bus, the input of the third pulse shaper is connected to the output of the phase locked loop and to the synchronization input of the sixth trigger, the data input of which is connected to the output of the fourth amplifier, the output The sixth trigger is the second data output of the device.

 In FIG. 1 is a timing chart explaining data transmission methods used when using the known and proposed devices; in FIG. 2 is an example of a circuit for incorporating the proposed device into a telecommunication system; figure 3 is a structural diagram of a data transmission unit; figure 4 is a structural diagram of a block for receiving data; figure 5 is a timing diagram of the signals of the data transmission unit; 6 is a timing diagram of the signals of the data receiving unit.

 Timing diagrams 1 and 2 (Fig. 1, a) correspond to DATA and CLK synchronization data signals generated in accordance with the generally accepted method of sequential synchronous data transmission, see, for example, ITU-T Recommendations (ITU-T) V.24, V .28. Timing diagrams 3 and 4 (Fig. 1, b) correspond to the DATA and CLK clock signals used in the device [I]. Timing diagrams 5 and 6 (FIG. 1, c) correspond to DATA and CLK synchronization signals received in the device [2]. Timing diagrams 7 and 8 (Fig. 1, g) correspond to the data signals DATA and synchronization CLK, adopted in the proposed device. (As will be shown, the CLK signal shown in diagram 8 is used not only for its intended purpose).

 The telecommunication system (figure 2) contains the proposed device 9 for data transmission and connected to it, the first - fourth 10-13 terminal devices DTE1 - DTE4. The device 9 contains connected to the opposite sides of the communication channel 14, the data transmission unit 15 (DCE1) and the data reception unit 16 (DCE2). The communication channel 14 contains the first 17 and second 18 communication lines. The outputs 19 and 20 of blocks 15 and 16 are the first and second outputs of the synchronization device 9. The outputs 21 and 22 of the blocks 15 and 16 are the third and fourth outputs of the synchronization device 9. The inputs 23 and 24 of the block 15 are the first and second data inputs of the device 9. The outputs 25 and 26 of block 16 are the first and second data outputs of device 9.

 The data transmission unit (Fig. 3) contains a clock generator 27, a shift register 28, an exclusive OR element 29, a first trigger 30, a first 31 and a second 32 amplifiers, the first output 33 of the clock generator is the first output 19 of the device synchronization, the input 34 of the shift register data 28 is the first input 23 of the device data, the first output 35 of the shift register 28 is connected to the first input of the exclusive OR 29 element and through the first amplifier 31 to the first line 17 of the communication channel 14, the second output 36 of the shift register 28 is connected to the second input m element Exclusive OR 29, a single output of the first trigger 30 through the second amplifier 32 is connected to the second line 18 of the communication channel 14.

 The data transmission unit also contains a third trigger 37, an AND 38 element and a multiplexer 39, the output of the Exclusive OR element 29 is connected to the data input of the third trigger 37, the output of which is connected to the control input of the multiplexer 39 and the first input of the And 38 element, the output of which is the third output 21 of the device synchronization, the first data input 40 of the multiplexer 39 is the second input 24 of the device data, the second data input 41 of the multiplexer 39 is connected to the zero output of the first trigger 30, the data input of which is connected to the output of the multiplex Ora 39, the first output 33 of the clock generator 27 is connected to the second input of the And 38 element, the second output 42 of the clock generator 27 is connected to the synchronization inputs 43 and 44 of the shift register 28 and the first trigger 30, the third output 45 of the clock generator 27 is connected to the synchronization input of the third trigger 37.

 The data receiving unit (Fig. 4) contains the third 46 and fourth 47 amplifiers, the first 48 and second 49 pulse shapers, the first OR element 50, the phase-locked loop 51 and the second trigger 52, the inputs of the third 46 and fourth 47 amplifiers are connected to the first 17 and the second 18 lines of communication channel 14, the outputs of the third 46 and fourth 47 amplifiers through the first 48 and second 49 pulse shapers are connected to the inputs of the first element OR 50, the output of which is connected to the input of the phase-locked loop 51, the output of which is the second output 20 syn device synchronization and is connected to the synchronization input of the second trigger 52, the single output of which is the first output 25 of the device data, the data input of the second trigger 52 is connected to the output of the third amplifier 46.

 The data receiving unit also contains a third 53 pulse shaper, fourth 54, fifth 55 and sixth 56 triggers and a second OR 57 element, the output of which is the fourth output 22 of the device synchronization, the inputs of the second OR 57 element are connected to the outputs of the fourth 54 and fifth 55 triggers, inputs the zero settings of which are connected to the output of the third 53 pulse shaper, and the synchronization inputs are with the single and zero outputs of the second trigger 52, the data inputs of the fourth 54 and fifth 55 triggers are connected to the positive voltage bus 58, they diruyuschego signal log. 1, the input of the third pulse shaper 53 is connected to the output of the phase-locked loop 51 and to the synchronization input of the sixth trigger 56, the data input of which is connected to the output of the fourth amplifier 47, the output of the sixth trigger 56 is the second data output of the device.

 Timing diagrams 59, 60 and 61 (Fig. 5) correspond to the signals at the outputs 33, 42 and 45 of the generator 27 of block 15. Timing diagrams 62, 63 and 64 display the signals at points 34, 36 and 35 of block 15. Timing diagrams 65, 66 and 67 correspond to the signals at the input of the data of the trigger 37, at the output of this trigger and at the output of the And 38 element. Timing diagrams 68 and 69 correspond to the signals at the input 24 and the output 18 of block 15.

 Timing diagrams 70 and 71 (Fig.6) display the signals at the inputs 17 and 18 of block 16. Timing diagrams 72 - 76 correspond to the signals at the outputs of the pulse shapers 48, 49, at the input and output of the block 51 and at the output of the pulse shaper 53. Timing diagrams 77-81 display the signals at the output 25, at the inputs of the OR element 57 and at the outputs 22 and 26 of block 16.

 The following describes the data transfer methods used when using known (Fig. 1, a - c) and the proposed (Fig. 1, d) devices.

 As shown in FIG. 1a-d, two signals are transmitted from the transmitter to the receiver: DATA (diagrams 1, 3, 5, 7) and CLK (diagrams 2, 4, 6, 8). The DATA signal is designed to transmit a serial stream of data bits. In the example shown in FIG. 1, each bit from the sequence 01011100110 is allocated a so-called bit interval. The boundaries between bit intervals are shown by dashed lines in the diagrams. Signals log. 1 and the log. 0 in this example corresponds to high and low voltage.

 The synchronization signal CLK in known devices is formed in different ways, but in all the considered cases it is used only for its intended purpose - to delimit bit intervals. In the proposed device, the CLK signal is used both for its intended purpose and (at the same time) to transmit an additional data stream.

 When transmitting data according to timing diagrams 1 and 2 of FIG. 1a, on the positive edge of the CLK clock signal, the transmitter starts issuing the next data bit. On the negative edge of this clock signal, the receiver device fixes the received bit. The clock source can be structurally located in the transmitter, receiver, or outside of both.

 When transmitting data according to time charts 3 and 4 of FIG. 1b, the truth of the transmitted DATA data bits is confirmed alternately by the positive and negative edges of the CLK signal. In other words, the positive and negative edges of the CLK signal correspond to the steady-state values of the data signal used by the receiver to fix the bits (for example, in one or two shift registers). The boundaries of the bit intervals are offset from the edges of the CLK signal by a quarter of the period of this signal. Compared with the previous data transmission method, the frequency of the CLK signal is halved while maintaining the same data rate.

 When transmitting data according to time charts 5 and 6 of FIG. 1c, the CLK synchronization signal changes only in those cases when the DATA signal remains unchanged. Thus, at any boundary of the bit interval, either the DATA signal or the CLK signal changes. The receiver monitors changes in these signals and always has information about the location of the bit boundaries. Compared to the previous data transmission method, this method “equalizes” the energy spectrum of the CLK signal. Now it does not contain a pronounced spectral line, which helps to reduce the level of generated crosstalk affecting adjacent cable wires.

 The data transfer method used in the proposed device (see Fig. 1, d) is close to just described (see Fig. 1, c). Similarly, the "missing" edges of the DATA signal are supplemented by guaranteed edges of the CLK signal. But in this case, the CLK signal is not “idle without information load” and, if possible, is used to transmit an additional data stream.

 Comparing timing diagrams 6 and 8, it can be noted that during the first four bit intervals, the CLK signal can be used as a “vehicle” to transmit four additional bits D1-D4. These bits, of course, can have arbitrary values. In particular, they can all be zero or one. This "freedom of choice" is possible due to the fact that the DATA signal during this period varies in each bit interval and is used by the receiver to recognize the inter-bit boundaries.

 After the D1-D4 bits are transmitted, a guaranteed difference in CLK signal levels is created, since the DATA signal remains unchanged. This is achieved by inverting the D4 bit. Further, the bit is inverted again, since the DATA signal is still unchanged, then the D5 bit is transmitted, etc. Guaranteed changes in the state of the CLK signal correspond to the vertical arrows in the figure. Thus, in this example, the CLK signal additionally “transfers” D1-D7 data simultaneously with the transmission of the “main” data by the DATA signal.

 With the equally probable occurrence of signals log. 0 and log. 1 in the DATA data stream (which can be achieved by its preliminary scrambling), the throughput of the additional data channel is 50% of the throughput of the main channel. Indeed, the probability of a difference in the levels of the DATA signal at the boundary of bit intervals i and j is 0.5 and does not depend on the history. But it is precisely this probability that determines the event of the “insertion” of the next bit D into the CLK signal stream. Thus, on average, every second bit interval is suitable for transmitting an additional data bit. As a result, the total throughput (or data transfer rate) of the proposed device compared to the prototype increased by 1.5 times.

 The following is an example of a circuit for incorporating the proposed device into a telecommunication system.

 The proposed device 9 for data transmission (figure 2) is connected to four terminal devices DTE1 (10) - DTE4 (13), for example, to four computers. During the operation of the system, data is transferred from device 10 to device 12 via the main data channel. At the same time, through an additional channel, data is transferred from device 11 to device 13. (To transfer data in the opposite direction, the second device 9, turned on in the opposite direction, is necessary).

 A pair of TxC1-TxDl signals (TxC2-TxD2) provides synchronous data transmission from device 10 (11) to block 15. The positive edges of the TxC1 (TxC2) signal define the boundaries of bit intervals. On the negative edges of the signal TxC1 (TxC2), the corresponding data bit TxD1 (TxD2) is temporarily stored in block 15.

 A pair of signals RxC1-RxD1 (RxC2-RxD2) provides synchronous data transfer from block 16 to device 12 (13). The positive edges of the signal RxC1 (RxC2) specify the moments of the beginning of bit intervals. On the negative edges of the signal RxC1 (RxC2), the corresponding data bits RxD1 (RxD2) are stored in the device 12 (13).

 On the lines 17 and 18 of the communication channel 14, DL1 and DL2 signals are transmitted - analogues of the DATA and CLK signals shown in diagrams 7 and 8, Fig. 1, d. The communication channel 14 can be made in the form of two twisted pairs of wires, two fiber optic lines, or other means of signal transmission, including those containing repeaters.

 The following describes the operation of the data transfer unit 15 (see Figs. 3, 5).

 All processes occurring in the device are synchronized by signals from the generator 27. The signal CL1 (ТхС1) from the output 33 of the generator 27 is sent to the output 19 of the device and then transferred to the device DTE1 (10). In response to this signal, TxD1 data is output from the DTE1 device (10). They arrive at the input 23 of the device and then at the input 34 of the two-bit shift register 28. Under the influence of the positive edges of the signal CL2, the data moves in this register, is transmitted through the amplifier 31 to line 17, and at the same time they are analyzed by the exclusive OR 29 element. Until the bits in the register 28 are alternated (... 010101 ...), a signal V = 1 is generated, which enables the operation of the And 38 element. At its output 21, the ТхС2 clock signal is generated, in response to which the input 24 from the DTE2 (11) device TxD2 data bits of an additional transmission channel. These bits pass through the multiplexer 39, trigger 30, amplifier 32 and enter line 18.

 Detection by an Exclusive OR element of 29 identical bits in register 28 means that it is not possible to transmit the next “useful” bit on an additional channel (due to the lack of a difference in signal levels in the main channel). Therefore, work with the DTE2 device (11) is suspended by the signal V = 0. This signal locks the AND element 38 at the lower input and switches the multiplexer 39 to a state in which the trigger 30 operates in a counting mode, that is, in each cycle it inverts the bit stored in it. Thus, as already shown, the "missing" edges of the signal DL 1 are made up.

 The following describes the operation of the data receiving unit 16 (see Figs. 4, 6).

 Signals DL1 and DL2 (diagrams 70 and 71) enter block 16 from lines 17 and 18, pass through amplifiers 46, 47 and pulse shapers 48 and 49.

 The signal G (diagram 72) at the output of the pulse former 48 accompanies any change in signal DL1. In this example, the signal G contains no pulses at positions corresponding to the vertical arrows between diagrams 71 and 70. The signal H (diagram 73) at the output of the pulse former 49 accompanies any change in signal DL2. Since in this example, the DL2 signal is shown conditionally, without specifying a specific code, it is not known in advance whether the pulses marked with crosses in the diagram 73 will be generated. But on the other hand, it can be argued that the remaining pulses in this diagram will be necessarily formed, since they correspond to guaranteed changes in the DL2 signal when it is inverted. Thus, using the OR element 50, the "missing" pulses are made up, and the signal K is a periodic sequence of pulses without "gaps". This signal is fed to the synchronization input of the phase-locked loop 51.

Block 51 can be made according to one of the known schemes (see, for example, US Pat. No. 6,215,835 B1). It is designed to generate a highly stable clock signal S (RxC1) based on continuous monitoring of the input signal K. In this example, the negative edge of the signal S is “tied” to the positive edge of the signal K. Due to the sufficient “inertia” of block 51, the signal S is practically insensitive to phase jitter "the signal K and its other short-term distortions caused by interference in the communication channel. (Such use of a standard phase locked loop in telecommunication systems is generally accepted and will not be further described below.)
On the positive edge of signal S, the data received from lines 17 and 18 are recorded in triggers 52 and 56. The signals from the outputs of these triggers go to outputs 25 and 26 of block 16 and then to devices DTE3 (12) and DTE4 (13). As noted, the RxD2 signal contains not only "useful", but also "service" bits obtained by inverting the previous ones.

 The service bits of the RxD2 signal (marked with crosses in diagram 81), unlike the useful ones, are not accompanied by negative edges of the RxC2 signal and therefore are not perceived by the DTE4 device (13). For such “thinning out” of pulses, triggers 54, 55 and an OR element 57 are used. Trigger 54 is set to a single state at the positive edge of the signal RxD1, and trigger 55 is set at the negative edge of this signal. The return of these triggers to the zero state occurs under the influence of pulses J, which come from the pulse shaper 53 and correspond to the negative edges of the signal S. The signals P and Q from the outputs of the triggers 54 and 55 are summed by the OR element 57. Therefore, in the periods of the stability of the signal RxD1, the clock signal RxC2 is not generated , which is required for filtering service bits.

Sources of information
1. US patent 6269414 BL.

 2. US patent 6044421 (prototype).

Claims (1)

 A device for transmitting data, comprising a data transmission unit and a data receiving unit connected to opposite sides of the communication channel, the data transmission unit comprises a clock generator, a shift register, an EXCLUSIVE OR element, a first trigger, first and second amplifiers, a first output of a clock generator is a first synchronization output device, the second output of the clock generator is connected to the inputs of the synchronization of the shift register and the first trigger, the data input of the shift register is the first input m of device data, the first output of the shift register is connected to the first input of the EXCLUSIVE OR element and through the first amplifier to the first line of the communication channel, the second output of the shift register is connected to the second input of the EXCLUSIVE OR element, the single output of the first trigger through the second amplifier is connected to the second line of the channel The communication unit, the data receiving unit contains the third and fourth amplifiers, the first and second pulse shapers, the first OR element, the phase-locked loop and the second trigger, the inputs of the third and fourth amplifiers are connected to the first and second lines of the communication channel, the outputs of the third and fourth amplifiers are connected through the first and second pulse shapers to the inputs of the first OR element, the output of which is connected to the input of the phase-locked loop, the output of which is the second synchronization output of the device and connected to the synchronization input the second trigger, the single output of which is the first data output of the device, the data input of the second trigger is connected to the output of the third amplifier, characterized in that the unit The data transfer further comprises a third trigger, an AND element and a multiplexer, the EXCLUSIVE OR element output is connected to a third trigger data input, the output of which is connected to the control input of the multiplexer and to the first input of the AND element, the output of which is the third synchronization output of the device, the first data input of the multiplexer is the second data input of the device, the second data input of the multiplexer is connected to the zero output of the first trigger, the data input of which is connected to the output of the multiplexer, the first output is the clock signal generator is connected to the second input of the And element, the third output of the clock generator is connected to the synchronization input of the third trigger, the data receiving unit further comprises a third pulse shaper, a fourth, fifth and sixth triggers and a second OR element, the output of which is the fourth synchronization output of the device, inputs of the second OR elements are connected to the outputs of the fourth and fifth triggers, the zero-setting inputs of which are connected to the output of the third pulse shaper, and the synchronization inputs are connected to the single and zero outputs of the second trigger, the data inputs of the fourth and fifth triggers are connected to the positive voltage bus, the input of the third pulse shaper is connected to the output of the phase locked loop and to the synchronization input of the sixth trigger, the data input of which is connected to the output of the fourth amplifier, the output of the sixth trigger is the second output of the device data.

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