RU2271612C1 - Data transfer device - Google Patents

Abstract

FIELD: data transfer devices for synchronous communication systems.

SUBSTANCE: proposed device has data transmitting and data receiving units connected to opposing ends of communication line. Data transmitting unit has stuffing unit and scrambler; data receiving unit has descrambler and destuffing unit. Device is characterized in that data transmitting and receiving units are capable of simultaneously identifying definite codes in bit stream which are shaped into random (unknown in advance) time moments. These moments function in the first place as reference points in sorting out bits assigned to different channels and are used, in the second place, for synchronous setting scrambler and descrambler pseudorandom bit sequence generators to same states. In this way service bits for stream division among channels and service data frames designed for code synchronization of descrambler and scrambler are excluded from data stream.

EFFECT: enhanced data transfer speed.

3 cl, 16 dwg

Description

The invention relates to general purpose electronic circuits, in particular to encoding, decoding and data conversion schemes for data transmission between subscribers remote from each other.

A device [1] for data transmission, comprising a data transmission unit and a data receiving unit connected to opposite sides of the communication line, the data transmission unit contains the first and second exclusive-OR elements, the first amplifier and the first shift register, the inputs of the second exclusive-OR element are connected to the outputs the first shift register, and the output to the first input of the first exclusive OR element, the input of the serial data of the first shift register is connected to the output of the first exclusive OR element and to the input of the first of the amplifier, the synchronization input of the first shift register is the device synchronization input, the second input of the first element is Exclusive OR is the device data input, the output of the first amplifier is connected to the communication line, the data reception unit contains a phase-locked loop generator, the second shift register, the third and fourth elements The exclusive OR and the second amplifier, the input of which is connected to the communication line, and the output to the input of the generator with phase-locked loop, the output of which is connected to the synchronization input The second shift register is the synchronization output of the device, the outputs of the second shift register are connected to the inputs of the third exclusive-OR element, the output of which is connected to the first input of the fourth exclusive-OR element, the output of which is the device data output, and the second input is connected to the serial data input of the second shift register and with the output of the second amplifier.

In the device [1], the data transmission and reception units perform the functions of a scrambler and a descrambler, respectively. The input data is converted by a scrambler to a form in which they can be considered as pseudo-random. The descrambler performs the inverse transform, i.e. restores the original data. Scrambling data allows you to replace long sequences of zeros or ones (and not only these sequences) with pseudo-random bits, which eliminates the possibility of loss of synchronization between blocks of data reception and transmission. In addition, the energy spectrum of the transmitted signal is leveled, which helps to reduce the level of crosstalk induced on adjacent twisted pairs of wires of the communication cable.

The disadvantage of the device [1] is the propagation of errors that can occur when transmitting a signal over a communication line. So, a single error is converted into a triple, since the error bit is first directly transmitted to the output of the device data, and then, moving along the second shift register, it distortes the output data two more times.

A device [2] for transmitting data is known, comprising a data transmission unit and a data receiving unit connected to opposite sides of the communication line, a data transmission unit comprising a scrambler comprising a pseudo-random sequence of bits, a first exclusive OR element and a first amplifier, a pseudo-random sequence of bits contains a first the shift register and the second exclusive OR element, the inputs of which are connected to the outputs of the first shift register, and the output to the first input of the first element OR to the serial data input of the first shift register, the synchronization input of which is the scrambler synchronization input, the second input of the first element Exclusive OR is the scrambler data input, the output of the first amplifier is connected to the communication line, the data reception unit contains a descrambler containing a phase-locked oscillator , the second shift register, the third and fourth elements Exclusive OR and the second amplifier, the input of which is connected to the communication line, and the output to the input of the generator with phase by adjusting the frequency, the output of which is the descrambler synchronization output, the outputs of the second shift register are connected to the inputs of the third exclusive-OR element, the output of which is connected to the first input of the fourth exclusive-OR element.

In the device [2], the shift register of the data receiving unit (descrambler) is logically isolated from the communication line, so there is no multiplication of errors coming from the line.

The device [2] has two disadvantages.

The first drawback is that in order to maintain synchronous operation of the shift registers of the scrambler and descrambler (in the event of a device synchronization violation or when it is initially turned on), it is necessary to periodically interrupt the transmission of useful data and transmit service information frames containing sufficiently long chains of synchronizing bits over the communication line. This reduces the effective data transfer rate on the line, complicates the exchange protocol and requires a considerable time for the descrambler to wait for the service frame in case of loss of synchronization. During this time, data transfer is not possible.

The second drawback is the lack of staffing hardware — insertion of control codes into the transmitted data stream and destaffing — separation of these codes from the data stream on the receiving side. Control codes can be addressed to a neighboring node of a digital data network to control the average speed of the oncoming data stream. Typical examples of such codes are: XON - "resume stream" and XOFF - "suspend stream".

Byte-stuffing is often used to introduce control codes into the data stream (see "Transparent XON / XOFF Local Flow Control in Hayes V series Modems" http://vk.pp.ru/docs/hayes/00000536.htm ). Byte-stuffing involves viewing the original array of arbitrary data in order to find codes (bytes) in it that randomly coincide with many control codes (This set also includes a certain DLE code.). The found codes are intentionally (reversibly) distorted so that they differ from the control codes. Distorted codes are preceded by marker codes (DLE) for their subsequent recognition by the receiving equipment. In the data array prepared in this way, which does not contain control command codes (except for the DLE codes artificially entered into the array), the "true" control codes are embedded, then the array is transmitted as a serial bit stream over the communication line to the remote side. The remote data receiver retrieves and accepts the "true" control codes for execution, retrieves the distorted bytes marked with marker codes, restores them, and discards the marker codes.

Token codes introduce unwanted redundancy into the stream of transmitted data. In the worst case, each “useful” byte should be preceded by a service byte, in which a marker code is transmitted, while the effective data transfer rate is halved compared to the maximum possible. In addition, to select control, marker, and data codes, the device - receiver of a serial bit stream must recognize the boundaries between bytes. To specify these boundaries, excessive bits are introduced into the data bitstream, which further reduces the effective transmission rate.

For example, according to US Pat. US application US 2002 0191721 A1, to each byte in the bitstream is added the demarcation bit received from the generator of the pseudo-random sequence of bits. The data receiver device detects the demarcation bits due to their consistent match with the reference pseudo-random bit sequence. Another way of delimiting bytes in a bitstream (US Pat. No. 6,011808) also involves adding a delimitation bit to each byte. This bit is formed by duplication and inversion of the zero bit of the transmitted byte. As a result, the beginning of the byte is always accompanied by the transmission of one of the combinations of bits - 01 or 10. The device - the data receiver detects the delimitation bits and zero data bits due to their statistically stable coincidence with codes 01 or 10. Both methods of introducing the delimitation bits are uneconomical - for every eight data bits you have to enter one service bit.

Both of the above disadvantages reduce the speed of data transmission through the device [2].

The purpose of the invention is to increase the speed of data transmission through the device.

The goal is achieved in that in a device for transmitting data containing a data transmission unit and a data receiving unit connected to opposite sides of the communication line, the data transmission unit comprises a scrambler comprising a pseudo-random sequence of bits, a first exclusive OR element and a first amplifier, a pseudo-random sequence of bits contains the first shift register and the second exclusive-OR element, the inputs of which are connected to the outputs of the first shift register, and the output to the first input of the first The exclusive OR element and to the serial data input of the first shift register, the synchronization input of which is the scrambler synchronization input, the second input of the first exclusive OR element is the scrambler data input, the output of the first amplifier is connected to the communication line, the data reception unit contains a descrambler containing a phase-locked oscillator frequencies, the second shift register, the third and fourth elements exclusive OR and the second amplifier, the input of which is connected to the communication line, and the output to the generator input In the case of phase-locked loop, the output of which is the descrambler synchronization output, the outputs of the second shift register are connected to the inputs of the third exclusive-OR element, the output of which is connected to the first input of the fourth exclusive-OR element. The data transmission unit further comprises a staffing unit, the first data input and the first synchronization output of which are the data input and the first synchronization output of the first channel, the second data input and the second synchronization output of the stuffing unit are the data input and the first synchronization output of the second channel, the scrambler further comprises a third shift register, first decoder, first trigger and first inverter, the output of which is connected to the synchronization input of the first trigger, the input of the first inverter is connected to the input and synchronization of the first and third shift registers, as well as with the third synchronization output of the stuffing unit, the control input of the first shift register is connected to the output of the first decoder and with the control input of the stuffing unit, the data output of which is connected to the scrambler data input, the serial data input of the third shift register is connected with the output of the first XOR element and with the data input of the first trigger, the output of which is connected to the input of the first amplifier, the inputs of the parallel data of the first shift about the register connected to the outputs of the first decoder, the inputs of which are connected to the outputs of the third shift register. The data receiving unit further comprises a destaffing unit, the first synchronization output of which is the second synchronization output of the first channel, the second synchronization output of the destaffing unit is the second synchronization output of the second channel, the descrambler further comprises a fourth shift register, a second decoder, second and third triggers and a second inverter, an output which is connected to the synchronization input of the second trigger and to the synchronization inputs of the second and fourth shift registers, the control input of the second shift the gaming register is connected to the output of the second decoder and to the control input of the destaffing unit, the synchronization input of which is connected to the synchronization output of the descrambler, the output of the third trigger is the data output of the descrambler and connected to the data outputs of the first and second channels of the device, the serial data input of the fourth shift register is connected to the second the input of the fourth XOR element and the output of the second trigger, the data input of which is connected to the output of the second amplifier, the inputs are parallel x of the second shift register are connected to the outputs of the second decoder, the inputs of which are connected to the outputs of the fourth shift register, the input of the serial data of the second shift register is connected to the first input of the fourth exclusive-OR element, the output of which is connected to the data input of the third trigger, the synchronization input of which is connected to the synchronization output descrambler and with the input of the second inverter.

The stuffing unit contains a pulse generator, an inverter, a delay element, a counter, the first and second AND elements, the first and fifth triggers and a multiplexer whose data inputs are the first and second data inputs of the block, and the control input is connected to the output of the fifth trigger, the first block synchronization output connected to the output of the second element And, the second synchronization output of the block is connected to the output of the first element And and with the counter counting input, the zero setting inputs of the counter and the second trigger are connected to the output of the fourth trigger and to the input the house of the delay element, the output of which is connected to the zero setting input of the fourth trigger, the data input of which is connected to the counter output, the synchronization inputs of the first and fourth triggers are connected to the inverter output, the input of which is connected to the output of the pulse generator, to the synchronization inputs of the third and fifth triggers and with the first inputs of the first and second elements And and is the third synchronization output of the block, the output of the multiplexer is connected to the data input of the third trigger, the output of which is the data output of the block, the data input of the first trigger is the control input of the block, the output of the first trigger is connected to the synchronization input of the second trigger, the data input of which is connected to the positive voltage bus, the single output of the second trigger is connected to the second input of the first element And and to the data input of the fifth trigger, the zero output of the second trigger connected to the second input of the second element I.

The destaffing unit contains an inverter, a delay element, a counter, the first and second elements And, the first, second and third triggers, the inverter input is connected to the first inputs of the first and second elements And is the synchronization input of the block, the data input of the first trigger is the control input of the block, the inputs synchronization of the first and third triggers are connected to the output of the inverter, the inputs of the zero setting of the counter and the second trigger are connected to the output of the third trigger and to the input of the delay element, the output of which is connected to the input of the installation well For the third trigger, the data input of which is connected to the output of the counter, the counting input of which is connected to the output of the first AND element and is the second output of the block synchronization, the output of the second And element is the first synchronization output of the block, the single and zero outputs of the second trigger are connected to the second inputs of the first and of the second element And, the data input of the second trigger is connected to the positive voltage bus, the synchronization input of the second trigger is connected to the zero output of the first trigger.

Figure 1, a and b presents a functional diagram of a known generator of a pseudo-random sequence of bits and a table is a pointer to the points of connection of the feedback circuit of this generator; figure 2 is a functional diagram of a known device [1] for data transmission; figure 3 is a functional diagram of a known device [2] for data transmission; figure 4 is a functional diagram of the proposed device for data transmission; figure 5 is a functional diagram of the staffing unit of the proposed device; figure 6 is a functional diagram of a block destaffing the proposed device; in Fig.7, a - c is a state table of a generator of a pseudo-random sequence of bits, a state diagram of this generator and an example of a code situation that explains the operation of the proposed device; on Fig - timing diagrams of the operation of the scrambler of the proposed device; figure 9 is a timing diagram of the descrambler of the proposed device; figure 10 - 13 are timing diagrams explaining the data transfer process of the proposed device in different code situations.

The pseudo-random sequence of bits generator 1 (Fig. , the input 5 of the synchronization of the shift register 2 is the synchronization input of the generator 1 of the pseudo-random sequence of bits. The direction of the data shift in register 2 is shown by arrow 6. The bit numbers M and N of register 2 are selected from shown in Fig. 1, b of table 7 — pointer of the connection points of the feedback circuit.

The known [1] device 8 for transmitting data (FIG. 2) contains data transmission unit 10 (scrambler) and data reception unit 11 (descrambler) connected to opposite sides of the communication line 9, data transmission unit 10 contains the first 12 and second 13 exclusive elements OR, the first 14 amplifier and the first 15 shift register, inputs of the second 13 Exclusive element OR connected to the outputs of the first 15 shift register, and the output to the first input of the first 12 element Exclusive OR, the serial data input of the first 15 shift register is connected to the output the first 12 exclusive-OR elements and with the input of the first 14 amplifier, the synchronization input of the first 15 shift register is the device synchronization input 16, the second input of the first 12 exclusive-OR elements is the device data input 17, the output of the first amplifier 14 is connected to the communication line 9, reception block 11 the data contains a phase-locked oscillator 18, a second 19 shift register, a third 20 and a fourth 21 exclusive-OR elements and a second 22 amplifier, the input of which is connected to communication line 9, and the output to the input of generator 18 with automatic frequency locking, the output of which is connected to the synchronization input of the second 19 shift register and is the device synchronization output 23, the outputs of the second 19 shift register are connected to the inputs of the third 20 Exclusive OR elements, the output of which is connected to the first input of the fourth 21 elements of the Exclusive OR, whose output is the output 24 of the device data, and the second input is connected to the serial data input of the second 19 shift register and the output of the second amplifier 22. The data shift directions in the registers 15 and 19 are shown by arrows 25. An external data source 26 (for example, the first computer) is connected to the inputs 16 and 17 of the device 8. An external data receiver 27 (for example, a second computer) is connected to the outputs 23 and 24 of the device 8.

The known [2] device 28 for transmitting data (Fig. 3) comprises data transmitting unit 30 (scrambler) and data receiving unit 31 (descrambler) connected to opposite sides of the communication line 29, data transmitting unit 30 includes a pseudo-random bit sequence generator 32, the first The 33 XOR element and the first 34 amplifier, the pseudo-random sequence of bits generator 32 contains the first 35 shift register and the second 36 XOR element, the inputs of which are connected to the outputs of the first 35 shift register, and the output to the first input to the first 33 exclusive-OR elements and to the serial data input of the first 35 shift register, the synchronization input of which is the scrambler 30 synchronization input 37, the second input of the first exclusive-OR element is the scrambler 30 data input 38, the output of the first amplifier 34 is connected to the communication line 29, block 31 data reception (descrambler) contains a phase-locked oscillator 39, a second 40 shift register, a third 41 and a fourth 42 exclusive-OR elements and a second amplifier 43, the input of which is connected to the communication line 29, output - to the input of oscillator 39 with the phase locked loop, whose output is the output 44 of descrambler synchronization 31, the outputs of the second shift register 40 are connected to the inputs of a third exclusive-OR element 41, whose output is connected to first input 42 of the fourth exclusive-OR element.

In block 30, the output of the first 33 XOR element is connected to the input of the first 34 amplifier. The data receiving unit 31 also contains a multiplexer 45, the output of which is connected to the serial data input of the register 40, and the control input is the control input 46 of the device 28. The first data input of the multiplexer 45 is connected to the first input of the fourth 42 XOR elements. The second data input of the multiplexer 45 is connected to the second input of the fourth exclusive-OR element 42 and to the output of the second amplifier 43. The output of the fourth element 42 Exclusive OR is the data output 47 of the device 28. The synchronization input of the register 40 is connected to the synchronization output 44 of the device 28. The data shift directions in the registers 35 and 40 are shown by arrows 48. An external data source 49 (for example, the first computer) is connected to the inputs 37 and 38 of the device 28. An external data receiver 50 (for example, a second computer) is connected to the outputs 44 and 47 and to the input 46 of the device 28.

The proposed device for transmitting data (Fig. 4) comprises data transmitting unit 52 and data receiving unit 53 connected to opposite sides of the communication line 51, data transmitting unit 52 contains a scrambler 54, containing a pseudo-random sequence of bits generator 55, the first 56 exclusive OR element, and the first 57 amplifier, generator 55 of the pseudo-random sequence of bits contains the first 58 shift register and the second 59 XOR element, the inputs of which are connected to the outputs of the first 58 shift register, and the output to the first input the first 56 exclusive OR element and to the serial data input of the first 58 shift register, the synchronization input of which is the scrambler synchronization input 60, the second input of the first exclusive OR element is the scrambler data input 61, the output of the first amplifier 57 is connected to the communication line 51, reception unit 53 the data contains a descrambler 62 containing a phase-locked loop generator 63, a second 64 shift register, a third 65 and a fourth 66 exclusive-OR elements and a second amplifier 67, the input of which is connected to the line with monitor 51, and the output is to the input of a phase-locked loop generator 63, the output of which is synchronization output of descrambler 62, the outputs of the second 64 shift register are connected to the inputs of the third 65 exclusive-OR element, the output of which is connected to the first input of the fourth 66 exclusive-OR element.

The data transmission unit 52 also contains a staffing unit 69, the first data input 70 and the first synchronization output 71 of which are the data input and the first synchronization output of the first channel, the second data input 72 and the second synchronization output 73 of the block 69 are the data input and the first synchronization output of the second channel The scrambler 54 further comprises a third 74 shift register, a first 75 decoder, a first 76 trigger and a first 77 inverter, the output of which is connected to the synchronization input of the first 76 trigger, the input of the first 77 inverter is connected to the input the synchronization odes of the first 58 and third 74 shift registers, as well as with the third synchronization output of block 69, the control input of the first 58 shift register is connected to the output of the first 75 decoder and to the control input 78 of block 69, the data output of which is connected to the input 61 of the scrambler data, input of serial data of the third 74 shift register is connected to the output of the first 56 XOR elements and to the data input of the first 76 trigger, the output of which is connected to the input of the first 57 amplifier, inputs 79 of the parallel data of the first 58 traction register connected to the outputs of the first decoder 75 whose inputs are connected to outputs of the third shift register 74.

The data receiving unit 53 also contains a destaffing unit 80, the first 81 synchronization output of which is the second synchronization output of the first channel, the second 82 synchronization output of the block 80 is the second synchronization output of the second channel, the descrambler 62 further comprises a fourth 83 shift register, second 84 decoder, second 85 and the third 86 triggers and the second 87 inverter, the output of which is connected to the synchronization input of the second 85 triggers and to the synchronization inputs of the second 64 and fourth 83 shift registers, the control input of the second 64 the shift register is connected to the output of the second decoder 84 and to the control input 88 of the destaffing unit 80, the synchronization input of which is connected to the descrambler synchronization output 68, the output of the third 86 trigger is the descrambler data output 89 and connected to the data outputs 90 and 91 of the first and second channels of the device, the serial data input of the fourth 83 shift register is connected to the second input of the fourth 66 exclusive-OR element and to the output of the second 85 trigger, the data input of which is connected to the output of the second 67 amplifier, the parallel data strokes 92 of the second 64 shift register are connected to the outputs of the second 84 decoder, the inputs of which are connected to the outputs of the fourth 83 shift register, the serial data input of the second 64 shift register is connected to the first input of the fourth 66 exclusive-OR element, the output of which is connected to the data input of the third 86 a trigger, the synchronization input of which is connected to the synchronization output 68 of the descrambler 62 and to the input of the second inverter 87. Arrows 93 show the data shift directions in registers 58, 64, 74, and 83.

The stuffing unit 69 (FIG. 5) comprises a pulse generator 94, an inverter 95, a delay element 96, a counter 97, a first 98 and a second 99 AND elements, a first 100, a second 101, a third 102, a fourth 103, a fifth 104 triggers and a multiplexer 105, the data inputs of which are the first 70 and second 72 data inputs of block 69, and the control input is connected to the output of the fifth 104 trigger, the first 71 synchronization output of the block 69 is connected to the output of the second 99 element And the second 73 synchronization output of the block 69 is connected to the output of the first 98 element And with the counter input of counter 97, the zero-setting inputs with the counter 97 and the second 101 flip-flops are connected to the output of the fourth 103 flip-flops and to the input of the delay element 96, the output of which is connected to the zero-setting input of the fourth 103 flip-flops, the data input of which is connected to the output of the counter 97, the synchronization inputs of the first 100 and fourth 103 flip-flops are connected to the output inverter 95, the input of which is connected to the output of the pulse generator 94, with the synchronization inputs of the third 102 and fifth 104 triggers and with the first inputs of the first 98 and second 99 elements And is the third 60 synchronization output of block 69, output m the lithotlexer 105 is connected to the data input of the third trigger 102, the output of which is the data output 61 of the block 69, the data input of the first 100 trigger is the control input 78 of the block 69, the output of the first 100 trigger is connected to the synchronization input of the second 101 trigger, the data input of which is connected to the bus 106 positive voltage, the single output of the second 101 flip-flops is connected to the second input of the first 98 of the And element and to the data input of the fifth 104 flip-flops, the zero output of the second 101 flip-flops is connected to the second input of the second 99 of the And element.

The destaffing unit 80 (Fig. 6) contains an inverter 107, a delay element 108, a counter 109, a first 110 and a second 111 elements And, the first 112, the second 113 and the third 114 triggers, the input of the inverter 107 is connected to the first inputs of the first 110 and second 111 elements And it is the synchronization input 68 of block 80, the data input of the first 112 trigger is the control input 88 of block 80, the synchronization inputs of the first 112 and third 114 triggers are connected to the output of inverter 107, the zero-setting inputs of the counter 109 and second 113 of the trigger are connected to the output of the third 114 trigger and with the input of element 108 delays, the output of which is connected to the zero-setting input of the third trigger 114, the data input of which is connected to the output of the counter 109, the counting input of which is connected to the output of the first 110 And element and is the second 82 synchronization output of the block 80, the output of the second 111 And element is the first 81 output synchronization unit 80, the single and zero outputs of the second trigger 113 are connected to the second inputs of the first 110 and second 111 elements And, the data input of the second trigger 113 is connected to the positive voltage bus 115, the synchronization input of the second 113 trig EPA is connected to the zero output of the first flip-flop 112.

Table 116 (FIG. 7, i) presents a list of states of the pseudo-random bit sequence generator 55; the state diagram 117 of this generator (Fig. 7, b) reflects the movement of the current state indicator 118 along the ring path; lines 119 and 120 divide the diagram into four sectors. Table 121 (Fig. 7, c) shows an example of a code situation explaining the operation of the proposed device.

Timing diagrams 122 and 123 (Fig. 8) correspond to the signals at the inputs 60 and 61 of the scrambler 54; chart 124 - the signal at the output of the element Exclusive OR 59; chart 125 - the signal at the output of the element Exclusive OR 56; chart 126 - the signals at the outputs of the register 74; chart 127 - the signal at the control input P / S register 58 (point 78); chart 128 - to the states of the generator 55 of the pseudo-random sequence of bits; chart 129 - the signal at the input of the amplifier 57.

Timing diagram 130 (Fig.9) correspond to the signal at the output of amplifier 67; chart 131 - the signal at the output of the inverter 87; chart 132 - the signal at the output of the trigger 85; chart 133 - the signals at the outputs of the register 83; chart 134 - the signal at the control input P / S * register 64 (point 88); chart 135 - the state of the register 64 of the generator of the pseudo-random bit sequence of the descrambler 62; chart 136 - the signal at the output of the element Exclusive OR 65; chart 137 - the signal at the output of the element Exclusive OR 66; chart 138 - to the signal at the input of inverter 87; chart 139 - the signal at the output of 89 descrambler 62.

Timing diagrams 140 and 141 (figure 10) correspond to the signals at the input and output of the inverter 95 (figure 5); diagrams 142 and 143 - signals at the input of data and the output of the trigger 100; diagrams 144 and 145 - signals at the single and zero outputs of the trigger 101; chart 146 shows a signal at the output of trigger 104; diagrams 147 and 148 - to signals at points 71 and 73; diagrams 149, 150, 151 and 152 - to the signals L1, L2, L3 at the outputs of the counter 97 and at its zero input; diagrams 153 and 154 - signals at points 70 and 72; diagrams 155 and 156 - to the signals at the data input and the output of the trigger 102; diagram 157 shows the signal at the input of amplifier 57 (Fig. 4).

Timing diagrams 158 and 159 (Fig.11) correspond to the signals at the input and output of the inverter 95 (Fig.5); diagrams 160 and 161 - to signals at the data input and the output of the trigger 100; diagrams 162 and 163 - signals at the single and zero outputs of the trigger 101; chart 164 - the signal at the output of the trigger 104; diagrams 165 and 166 - signals at points 71 and 73; diagrams 167, 168, 169 and 170 to the signals L1, L2, L3 at the outputs of the counter 97 and at its input zero; diagrams 171 and 172 - signals at points 70 and 72; diagrams 173 and 174 - to the signals at the data input and the output of the trigger 102; diagram 175 is a signal at the input of amplifier 57 (Fig. 4).

Timing diagrams 176, 177 and 178 (Fig. 12) correspond to signals at the data input, synchronization input, and trigger output 85; chart 179 - signal in the input bit of the register 83; diagrams 180 and 181 - signals at the input of data and the output of the trigger 112 (Fig.6); diagrams 182 and 183 - signals at the single and zero outputs of the trigger 113; diagrams 184 and 185 - to signals in the register 64 and at the output of the element Exclusive OR 65; diagrams 186, 187 and 188 - signals at the data input, synchronization input and trigger output 86; diagrams 189 and 190 - to signals at points 81 and 82; diagrams 191, 192, 193 and 194 - to the signals L1 *, L2 *, L3 * at the outputs of the counter 109 and at its input zero.

Timing diagrams 195, 196 and 197 (FIG. 13) correspond to signals at the data input, synchronization input, and trigger output 85; chart 198 - the signal in the input bit of the register 83; diagrams 199 and 200 to the signals at the data input and output of the trigger 112 (Fig.6); diagrams 201 and 202 - signals at the single and zero outputs of the trigger 113; diagrams 203 and 204 - to signals in the register 64 and at the output of the element Exclusive OR 65; diagrams 205, 206 and 207 - signals at the data input, synchronization input and trigger output 86; diagrams 208 and 209 - to signals at points 81 and 82; diagrams 210, 211, 212 and 213 to the signals L1 *, L2 *, L3 * at the outputs of the counter 109 and at its input zero.

The following is a brief description of the operation of known devices [1, 2].

Scramblers and descramblers typically contain pseudo-random bit sequence generators or fragments of such generators. An example of constructing a generator of a pseudo-random sequence of bits is shown in figure 1 (see the book. P. Horowitz, W. Hill "The Art of Circuit Engineering": In three volumes - M .: Mir, 1993. - 2 tons). Generator 1 is made on the basis of shift register 2 with an exclusive OR (XOR) 3 logic element in the feedback circuit.

In the initial state, any non-zero code is present in register 2 (the initial setup circuit of the register is not shown). Under the influence of the positive edges of the clock signal CLK at input 5, this code circulates in the generator and simultaneously modifies. In each clock cycle (CLK signal period), the code advances in register 2 in the direction indicated by arrow 6, while the data bit from output 4 is entered into the freed register bit. As an output from the generator, you can use the output of the exclusive OR 3 element or the output of any bit of the register.

In the general case, when using the M-bit register 2, the feedback circuit is connected to the digits with the numbers M and N (M> N). In order for a pseudo-random sequence of bits with a repetition period equal to 2 ^M - 1 to be formed at the output of the generator, you should select the connection points of the feedback circuit in accordance with table 7 (Fig. 1, b), which describes a number of generators of different bit depths. When the generator is operating in register 2, all possible M-bit codes are generated, except for zero. (Note that in all the devices described below it is possible to use advanced generators that do not have forbidden states, see, for example, Prince B. Shevkoplyas "Microprocessor Structures. Engineering Solutions": Handbook. - Supplement One. - M: Radio and communication, 1993. - 256 p.).

A pseudo-random sequence of bits with a repetition period equal to 2 ^M - 1 has the following properties.

1. In a full cycle (2 ^M - 1 cycles), the number of log. 1 generated at the output 4 of generator 1 is one more than the number of log. 0. Additional log. 1 appears due to the exclusion of a state in which a zero code would be present in register 2. This can be interpreted so that the probabilities of occurrence of log.0 and log.1 at the output 4 of generator 1 are almost the same.

2. In a full cycle (2 ^M - 1 cycles), half of the series from consecutive log.1 has a length of 1, one fourth of series have a length of 2, one eighth of a length of 3, etc. Series from log.0 have the same properties. taking into account the missed log. 0. This suggests that the probabilities of the appearance of "eagles" and "tails" do not depend on the outcome of previous "tosses." Therefore, the probability that a series of consecutive log. 1 or log. 0 ends at the next toss is 1/2.

3. If the sequence of the full cycle (2 ^M - 1 cycles) is compared with the same sequence, but cyclically shifted by any number of cycles W (W is not zero or a multiple of 2 ^M - 1), then the number of mismatches will be one more, than the number of matches.

The most common are two main schemes of devices for data transmission (devices of the "scrambler - descrambler" type): with non-isolated and isolated (from the communication line) generators of pseudo-random bit sequences.

In the device 8 (FIG. 2 [1]), the scrambler 10 and the descrambler 11 are made using fragments of the pseudorandom sequences of bits considered earlier 1 (see FIG. 1). An additional element Exclusive OR 12 is introduced into the feedback circuit of the generator based on the shift register 15. A similar generator based on the shift register 19 with an open feedback circuit is used in the descrambler.

All processes taking place in the device 8 are synchronized from a clock located in an external data source 26 (it can also be placed in block 10). The clock generates a signal CLK - a continuous sequence of clock pulses with a duty cycle equal to two. In each clock cycle, the next bit of the transmitted DATA data is fed to input 17 of the scrambler 10, and in the shift register 15, the accumulated code moves one bit to the right (arrow 25).

If we assume that data source 26 sends a long sequence of log.0 (DATA = 0) to scrambler 10, then the XOR 12 element can be considered as a repeater of the Y1 signal from the output of the XOR OR 13 element. In this situation, register 15 is actually closed in a ring and generates exactly the same pseudo-random sequence of bits as in the generator circuit 1 considered earlier (Fig. 1). If an arbitrary bit sequence is received from data source 26, then it interacts with the bit sequence from the output of the Exclusive OR 13. As a result, a new (scrambled) sequence of SCRD data bits is generated, which is close in structure to random. This sequence, in turn, advances in register 15, forms the bit stream Y1 at the output of the element Exclusive OR 13, etc.

A scrambled SCRD bit sequence passes through an amplifier 14, is transmitted over a communication line 9 (for example, over a twisted pair of wires of a multi-core cable of an urban telephone network) and enters a descrambler 11, where it passes through an amplifier 22. Using a generator 18 with phase-locked loop frequency from the input signal SCRD * (from the output of amplifier 22), a clock signal CLK * is allocated, which is transmitted to the clock input C of register 19 and to the output 23 of device 8.

The oscillator 18 with phase-locked loop can be performed according to one of the known schemes (see, for example, US Pat. No. 6,215,835 B1). It is designed to generate a highly stable CLK * clock based on continuous tracking of the SCRD * input signal. In this case, the negative edge of the signal CLK * is tied to the moments of change of the signal SCRD * (0 → 1 or 1 → 0), so that the positive edge of the signal CLK * is formed in the middle of the bit interval of the signal SCRD *, which corresponds to its steady-state value. The data shift in register 19 and the reception of the next SCRD * bit in the freed bit occur at the positive edge of the CLK * signal. The descrambled DATA * data arrives at the data receiver 27 and is captured therein along the positive edges of the CLK * signal.

Due to the sufficient inertia of the generator 18, the CLK * signal is practically insensitive to the "jitter" of the SCRD * signal and its other short-term distortions caused by interference in the communication line 9 (Such use of a standard generator with phase-locked loop in telecommunication systems is generally accepted and will not be described in detail below).

DATA and DATA * data streams match up to a delay in transmission. Indeed, in the steady state, the same codes are present in the shift registers 15 and 19, since the same data SCRD = SCRD * (taking into account the transmission delay) is supplied to the inputs D of these registers, and the clock frequency is the same. Therefore, Y2 = Y1, and, taking this into account,

Y2=SCRD

Y2=(DATA

Y1)

Y2=DATA

Y1

Y1=DATA

0=DATA.DATA * = SCRD *

Y2 = SCRD

Y2 = (DATA

Y1)

Y2 = DATA

Y1

Y1 = DATA

0 = DATA.

The considered method of scrambling - descrambling data does not require the use of any special initial synchronization procedure (as in the device [2]). After filling in the shift register 19, as was shown, the pseudorandom bit sequence generators based on registers 15 and 19 work synchronously (their states are always the same) and generate the same signals Y1 and Y2. When a single error occurs in the communication line 9, the code synchronization (the identity of the contents of registers 15 and 19) is temporarily violated, but then automatically restored as soon as the correct data is again filled in the register 19. However, in the process of moving the erroneous bit through the shift register 19, namely, the periods of its falling first on one and then on the other input of the Exclusive OR 20 element, the Y2 signal twice takes the wrong value. This leads to the propagation of a single error - it first appears in the DATA * signal at the moment it arrives from the line and then occurs two more times with a subsequent twofold distortion of the Y signal.

In the device 28 (Fig. 3 [2]), pseudo-random bit sequence generators isolated from the communication line 29 are used. Their initial code synchronization is performed using descrambler hardware and software source 49 and data receiver 50.

The hardware includes a multiplexer 45 (MLJX) and a program-controlled output 46 of the data receiver 50, on which the control signal F. is generated. During normal operation of the scrambler-descrambler system, the data receiver 50 constantly supports the output signal F = 0. The signal Z2 from the output of the Exclusive OR 41 element is transmitted to the output of the multiplexer 45, the pseudo-random bit sequence generator based on register 40 is isolated from external influences.

Assume that in the initial state the descrambler is not synchronized with the scrambler. Such a situation may arise, for example, after turning on the supply voltage of the receiving side equipment, after an error in the operation of the descrambler generator 39 due to the influence of interference on the communication line or for other reasons. In the absence of code synchronization between the scrambler and the descrambler, the contents of registers 35 and 40 do not match, the received DATA * data stream is erroneous and does not match the DATA transmitted data stream.

Upon detection of a stable chaotic data stream DATA * (in which there is no separation of information frames caused by the protocol of exchange, etc.), the receiver generates a signal F = 1. As a result, the multiplexer 45 begins to transmit to the input D of the register 40 a signal of scrambled data SCRD *, as in the previously discussed device [1] (see figure 2).

The exchange protocol provides for the transfer of data in the form of a sequence of frames. Groups of regular frames are interspersed with overhead frames. For example, after a group of 1000 ordinary frames, one official follows. In particular, it contains a synchronization sequence of a certain number (for example, 256) of zero bits. When these bits are sent (DATA = 0) to the scrambler, the Exclusive OR 33 element acts as a repeater of the Z1 signal from the output of the Exclusive OR 36 element. Therefore, in this case, the scrambled SCRD signal is a fragment of a “true” pseudo-random bit sequence, in the sense that it not mixed with a stream of arbitrary DATA data and generated only by the 32 scrambler generator.

This sequence is automatically loaded into register 40 and passes through it, since F = 1. After the contents of the registers 35 and 40 are the same, the signal Z2 begins to repeat the signal Z1. Code synchronization is achieved. A continuous sequence of log.0 is supplied to the input of the data receiver 50, since DATA * = DATA = 0. After confidently detecting a sufficiently long (for example, containing 180 bits) sequence of log.0, the receiver 50 generates a signal F = 0 and thereby returns the generator of the pseudo-random sequence of bits of the descrambler to the isolated operation mode. Now, code synchronization is not only achieved, but also “saved” due to the logical isolation of register 40 from communication line 29. After the transmission of the service (synchronizing) frame is completed, the data source 49 proceeds with the transmission of a group of 1000 ordinary frames according to the exchange protocol adopted in the system.

Thus, in the device [2], in order to maintain synchronous operation of the shift registers of the scrambler and descrambler (in case of a violation of the device’s synchronization or when the receiver part is turned on for the first time), it is necessary to periodically interrupt the transmission of useful data and transmit service information frames containing sufficiently long chains over the communication line sync bits (DATA = 0.). As a result, the effective data transfer rate on the line decreases, and the exchange protocol is complicated. In addition, with an increase in the intervals between overhead frames (which is desirable for a more efficient transmission of useful data), the wait time for the descrambler in the event of loss of code synchronization increases. During this time, the transfer of useful data is not possible.

Unlike the device [2], the proposed device (Fig. 4) implements two improvements to increase the data transfer rate.

The first improvement consists in the fact that the restoration of code synchronization between the scrambler and descrambler in case of loss occurs without transferring any service synchronizing code sequences over the communication line. Therefore, the flow of useful data is not interrupted, the synchronization recovery time is reduced.

The second improvement is that information about the placement of instruction codes embedded in the data stream is not explicitly transmitted over the line; The carriers of this information are random events that are recorded simultaneously by data transmission and reception units.

In general terms, the idea of the first improvement is as follows. The scrambler and descrambler contain pseudo-random bit sequence generators isolated from the communication line with the same feedback structure. The scrambled bit stream is constantly analyzed by the scrambler and descrambler in order to find certain codes in it. The detection of each such code by the scrambler and descrambler leads to the simultaneous installation of both generators of the pseudo-random sequence of bits in a certain state corresponding to this code. Thus, the generators at random moments are simultaneously set to the same state as the transfer of useful data. These events occur relatively rarely, i.e. most of the time, the generators operate in the mode of "natural" sequential transition from the previous state to the next, as was shown in the description of the generator 1 (figure 1). If the code synchronization has not been broken, then the moments of installation of the generators only confirms it. If the code synchronization was previously lost, then it is restored upon the first detection of one of the given codes in the stream of scrambled data. Thus, synchronization overhead bits are not transmitted over the communication line.

The second improvement is also based on the fact that data transmission and reception units simultaneously (up to transmission delay) detect predetermined codes in a scrambled data stream. The moments of detection of such codes are random events. They are used to synchronize the work of stuffing and destaffing blocks. If these blocks previously worked inconsistently, then after the simultaneous detection of one of the mentioned random events, the correct synchronization is restored - in the future, the destaffing block generates signals that allow to extract command codes from the bit stream at the right time intervals and send them to the second channel.

The following describes the operation of the components of the proposed device.

The shift registers 74 and 83 (FIG. 4) are intended for temporary storage of fragments of SDATA and SDATA * streams of scrambled data. In the steady state, these fragments are the same (coincide up to a transmission delay). Reception of the next bit in the register 74 (83) occurs on the positive edge of the signal at the clock input C of this register. Simultaneously with the reception of the next bit from input D, previously stored data is shifted to one bit to the right (arrow 93). In this example of the construction of the device, the bit width of the register 74 (83) is chosen equal to eight, although it can be greater or less. The dynamics of the operation of the register 74 can be traced to the table 121 of its states (Fig.7, c).

The scrambler 54 pseudorandom bit sequence generator 55 contains a shift register 58 and an exclusive OR element 59. A similar descrambler pseudo random bit sequence generator 55 contains a shift register 64 and an exclusive OR element 65.

Shift registers 58 and 64 are intended for temporary storage of pseudo-random codes SRND and SRND *. In the steady state, these codes are the same (coincide with an accuracy of transmission delay). The next bit in register 58 (64) is received from input D along the positive edge of the signal at synchronizing input C, provided that at its control input P / S (P / S *), which sets the mode of parallel or serial data reception, a log signal . 0. Simultaneously with the reception of the next bit from input D, the previously stored code is shifted by one bit to the right (along arrow 93). If at the control input P / S (P / S *) register 58 (64) there is a log signal. 1, then a parallel code from the group of inputs 79 (92) is received on the positive edge of the signal at the synchronizing input C into the register. In this example of the construction of the device, the width of the register 58 (64) is chosen equal to five, although it can be greater or less. At the same time, the connection points of the inputs of the Exclusive OR element 59 (65) to the register 58 (64) are selected in accordance with the table presented in figure 1, b.

The initial state of the register 58 may be any, including zero. The exit from the zero state occurs when a parallel code is written to the register from inputs 79. The scrambler initialization program provides for the output of some code CODE ₁ to its input 61, which is recognized by the decoder 75. If the code zero was initially present in register 58, the code CODE ₁ passes without change through the XOR element 56 and is sequentially loaded into the register 74. The decoder 75 responds to it by transferring the register 58 to the parallel loading mode (P / S = 1) and generating a non-zero code LOAD ₁ , which is then received in register 58 from inputs 79. Thus, the generator 55 leaves the forbidden state 000 ... 0. If the initial state of register 58 was nonzero, then issuing CODE ₁ code to input 61 is useless, but does not lead to any undesirable consequences. It is also possible to set register 58 to a nonzero state (the corresponding input of register 58 to this state is not shown).

The initial state of the register 64 may also be any, including zero. This state is updated (becomes obviously nonzero) when one of the predefined codes (CODE ₁ and, possibly, others) is detected by the decoder 84 in the scrambled data stream.

An exclusive OR element 56 (59, 65, 66) generates a signal of logic 1 at the output only when the input signals have opposite logical values (log 0 and log 1). The exclusive OR elements 59 and 65 form the output signals RND and RND * of the pseudo-random bit sequence generators of the scrambler 54 and the descrambler 62. The exclusive OR elements 56 and 66 form the scrambled SCRD and descrambled DIN data signals.

D-type flip-flops 76, 85 and 86 receive data bits from input D along the positive edge of the signal at synchronization input C. Triggers 76 and 86 generate DLINE and DATA * output signals, in which the signal can change only once at the boundaries between bit intervals, while the input signals SCRD and DIN of these triggers at the boundaries between bit intervals can change many times due to the non-simultaneous occurrence of transients ("racing" signals) in circuits 58-59-56; 61-56 and 64-65-66; 85-66. Trigger 85 largely eliminates the jitter of the input signal (edge “jitter” at the boundaries between bit intervals) due to the fact that the reception of a bit in this trigger occurs at the center of the bit interval when the transients of the DLTNE * signal have already ended. The residual jitter of the SDIN signal at the output of the trigger 85 is determined by the imperfect signal CLK * at the output of the generator 63. The initial states of the triggers 76, 85, and 86 are arbitrary.

Inverter 77 (87) converts the input signal log.0 to the output signal log.1, and vice versa - the input signal log.1 to the output signal log.0.

Generator 63 with phase-locked loop can be performed according to one of the known schemes (see, for example, US Pat. No. 6,215,835 B1). It is designed to generate a highly stable CLK * clock based on continuous tracking of the DLINE * input signal. The positive edge of the CLK * signal is tied to the moments when the DLINE * signal changes (0 → 1 or 1 → 0), so that the negative edge of the CLK * signal is formed in the middle of the bit interval of the DLINE * signal, which corresponds to its steady-state value.

Due to the sufficient inertia of the generator 63, the CLK * signal is practically insensitive to the jitter of the DLINE * signal and its other short-term distortions caused by noise in the communication line 51 (Such use of a standard phase-locked oscillator in telecommunication systems is generally accepted and will not be detailed further).

The decoder 75 (84) for allocating a stream of scrambled data passing through the shift register 74 (83), certain codes CODE _1, CODE _2, ..., _K SOOE. When the decoder 75 (84) detects the indicated codes at its outputs 79 (92), the corresponding V-bit code LOAD ₁ , LOAD ₂ , ..., LOAD _{K is} generated for subsequent parallel loading of the shift register 58 (64). In this example, the construction of the device K = 4, V = 5. If any code CODE ₁ , CODE ₂ , ..., CODE _{K is} detected, the decoder 75 (84) also generates a single signal at the input P / S (P / S *) for controlling the operating mode of register 58 (64), preparing it for parallel reception data on the positive edge of the next sync pulse at input C.

The amplifier 57 (67) is designed to transmit (receive) a scrambled data signal to the line (from the line) 51. The parameters of the amplifiers 57 and 67 are determined by the type of communication line 51, which in the simplest version can be made in the form of a twisted pair of wires, coaxial or fiber cable. The communication line may contain sequentially connected repeaters, in which blocks of buffer memory can be used. Therefore, the signal transmission delay between the transmission unit 52 and the data receiving unit 53 may be significant and not known in advance (but constant).

The clock generator 94, located in the block 69 stuffing (figure 5), sets the pace of the entire device. At the output 60 of the generator 94, a continuous pulse train is formed with a duty cycle of two. Depending on the state of the trigger 101, the pulses from the output of the generator 94 pass through the element And 99 or the element And 98 and are transmitted either to the first or second channel (at points 71 or 73). In response to each pulse transmitted to the corresponding channel, external sources of data and commands (not shown) form bits that arrive at the inputs 70 and 72 of the device.

Data is transmitted on the first channel, and commands on the second. Upon receipt of the pulse signal J = 1, block 69 stops transmitting data from the first channel for four clock cycles and fills the received pause with four bits received from the second channel, after which it returns to transmitting data from the first channel. Thus, the DATA data stream at the output 61 of block 69 contains inserts (four stuff bits from the second channel), the position of which is tied to pulses J = 1.

The number of bits in the insert is determined by the capacity of the counter 97. The counter adds one to the code stored in it along the positive edge of the TxC2 signal. The counting range is from code 000 ₂ to code 100 ₂ , after which, with a delay of half a clock, a signal RESET is set to set counter 97 and trigger 101 to zero. Element 96 delays the signal from the output of flip-flop 103 by about a quarter of the clock cycle CLK and sets the duration of the RESET pulse. Positive voltage + U at the data input of the trigger 101 corresponds to the signal log. 1. The multiplexer 105 at H = 0 transmits the signal TxD1 from the first channel to the input of the trigger 102, and at H = 1, the signal TxD2 from the second channel.

In the destaffing unit 80 (Fig. 6), the CLK * clock signal is distributed in two directions corresponding to the first and second channels (outputs 81 and 82). The data receivers of the corresponding channels (not shown) receive bits from the total DATA * data stream (see Fig. 4, outputs 90 and 91) using the corresponding clock signals RxC1 and RxC2.

The counter 109 and the delay element 108 are similar to the counter 97 and the delay element 96 of the staffing unit 69 (see FIG. 5). Upon receipt of the pulse signal J * = 1, the block 80 for four clock cycles stops the generation of clock pulses in the first channel and the next four clock pulses gives in the second channel, and then returns to the first channel. Thus, command bits previously inserted into the data stream are perceived only by external equipment of the second channel, which is required. The coordinated operation of the units of 69 stuffing and 80 destaffing is carried out due to the fact that pulses J and J * are formed in these blocks simultaneously (up to a transmission delay).

The following is a description of the operation of a larger fragment of the proposed device. This fragment includes a scrambler 54, a communication line 51 and a descrambler 62.

The DATA input data and the accompanying synchronization signal CLK go to the inputs 61 and 60 of the scrambler 54. The positive edges of the CLK signal (moments T0, T1, ..., T18 in Fig. 8) correspond to the boundaries between the bit intervals of the DATA data signal, as shown in diagrams 122 and 123. On the positive edges of the signal CLK, the contents of the register 74 are changed (diagram 126), the generator 55 goes into new states (diagram 128). At the same time, for each positive edge of the CLK signal, another pseudorandom RND bit is formed (diagram 124), which is added modulo two with the DATA data bit and converted into a scrambled SCRD data bit (diagram 125). At the end of the transient processes, at the moment of formation of the negative edge of the CLK signal, the SCRD bit is received in the trigger 76 (DLINE signal diagram 129) and transmitted through the amplifier 57 to the communication line 51.

In the time interval T8-T9 (Fig. 8), the decoder 75 generates a signal J = 1 at the input P / S of the operation mode control of the register 58 (diagram 127), preparing it for receiving parallel data at the time T9.

In the absence of parallel loading, the generator 55 of the pseudo-random sequence of bits sequentially, cyclically passes through a series of states S1, S2, S3, ..., S31, S1, S2, etc., as shown in Fig. 7, a, b (table 116 Diagram 117). In state S1 (see the first row of table 116, as well as pointer 118 in diagram 117), a five-digit binary code 11111 ₂ = 1F ₁₆ is stored in register 58, and a signal 0 is generated at the output of RND generator 55. In the next step, the pointer 118 moves clockwise and locks in an adjacent position, the generator 55 switches to state S2, in which SRND = 01111 ₂ = 0F ₁₆ , RND = 0, etc. This process is cyclically repeated, the pointer 118 rotates in a circle, sequentially passing through all possible states S _i .

Parallel loading of the register 58 in an arbitrary cycle leads to the forced installation of the generator 55 in one of the specified states, in this example, in the states S3, S11, S19 or S27. These states are preferably selected so that in diagram 117 the arcs S3-S11, S11-S19, S19-S27 and S27-S3 have approximately equal lengths (see indicators 119 and 120, which divide the circle into four approximately equal parts). In the process of operation of the scrambler, the generator 55 is relatively rare, with equal probability is set in these states, and in the intervals between such settings, the pointer 118 continues to uniform (step) clockwise rotation.

The choice of several (and not one) given states to which the generator 55 goes over at the moments of its parallel loading is advisable in those cases when the number of states of the generator is large enough, and during a full turn of the pointer 118 the probability of parallel loading of the register 58 is close to unity. Therefore, if the pointer 118 periodically “breaks” from uniform rotation and falls into the same predetermined state, then the likelihood that it has time to complete at least one full revolution becomes low. In other words, some states of the generator 55 will be used less frequently than others, and then the properties of the “canonical” pseudo-random sequence of bits noted earlier (when describing the generator 1, see FIG. 1) will be lost to some extent, which is undesirable. The presence of several fixed installation points, evenly distributed over the diagram 117, evens out the probabilities of using all possible states of the generator 55.

As shown in diagrams 126 and 127 (FIG. 8), one of the codes causing the generator 55 to be forced to a fixed state is SDATA = CODE ₁ = 62 ₁₆ = 01100010 ₂ . This code is present in register 74 in the time interval T8-T9 and, as already noted, the decoder 75 responds to it by preparing register 58 to receive the parallel LOAD ₁ code from inputs 79. This code in this example is 0E ₁₆ = 01110 ₂ and corresponds to the state S11 of the generator 55 (see table. 116 in Fig.7, a). Thus, at time T9, the chain of successive transitions ... S16, S17, ..., S23, S24 is broken, and instead of switching to the next state S25, the generator 55 “jumps” to the state S11. After this, a new chain of successive transitions is formed: S11, S12, ..., S18, S19, ... - until the next situation arises in which this circuit breaks, and then the next chain is formed with one of the initial states S3, S11, S19 or S27 etc.

The scrambled DLINE * data received from line 51 synchronizes the generator 63 with phase-locked loop (Fig. 4), as a result, the signal CLK * is generated at its output, and its inverse value is generated at the output of the inverter 89 (diagrams 130, 138, 131 in FIG. 9). The SDIN signal (diagram 132) at the output of the trigger 85 repeats the DLINE * signal with a delay of half the clock period, while the SDIN signal, as already noted, practically does not contain phase distortion (jitter). The scrambled SDIN data passes sequentially through the register 83. After filling it, the SDATA * data (diagram 133), up to the transmission delay, coincides with the SDATA data in the scrambler register 74 (diagram 126).

This follows from the fact that, firstly, the data source for both registers is common - the output of the Exclusive OR 56 element, and, secondly, nothing prevents the simultaneous (up to a transmission delay) filling of both registers with the same data. Since the decoders 75 and 84 are identical, and the data at their inputs are the same, the signals at the outputs of these decoders are also the same (up to a transmission delay). It follows that the previously considered process of setting the generator 55 to a certain state also proceeds in descrambler 62, namely, in the time interval T8-T9 (Fig. 9), the signal J * = 1 is formed at the input P / S * of register 64 ( chart 134), at time T9, a parallel OE ₁₆ code corresponding to state S11 is received in register 64.

Regardless of the history of the generator of the pseudo-random bit sequence of the descrambler 62, starting from the moment T9 (Fig. 9), this generator is synchronized with the generator 55 of the scrambler 54 in the sense that the bit sequences generated by both generators coincide. Undefined states and signals in the initial period when there was no code synchronization between the generators are marked with “X” in diagrams 135, 136, 137 and 139.

Starting from moment T9, the scrambling RND (diagram 124 in Fig. 8) and the descrambling RND * (diagram 136 in Fig. 9) the bit sequences coincide, therefore, the DIN signal (diagram 137) of the descrambled data coincides with the DATA signal (diagram 123) at the input 61 scramblers accurate to transmission delay. The output DATA * signal (diagram 139) of the data, "cleared" of possible multiple switching at the boundaries between bit intervals, is sent to the output 89 of the descrambler and is accompanied by a signal CLK *. Thus, the input signals DATA and CLK are converted into coincident (up to a transmission delay) output signals DATA * and CLK *.

The frequency of repetition of the moments of synchronous installation of registers 58 and 64 in the same state (moments of code synchronization) depends on the data transfer rate, as well as on the bit depth and the number K of the codes CODE ₁ , CODE ₂ , ..., CODE _K recognized by the decoders 75 and 84.

With K = 1 and a bit width of register 74 (83) equal to 8, in the scrambled data stream, on average, in each 256-bit chain, one sought code will be found, equal to CODE ₁ . With a data transfer rate of 10 Mbit / s, the average repetition rate of the synchronization moments is 10,000,000 / 256 = 39,062.5 Hz. At K = 4, the frequency of the synchronization moments increases four times and amounts to 156250 Hz.

To reduce the probability of false recognition of codes CODE ₁ , CODE ₂ , ..., CODE _{To the} descrambler decoder 84 in connection with the receipt of 83 error bits from the communication line into the register, the bit capacity of this register (as well as register 74) can be increased, for example, to 20 bits .

Below is the operation of the proposed device as a whole.

As already noted, the device synchronously receives a data stream from the first channel, inserts command bits from the second channel into this stream, scrambles the resulting composite stream and transfers it over the communication line. On the far side, the composite stream is received from the line, the clock signal is extracted from it, the descrambling and distribution of the data and command bits contained in it are transmitted over the corresponding channels. The task is to ensure the coordinated operation of data transmission and reception units. Its solution is based on the use of "stochastic" synchronization, which does not require the introduction of overhead information in the bit stream transmitted over the line.

With this synchronization, random events associated with the "spontaneous" occurrence of some specified codes in the stream of scrambled data are simultaneously recorded at the receiving and transmitting sides. The frequency of occurrence of these events, as has been shown, is predictable and is determined by the selected data transfer rate, as well as by the bit depth and the number of CODE ₁ , CODE ₂ , ..., CODE _K codes set for recognition.

In the steady state, the staffing unit 69 (Fig. 5) transmits to the output 61 a stream of data coming from the first channel (see Fig. 10, time interval T0-T5). On the timing diagrams shown in Fig.10 - 13, the bits coming from the first and second channels are marked with numbers 1 and 2.

The data bit TxD1 (TxD2) is generated by an external source (for example, a computer) and fed to the input 70 (72) of the device (Figs. 4, 5) in response to the positive edge of the signal TxC1 (TxC2). This bit may be received at the data input of the trigger 102 with a certain delay, which is not taken into account in the time diagrams (Figs. 10, 11) to increase their visibility. The permissible delay (indicated by the symbol T * in the interval T0-T1 in diagram 155, Fig. 10) can approach one period of the clock signal CLK provided that the trigger DAT signal has sufficient time for stable operation of the trigger 102 at its data input. The DAT signal preset time is the interval between the end of the T * period and the closest positive edge of the CLK signal (time T1).

As shown in FIG. 10, in the process of transmitting previously unknown data, it happened that a DATA data bit was generated in the T4-T5 clock cycle, which subsequently generates the formation of pulses J and J *. This bit is marked with a dot in diagram 156 and is referred to as the synchronization bit for brevity. It should be remembered that this bit is not overhead — it belongs to the stream of user or other “useful” data, in this case transmitted over the first channel.

The synchronization bit in the same clock cycle (T4-T5, Fig. 10) is scrambled by the exclusive OR 56 element, and in the next clock cycle (T5-T6) it is loaded into the leftmost bit of the shift register 74, while the remaining bits are moved one position to the right. The SDATA code received in tact T5-T6 belongs to the set of codes CODE ₁ , CODE ₂ , ..., CODE _K and, therefore, it is detected by the decoder 75, as a result, a signal J = 1 is generated at its output. From this signal, control pulses are formed (see diagrams 144-146) with a duration equal to four clock cycles (the duration is determined by the capacity of the counter 97).

During the action of these pulses, the multiplexer 105 switches to receive TxD2 data from the second channel, the flow of TxC1 clock signals stops and four TxC2 pulses are generated (diagrams 153, 154, 147, 148). At the end of the action of the control pulses (diagrams 144-146), the stuffing unit 69 goes into the initial state, in which the data of the first channel is transmitted through it. When data is transmitted to line 51, after the synchronization bit “by inertia”, two more bits from the first channel are transmitted and only then four bits from the second channel (diagram 157).

Block 69 is insensitive to re-generated pulses J if they are input to the block in clocks T6-T7, T7-T8, T8-T9 or T9-T10 (the latter is shown by a dashed line in diagram 142), since the repeated positive edge of the signal F either absent, or confirms the previous installation of the trigger 101 in a single state, or does not affect this trigger due to the presence of a RESET pulse. If the reconfigured pulse J arrives at the input of block 69 in cycle T10-T11 (Fig. 11, diagram 160) or in subsequent cycles, then the insertion of command bits from the second channel is repeated (diagrams 161-175). Note that in the reconstructed pulse J in this case is generated by the synchronization bit from the second channel (marked with a dot in diagram 174). When data is transmitted to line 51, after the synchronization bit, two more bits are transmitted (one from the second and one from the first channel) and only then four bits from the second channel (diagram 175).

The synchronization bit enters the descrambler through the communication line and causes the formation of a pulse J * (Fig. 12, diagrams 176-180). The numbering of time points in the diagrams describing the operation of the data transmission unit 52 (Figs. 10-11) is not related to the numbering of time points in the diagrams describing the operation of the data reception unit 53 (Figs. 12-13) (Recall that the signal transmission delay is line 51 is not known in advance, so the time frames in blocks 52 and 53 are different).

From the signal J * = 1, control pulses are formed (see diagrams 182, 183) with a duration equal to four clock cycles (the duration is determined by the capacity of the counter 109). During the action of these pulses, the clock stream RxC1 stops and four pulses RxC2 are formed (diagrams 189, 190). At the end of the action of the control pulses (diagrams 182, 183), the destaffing unit 80 switches to its initial state, in which the synchronization pulses RxC1 of the first channel are formed. This takes into account that, as was shown, after the synchronization bit, two bits from the first channel and then four bits from the second channel are transmitted along the line (diagrams 176, 188). The necessary fragments of the composite DATA * data stream are fixed by the receivers of the first and second channels (receivers not shown) along the negative edges of the corresponding clock signals RxC1 and RxC2.

Block 80 (as well as block 69) is insensitive to re-generated pulses J * if they arrive in adjacent clock cycles T5'-T6 ', T6'-T7', T7'-T8 'or T8'-T9' (the latter is shown in diagram 180 with a dashed line), since the repeated positive edge of the J ** signal either confirms the previously performed installation of trigger 113 to a single state or does not affect this trigger due to the presence of a RESET * pulse. If the reconfigured pulse J * arrives at the input of block 80 in cycle T9'-T10 '(Fig. 13, diagram 199) or in subsequent cycles, then the output of the four clock pulses RxC2 to the second channel is repeated (diagrams 199-213).

From a comparison of the timing diagrams shown in FIGS. 10, 11 and 12, 13, it follows that the operation of blocks 69 and 80 is consistent. In any code situation, the insertion of bits from the second channel into the data stream generated on the transmitting side is recognized at the receiving side, extracted from the stream, and sent to the second channel.

The use of the proposed device can increase the data transfer rate due to two factors. The first factor is the exclusion from the data stream of a relatively large amount of overhead information designed to synchronize the operation of the descrambler with the scrambler, as well as the exclusion from the communication protocols of the corresponding software. The second factor is the exclusion from the data stream of overhead information indicating that the data belongs to the first or second channel.

Information sources

1. US Patent No. 5530959 (Fig. 1).

2. US Patent No. 5530959 (Fig. 5) (prototype).

Claims (3)

1. A device for transmitting data, comprising a data transmission unit and a data receiving unit connected to opposite sides of a communication line, a data transmission unit comprising a scrambler comprising a pseudo-random sequence of bits, a first exclusive OR element and a first amplifier, a pseudo-random sequence of bits contains a first shift register and the second exclusive-OR element, the inputs of which are connected to the outputs of the first shift register, and the output to the first input of the first exclusive-OR element and to the serial data input of the first shift register, the synchronization input of which is the scrambler synchronization input, the second input of the first exclusive-OR element is the scrambler data input, the output of the first amplifier is connected to the communication line, the data reception unit contains a descrambler containing a phase-locked oscillator, the second shift register, the third and fourth elements Exclusive OR and the second amplifier, the input of which is connected to the communication line, and the output to the input of the generator with phase-locked loop frequency, the output of which is the descrambler synchronization output, the outputs of the second shift register are connected to the inputs of the third exclusive-OR element, the output of which is connected to the first input of the fourth exclusive-OR element, characterized in that the data transfer unit further comprises a staffing unit, a first data input and a first the synchronization output of which is the data input and the first synchronization output of the first channel, the second data input and the second synchronization output of the stuffing unit are the data input the first synchronization output of the second channel, the scrambler further comprises a third shift register, a first decoder, a first trigger and a first inverter, the output of which is connected to the synchronization input of the first trigger, the input of the first inverter is connected to the synchronization inputs of the first and third shift registers, as well as to the third synchronization output stuffing unit, the control input of the first shift register is connected to the output of the first decoder and to the control input of the stuffing unit, the data output of which is connected to the input m of scrambler data, the input of the serial data of the third shift register is connected to the output of the first Exclusive OR element and to the data input of the first trigger, the output of which is connected to the input of the first amplifier, the inputs of the parallel data of the first shift register are connected to the outputs of the first decoder, the inputs of which are connected to the outputs of the third the shift register, the data receiving unit further comprises a destaffing unit, the first synchronization output of which is the second synchronization output of the first channel, the second the second synchronization output of the destaffing unit is the second synchronization output of the second channel, the descrambler further comprises a fourth shift register, a second decoder, a second and third triggers and a second inverter, the output of which is connected to the synchronization input of the second trigger and to the synchronization inputs of the second and fourth shift registers, the control input the second shift register is connected to the output of the second decoder and to the control input of the destaffing unit, the synchronization input of which is connected to the synchronization output descrambler, the output of the third trigger is the data output of the descrambler and is connected to the data outputs of the first and second channels of the device, the input of the serial data of the fourth shift register is connected to the second input of the fourth XOR element and to the output of the second trigger, the data input of which is connected to the output of the second amplifier, the inputs of the parallel data of the second shift register are connected to the outputs of the second decoder, the inputs of which are connected to the outputs of the fourth shift register, the input is The data of the second shift register is connected to the first input of the fourth XOR element, the output of which is connected to the data input of the third trigger, the synchronization input of which is connected to the synchronization output of the descrambler and to the input of the second inverter. 2. The device for transmitting data according to claim 1, characterized in that the staffing unit comprises a pulse generator, an inverter, a delay element, a counter, first and second AND elements, the first and fifth triggers and a multiplexer, the data inputs of which are the first and second data inputs block, and the control input is connected to the output of the fifth trigger, the first synchronization output of the block is connected to the output of the second element And, the second synchronization output of the block is connected to the output of the first element And and to the counter counter input, counter zero and second inputs of the trigger are connected to the output of the fourth trigger and to the input of the delay element, the output of which is connected to the zero setting input of the fourth trigger, the data input of which is connected to the counter output, the synchronization inputs of the first and fourth triggers are connected to the inverter output, the input of which is connected to the output of the pulse generator, with the synchronization inputs of the third and fifth triggers and with the first inputs of the first and second elements And is the third synchronization output of the block, the multiplexer output is connected to the data input t its trigger, the output of which is the data output of the block, the data input of the first trigger is the control input of the block, the output of the first trigger is connected to the synchronization input of the second trigger, the data input of which is connected to the positive voltage bus, the single output of the second trigger is connected to the second input of the first element And and with the data input of the fifth trigger, the zero output of the second trigger is connected to the second input of the second element I. 3. The device for transmitting data according to claim 1, characterized in that the destaffing unit comprises an inverter, a delay element, a counter, first and second elements AND, first, second and third triggers, the inverter input is connected to the first inputs of the first and second elements And and is the synchronization input of the block, the data input of the first trigger is the control input of the block, the synchronization inputs of the first and third triggers are connected to the inverter output, the zero setting inputs of the counter and the second trigger are connected to the output of the third trigger and to the ele The delay element, the output of which is connected to the zero-setting input of the third trigger, the data input of which is connected to the output of the counter, the counting input of which is connected to the output of the first AND element and is the second synchronization output of the block, the output of the second And element is the first synchronization output of the block, single and zero the outputs of the second trigger are connected to the second inputs of the first and second elements AND, the data input of the second trigger is connected to the positive voltage bus, the synchronization input of the second trigger is connected to zero mu output of the first trigger.

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