RU2262205C1 - Device for transferring data - Google Patents

Abstract

FIELD: data transfer devices for use with synchronous telecommunication systems.

SUBSTANCE: device implements simultaneous recognition by receipt and transfer blocks in a scrambled flow of bits, of certain codes, which are formed at random (not known previously) time moments. These moments, firstly, serve as direction points for sorting bits, belonging to different channels, and, secondly, are used for synchronization setting of generators of pseudo-random series of scrambler and de-scrambler bits to similar states. Therefore, service bits are excluded from data flow, meant for separation of flow across channels and service frames, meant for code synchronization of de-scrambler and scrambler.

EFFECT: higher speed of operation.

3 cl, 21 dwg

Description

The invention relates to general purpose electronic circuits, in particular to encoding, decoding and data conversion schemes for data transmission between subscribers remote from each other.

A device [1] for data transmission, comprising a data transmission unit and a data receiving unit connected to opposite sides of the communication line, the data transmission unit contains the first and second exclusive-OR elements, the first amplifier and the first shift register, the inputs of the second exclusive-OR element are connected to the outputs the first shift register, and the output to the first input of the first exclusive OR element, the input of the serial data of the first shift register is connected to the output of the first exclusive OR element and to the input of the first of the amplifier, the synchronization input of the first shift register is the device synchronization input, the second input of the first element is Exclusive OR is the device data input, the output of the first amplifier is connected to the communication line, the data reception unit contains a phase-locked loop generator, the second shift register, the third and fourth elements The exclusive OR and the second amplifier, the input of which is connected to the communication line, and the output to the input of the generator with phase-locked loop, the output of which is connected to the synchronization input The second shift register is the synchronization output of the device, the outputs of the second shift register are connected to the inputs of the third exclusive-OR element, the output of which is connected to the first input of the fourth exclusive-OR element, the output of which is the device data output, and the second input is connected to the serial data input of the second shift register and with the output of the second amplifier.

In the device [1], the data transmission and reception units perform, respectively, the functions of a scrambler and descrambler. The input data is converted by a scrambler to a form in which they can be considered as pseudo-random. The descrambler performs the inverse transform, i.e. restores the original data. Scrambling data allows you to replace long sequences of zeros or ones (and not only these sequences) with pseudo-random bits, which eliminates the possibility of loss of synchronization between blocks of data reception and transmission. In addition, the energy spectrum of the transmitted signal is leveled, which helps to reduce the level of crosstalk induced on neighboring twisted pairs of wires of the communication line cable.

The disadvantage of the device [1] is the propagation of errors that may occur when transmitting a signal over a communication line. So, a single error is converted into a triple, since the error bit is first directly transmitted to the output of the device data, and then, moving along the second shift register, it distortes the output data two more times.

A device for transmitting data [2] is known, comprising a data transmission unit and a data receiving unit connected to opposite sides of the communication line, a data transmission unit comprising a scrambler comprising a pseudo-random sequence of bits, a first exclusive OR element and a first amplifier, a pseudo-random sequence of bits contains a first shift register and the second exclusive OR element, the inputs of which are connected to the outputs of the first shift register, and the output to the first input of the first element OR to the serial data input of the first shift register, the synchronization input of which is the scrambler synchronization input, the second input of the first element Exclusive OR is the scrambler data input, the output of the first amplifier is connected to the communication line, the data reception unit contains a descrambler containing a phase-locked oscillator , the second shift register, the third and fourth elements Exclusive OR and the second amplifier, the input of which is connected to the communication line, and the output to the input of the generator with phase by adjusting the frequency, the output of which is the descrambler synchronization output, the outputs of the second shift register are connected to the inputs of the third exclusive-OR element, the output of which is connected to the first input of the fourth exclusive-OR element.

In the device [2], the shift register of the data receiving unit (descrambler) is logically isolated from the communication line, so there is no multiplication of errors coming from the line.

The device [2] has two disadvantages.

The first drawback is that in order to maintain the synchronous operation of the shift registers of the scrambler and descrambler (in the event of a violation of the device’s synchronization or when it is turned on for the first time), it is necessary to periodically interrupt the transmission of useful data and transmit service information frames containing sufficiently long chains of synchronizing bits over the communication line. This reduces the effective data transfer rate on the line, complicates the exchange protocol and requires a considerable time for the descrambler to wait for the service frame in case of loss of synchronization. During this time, data transfer is not possible.

The second drawback is the lack of hardware for delimiting bits belonging to different channels when they are multiplexed over a communication line. Data from different channels can be packed into frames or other structural units, such as bytes. For example, the data of the first channel is placed at even positions of the byte, and the data of the second is at odd positions. To specify the boundaries between bytes, redundant bits must be entered into the data bitstream, which reduces the transmission rate. For example, according to US Pat. application US 2002 0191721 A1, to each byte in the bitstream is added the demarcation bit received from the generator of the pseudo-random sequence of bits. The data receiver detects the demarcation bits due to their consistent match with the reference pseudo-random bit sequence. Another way of delimiting bytes in a bitstream (US Pat. No. 6,011808) also involves adding a delimitation bit to each byte. This bit is formed by duplication and inversion of the zero bit of the transmitted byte. As a result, the beginning of the byte is accompanied by the transfer of combinations of bits 01 or 10. The data receiver detects the delimitation bits and zero data bits due to their statistically stable coincidence with codes 01 or 10. Both methods of introducing the delimitation bits are uneconomical - you have to enter one service bit for every eight data bits bit.

Both of the above disadvantages reduce the speed of data transmission through the device [2].

The purpose of the invention is to increase the speed of data transmission through the device.

The goal is achieved in that in a device for transmitting data containing a data transmission unit and a data receiving unit connected to opposite sides of the communication line, the data transmission unit comprises a scrambler comprising a pseudo-random sequence of bits, a first exclusive OR element and a first amplifier, a pseudo-random sequence of bits contains the first shift register and the second exclusive-OR element, the inputs of which are connected to the outputs of the first shift register, and the output to the first input of the first The exclusive OR element and to the serial data input of the first shift register, the synchronization input of which is the scrambler synchronization input, the second input of the first exclusive OR element is the scrambler data input, the output of the first amplifier is connected to the communication line, the data reception unit contains a descrambler containing a phase-locked oscillator frequencies, the second shift register, the third and fourth elements exclusive OR and the second amplifier, the input of which is connected to the communication line, and the output to the generator input In the case of phase-locked loop, the output of which is the descrambler synchronization output, the outputs of the second shift register are connected to the inputs of the third exclusive-OR element, the output of which is connected to the first input of the fourth exclusive-OR element. The data transmission unit further comprises a data multiplexing unit, the first data input and the first synchronization output of which are the data input and the first synchronization output of the first channel, the second data input and the second synchronization output of the data multiplexing unit are the data input and the first synchronization output of the second channel, the scrambler further comprises third shift register, first decoder, first trigger and first inverter, the output of which is connected to the synchronization input of the first trigger, input the first inverter is connected to the synchronization inputs of the first and third shift registers, as well as to the third synchronization output of the data multiplexing unit, the control input of the first shift register is connected to the output of the first decoder and to the correction input of the data multiplexing unit, the multiplexed data output of which is connected to the scrambler data input, the input of the serial data of the third shift register is connected to the output of the first XOR element and to the data input of the first trigger, exit which is connected to the input of the first amplifier, the inputs of the parallel data of the first shift register are connected to the outputs of the first decoder, the inputs of which are connected to the outputs of the third shift register, the data receiving unit further comprises a data demultiplexing unit, the first data output and the first synchronization output of which are the data output and the second the synchronization output of the first channel, the second data output and the second synchronization output of the data demultiplexing unit are the data output and the second output The second channel, the descrambler additionally contains the fourth shift register, the second decoder, the second and third triggers and the second inverter, the output of which is connected to the synchronization input of the second trigger and to the synchronization inputs of the second and fourth shift registers, the control input of the second shift register is connected to the output of the second a decoder and with a correction input of the data demultiplexing unit, the data input of which is connected to the output of the third trigger, and the synchronization input is connected to the synchronization output and descrambler, the input of the fourth data of the fourth shift register is connected to the second input of the fourth exclusive-OR element and to the output of the second trigger, the data input of which is connected to the output of the second amplifier, the inputs of the parallel data of the second shift register are connected to the outputs of the second decoder, the inputs of which are connected to the outputs of the fourth the shift register, the input of the serial data of the second shift register is connected to the first input of the fourth exclusive-OR element, the output of which is connected to data input of the third trigger, the synchronization input of which is connected to the synchronization output of the descrambler and to the input of the second inverter.

The data multiplexing unit contains a pulse generator, an inverter, an And element, first-fourth triggers and a multiplexer, the data inputs of which are the first and second data inputs of the block, and the control input is connected to the zero output of the fourth trigger and is the second block synchronization output, the first block synchronization output connected to the output of the fourth trigger, the synchronization input of which is connected to the synchronization input of the third trigger, with the output of the pulse generator and with the input of the inverter and is the third output block synchronization, the output of the third trigger is the output of the multiplexed data of the block, the data input of the first trigger is connected to the first input of the And element and is the input of the block correction, the second input of the element And is connected to the output of the first trigger, the synchronization input of which is connected to the synchronization input of the second trigger and the output inverter, the zero output of the second trigger is connected to its data input, and its zero setting input is connected to the output of the And element, the multiplexer output is connected to the data input of the third trigger, the output is w cerned latch connected to the input of the fourth flip-flop data.

The data demultiplexing unit contains the first to seventh triggers, the inverter and the And element, the inverter input is connected to the synchronization inputs of the third and sixth triggers and is the synchronization input of the block, the inverter output is connected to the synchronization inputs of the first, second and seventh triggers, the data inputs of the fourth and fifth triggers are connected and are the block data input, the first trigger data input is the block correction input, the fourth and fifth trigger outputs are the first and second block data outputs, the synchronization input of the fourth trigger is connected to the zero output of the seventh trigger and is the first block synchronization output, the fifth trigger synchronization input is connected to the seventh trigger output and is the second block synchronization output, the zero output of the first trigger is connected to the first input of the And element, the second input of which is connected to the output of the third the trigger, the data input of which is connected to the output of the first trigger, the data input of the seventh trigger is connected to the output of the sixth trigger, the data input of which is connected to the output of the second igger, the data input of which is connected to its zero output, and the input of setting zero - with the output of the element I.

Figure 1, a and b presents a functional diagram of a known generator of a pseudo-random sequence of bits and a table is a pointer to the points of connection of the feedback circuit of this generator; figure 2 is a functional diagram of a known device [1] for data transmission; figure 3 is a functional diagram of a known device [2] for data transmission; figure 4 is a functional diagram of the proposed device for data transmission; figure 5 is a functional diagram of the data multiplexing unit of the proposed device; figure 6 is a functional block diagram of the demultiplexing data of the proposed device; 7, a-c - table of states of the generator of a pseudo-random sequence of bits, a state diagram of this generator and an example of a code situation that explains the operation of the proposed device; on Fig - timing diagrams of the operation of the scrambler of the proposed device; figure 9 is a timing diagram of the descrambler of the proposed device; figure 10-figure 18 is a timing diagram explaining the data transfer process of the proposed device in different code situations.

The pseudo-random sequence of bits generator 1 (Fig. , the input 5 synchronization of the shift register 2 is the synchronization input of the generator 1 of the pseudo-random sequence of bits. The direction of data shift in register 2 is shown by arrow 6. The bit numbers M and N of register 2 are selected from shown in Fig. 1, b of table 7 — pointer of the connection points of the feedback circuit.

The known [1] device 8 for transmitting data (FIG. 2) contains data transmission unit 10 (scrambler) and data reception unit 11 (descrambler) connected to opposite sides of the communication line 9, data transmission unit 10 contains the first 12 and second 13 exclusive elements OR, the first 14 amplifier and the first 15 shift register, inputs of the second 13 Exclusive element OR connected to the outputs of the first 15 shift register, and the output to the first input of the first 12 element Exclusive OR, the serial data input of the first 15 shift register is connected to the output the first 12 exclusive-OR elements and with the input of the first 14 amplifier, the synchronization input of the first 15 shift register is the device synchronization input 16, the second input of the first 12 exclusive-OR elements is the device data input 17, the output of the first amplifier 14 is connected to the communication line 9, reception block 11 the data contains a phase-locked oscillator 18, a second 19 shift register, a third 20 and a fourth 21 exclusive-OR elements and a second 22 amplifier, the input of which is connected to communication line 9, and the output to the input of generator 18 with automatic frequency locking, the output of which is connected to the synchronization input of the second 19 shift register and is the device synchronization output 23, the outputs of the second 19 shift register are connected to the inputs of the third 20 Exclusive OR elements, the output of which is connected to the first input of the fourth 21 elements of the Exclusive OR, whose output is the output 24 of the device data, and the second input is connected to the serial data input of the second 19 shift register and the output of the second amplifier 22. The data shift directions in the registers 15 and 19 are shown by arrows 25. An external data source 26 (for example, the first computer) is connected to the inputs 16 and 17 of the device 8. An external data receiver 27 (for example, a second computer) is connected to the outputs 23 and 24 of the device 8.

The known [2] device 28 for transmitting data (Fig. 3) comprises data transmitting unit 30 (scrambler) and data receiving unit 31 (descrambler) connected to opposite sides of the communication line 29, data transmitting unit 30 includes a pseudo-random bit sequence generator 32, the first The 33 XOR element and the first 34 amplifier, the pseudo-random sequence of bits generator 32 contains the first 35 shift register and the second 36 XOR element, the inputs of which are connected to the outputs of the first 35 shift register, and the output to the first input to the first 33 exclusive-OR elements and to the serial data input of the first 35 shift register, the synchronization input of which is the scrambler 30 synchronization input 37, the second input of the first exclusive-OR element is the scrambler 30 data input 38, the output of the first amplifier 34 is connected to the communication line 29, block 31 data reception (descrambler) contains a phase-locked oscillator 39, a second 40 shift register, a third 41 and a fourth 42 exclusive-OR elements and a second amplifier 43, the input of which is connected to the communication line 29, output - to the input of oscillator 39 with the phase locked loop, whose output is the output 44 of descrambler synchronization 31, the outputs of the second shift register 40 are connected to the inputs of a third exclusive-OR element 41, whose output is connected to first input 42 of the fourth exclusive-OR element.

In block 30, the output of the first 33 Exclusive OR element is connected to the input of the first 34 amplifier. The data receiving unit 31 also includes a multiplexer 45, the output of which is connected to the input of the serial data of the register 40, and the control input is the control input 46 of the device 28. The first data input of the multiplexer 45 is connected to the first input of the fourth exclusive-OR element 42. The second data input of the multiplexer 45 is connected to the second input of the fourth exclusive-OR element 42 and to the output of the second amplifier 43. The output of the fourth element 42 Exclusive OR is the data output 47 of the device 28. The synchronization input of the register 40 is connected to the synchronization output 44 of the device 28. The data shift directions in the registers 35 and 40 are shown by arrows 48. An external data source 49 (for example, the first computer) is connected to the inputs 37 and 38 of the device 28. An external data receiver 50 (for example, a second computer) is connected to the outputs 44 and 47 and to the input 46 of the device 28.

The proposed device for transmitting data (Fig. 4) comprises data transmitting unit 52 and data receiving unit 53 connected to opposite sides of the communication line 51, data transmitting unit 52 contains a scrambler 54, containing a pseudo-random sequence of bits generator 55, the first 56 exclusive OR element, and the first 57 amplifier, generator 55 of the pseudo-random sequence of bits contains the first 58 shift register and the second 59 XOR element, the inputs of which are connected to the outputs of the first 58 shift register, and the output to the first input the first 56 exclusive OR element and to the serial data input of the first 58 shift register, the synchronization input of which is the scrambler synchronization input 60, the second input of the first exclusive OR element is the scrambler data input 61, the output of the first amplifier 57 is connected to the communication line 51, reception unit 53 the data contains a descrambler 62 containing a phase-locked loop generator 63, a second 64 shift register, a third 65 and a fourth 66 exclusive-OR elements and a second amplifier 67, the input of which is connected to the line with monitor 51, and the output is to the input of a phase-locked loop generator 63, the output of which is synchronization output of descrambler 62, the outputs of the second 64 shift register are connected to the inputs of the third 65 exclusive-OR element, the output of which is connected to the first input of the fourth 66 exclusive-OR element.

The data transmission unit 52 also contains a data multiplexing unit 69, the first data input 70 and the first synchronization output 71 of which are the data input and the first synchronization output of the first channel, the second data input 72 and the second synchronization output 73 of the data multiplexing unit 69 are the data input and the first output of the second channel synchronization, the scrambler 54 further comprises a third 74 shift register, a first 75 decoder, a first 76 trigger and a first 77 inverter, the output of which is connected to the synchronization input of the first 76 t Igger, the input of the first 77 inverter is connected to the synchronization inputs of the first 58 and third 74 shift registers, as well as to the third synchronization output of the data multiplexing unit 69, the control input of the first 58 shift register is connected to the output of the first 75 decoder and to the correction input 78 of the data multiplexing unit 69 the output of the multiplexed data of which is connected to the input 61 of the scrambler data, the input of the serial data of the third 74 shift register is connected to the output of the first 56 element Exclusive OR and to the input the data of the first 76 trigger, the output of which is connected to the input of the first 57 amplifier, the inputs 79 of the parallel data of the first 58 shift register are connected to the outputs of the first 75 decoder, the inputs of which are connected to the outputs of the third 74 shift register.

The data receiving unit 53 also contains a data demultiplexing unit 80, the first 81 data output and the first 82 synchronization output of which are the data output and the second synchronization output of the first channel, the second 83 data output and the second 84 synchronization output of the data demultiplexing unit 80 are the data output and the second output the second channel synchronization, the descrambler 62 further comprises a fourth 85 shift register, a second 86 decoder, a second 87 and a third 88 triggers and a second 89 inverter, the output of which is connected to the input of the synchronization of the second 87 trigger and to the synchronization inputs of the second 64 and fourth 85 shift registers, the control input of the second 64 shift register is connected to the output of the second 86 decoder and to the correction input 90 of the data demultiplexing unit 80, the data input 91 of which is connected to the output of the third 88 trigger, and synchronization input - with descrambler synchronization output 68, the fourth data input of the fourth 85 shift register is connected to the second input of the fourth 66 exclusive-OR element and to the output of the second 87 trigger, input yes which is connected to the output of the second 67 amplifier, the inputs 92 of the parallel data of the second 64 shift register are connected to the outputs of the second 86 decoder, the inputs of which are connected to the outputs of the fourth 85 shift register, the serial data input of the second 64 shift register is connected to the first input of the fourth 66 element XOR the output of which is connected to the data input of the third 88 trigger, the synchronization input of which is connected to the output 68 of the synchronization of the descrambler 62 and to the input of the second 89 inverter. Arrows 93 show the data shift directions in registers 58, 64, 74, and 85.

The data multiplexing unit 69 (Fig. 5) contains a pulse generator 94, an inverter 95, an AND element 96, a first 97, a second 98, a third 99, a fourth 100 triggers and a multiplexer 101, the data inputs of which are the first 70 and second 72 data inputs of the block 69 and the control input is connected to the zero output of the fourth 100 trigger and is the second 73 synchronization output of block 69, the first 71 synchronization output of block 69 is connected to the output of the fourth 100 trigger, the synchronization input of which is connected to the synchronization input of the third 99 trigger, with the output of the generator 94 and pulses and with the input of the inverter 95 and is the third 60 synchronization output of block 69, the output of the third 99 trigger is output 61 of the multiplexed data of block 69, the data input of the first 97 trigger is connected to the first input of AND element 96 and is the input 78 of the correction block 69, the second input of the element And 96 is connected to the output of the first 97 trigger, the synchronization input of which is connected to the synchronization input of the second 98 trigger and to the output of the inverter 95, the zero output of the second 98 trigger is connected to its data input, and its zero-setting input is connected to the elem NTA and 96, the output of multiplexer 101 is connected to the input of the third data flip-flop 99, the output of the second flip-flop 98 is connected to the data input of the fourth flip-flop 100.

Block 80 demultiplexing data (6) contains the first 102, second 103, third 104, fourth 105, fifth 106, sixth 107, seventh 108 triggers, inverter 109 and element And 110, the input of the inverter 109 is connected to the synchronization inputs of the third 104 and sixth 107 triggers and is the synchronization input of the block, the output of the inverter 109 is connected to the synchronization inputs of the first 102, second 103 and seventh 108 triggers, the data inputs of the fourth 105 and fifth 106 of the triggers are connected and are the data input 91 of the block 80, the data input of the first 102 trigger is the input 90 correction block 80, you the odes of the fourth 105 and fifth 106 triggers are the first 81 and second 83 data outputs of block 80, the synchronization input of the fourth 105 trigger is connected to the zero output of the seventh 108 trigger and is the first 82 synchronization output of the block 80, the synchronization input of the fifth 106 trigger is connected to the output of the seventh 108 trigger and is the second 84 synchronization output of block 80, the zero output of the first 102 trigger is connected to the first input of AND element 110, the second input of which is connected to the output of the third 104 trigger, the data input of which is connected to the output of the first 1 02 trigger, the data input of the seventh 108 trigger is connected to the output of the sixth 107 trigger, the data input of which is connected to the output of the second 103 trigger, the data input of which is connected to its zero output, and the zero setting input is connected to the output of the And 110 element.

Table 111 (FIG. 7 a) provides a list of states of the pseudo-random bit sequence generator 55; the state diagram 112 of this generator (Fig. 7, b) reflects the movement of the current state indicator 113 along the ring path; lines 114 and 115 divide the diagram into four sectors. Table 116 (Fig. 7, c) shows an example of a code situation explaining the operation of the proposed device.

Timing diagrams 117 and 118 (Fig. 8) correspond to the signals at the inputs 60 and 61 of the scrambler 54; chart 119 - the signal at the output of the element Exclusive OR 59; chart 120 - the signal at the output of the element Exclusive OR 56; chart 121 - signals at the outputs of the register 74; chart 122 - the signal at the control input P / S register 58 (point 78); chart 123 - states of the generator 55 of the pseudo-random sequence of bits; chart 124 is a signal at the input of amplifier 57.

Timing diagram 125 (Fig.9) correspond to the signal at the output of amplifier 67; chart 126 - the signal at the output of the inverter 89; chart 127 - the signal at the output of the trigger 87; chart 128 - the signals at the outputs of the register 85; chart 129 - the signal at the control input P / S * register 64 (point 90); chart 130 - the state of the register 64 of the generator of the pseudo-random bit sequence of the descrambler 62; chart 131 - the signal at the output of the element Exclusive OR 65; chart 132 - the signal at the output of the element Exclusive OR 66; chart 133 - the signal at the input of the inverter 89; chart 134 shows the signal at the output of 91 descrambler 62.

Timing diagrams 135 and 136 (figure 10) correspond to the signals at the input and output of the inverter 95 (figure 5); diagrams 137 and 138 - to the signals at the data input and the output of the trigger 97; diagrams 139 and 140 - to signals at the input of the zero setting and the output of the trigger 98; diagrams 141 and 142 - to signals at points 71 and 70; diagrams 143 and 144 - to signals at points 73 and 72; diagrams 145 and 146 to the signals at the data input and the output of the trigger 99; diagram 147 shows the signal at the output of trigger 76 (Fig. 4).

Timing diagrams 148 and 149 (Fig. 11) correspond to the signals at the input and output of the inverter 95 (Fig. 5); diagrams 150 and 151 - to signals at the data input and the output of the trigger 97; diagrams 152 and 153 - to the signals at the input of the zero setting and the output of the trigger 98; diagrams 154 and 155 — to signals at points 71 and 70; diagrams 156 and 157 - to signals at points 73 and 72; diagrams 158 and 159 - to signals at the data input and the output of the trigger 99; chart 160 - the signal at the output of the trigger 76 (figure 4).

Timing diagrams 161 and 162 (Fig. 12) correspond to signals at the input and output of inverter 95 (Fig. 5); diagrams 163 and 164 - to signals at the data input and the output of the trigger 97; diagrams 165 and 166 — to signals at the input of the zero setting and the output of the trigger 98; diagrams 167 and 168 - to signals at points 71 and 70; diagrams 169 and 170 - to signals at points 73 and 72; diagrams 171 and 172 - to signals at the data input and the output of the trigger 99; diagram 173 - the signal at the output of the trigger 76 (figure 4).

Timing diagrams 174, 175 and 176 (FIG. 13) correspond to signals at the data input, synchronization input, and trigger output 87 (FIG. 4); chart 177 - signal in the input bit of the register 85; diagrams 178 and 179 - signals at the input of data and the output of the trigger 102 (Fig.6); diagrams 180 and 181 - to the signals at the output of the trigger 104 and at the output of the element And 110; diagrams 182 and 183 - to signals in the register 64 and at the output of the element Exclusive OR 65; diagrams 184, 185 and 186 to signals at the data input, synchronization input, and trigger 88 output; diagrams 187 and 188 - signals at the input of data and the output of the trigger 107; diagrams 189 and 190 - to signals at points 84 and 82; diagrams 191 and 192 - to signals at points 83 and 81.

Timing diagrams 193, 194 and 195 (Fig. 14) correspond to signals at the data input, synchronization input, and trigger output 87; chart 196 - the signal in the input bit of the register 85; diagrams 197 and 198 — to signals at data input 19 and trigger output 102; diagrams 199 and 200 to the signals at the output of the trigger 104 and at the output of the element And 110; diagrams 201 and 202 - to signals in the register 64 and at the output of the element Exclusive OR 65; diagrams 203, 204, and 205 show signals at the data input, synchronization input, and trigger 88 output; diagrams 206 and 207 — to signals at the input of data and the output of trigger 107; diagrams 208 and 209 - to signals at points 84 and 82; diagrams 210 and 211 to signals at points 83 and 81.

Timing diagrams 212, 213 and 214 (Fig. 15) correspond to signals at the data input, synchronization input, and trigger output 87; chart 215 - the signal in the input bit of the register 85; diagrams 216 and 217 to the signals at the data input and the output of the trigger 102; diagrams 218 and 219 - to the signals at the output of the trigger 104 and at the output of the element And 110; diagrams 220 and 221 - to signals in the register 64 and at the output of the element Exclusive OR 65; diagrams 222, 223, and 224 — to signals at the data input, synchronization input, and trigger 88 output; diagrams 225 and 226 - to the signals at the data input and the output of the trigger 107; diagrams 227 and 228 - to signals at points 84 and 82; diagrams 229 and 230 - to signals at points 83 and 81.

Timing diagrams 231, 232 and 233 (Fig. 16) correspond to signals at the data input, synchronization input, and trigger output 87; chart 234 shows a signal in the input bit of register 85; diagrams 235 and 236 - to the signals at the data input and the output of the trigger 102; diagrams 237 and 238 - to the signals at the output of the trigger 104 and at the output of the element And 110; diagrams 239 and 240 - to signals in the register 64 and at the output of the element Exclusive OR 65; diagrams 241, 242 and 243 - to signals at the data input, synchronization input, and trigger 88 output; diagrams 244 and 245 - to signals at the data input and output of the trigger 107; diagrams 246 and 247 - signals at points 84 and 82; diagrams 248 and 249 - to signals at points 83 and 81.

Timing diagrams 250, 251 and 252 (FIG. 17) correspond to signals at the data input, synchronization input, and trigger output 87; chart 253 - signal in the input bit of the register 85; diagrams 254 and 255 - to signals at the data input and the output of the trigger 102; diagrams 256 and 257 - signals at the output of the trigger 104 and at the output of the element And 110; diagrams 258 and 259 - to signals in the register 64 and at the output of the element Exclusive OR 65; diagrams 260, 261, and 262 — to signals at the data input, synchronization input, and trigger 88 output; diagrams 263 and 264 - to signals at the data input and output of the trigger 107; diagrams 265 and 266 - signals at points 84 and 82; diagrams 267 and 268 - to signals at points 83 and 81.

Timing diagrams 269, 270 and 271 (Fig. 18) correspond to signals at the data input, synchronization input, and trigger output 87; chart 272 - signal in the input bit of the register 85; diagrams 273 and 274 - to the signals at the data input and the output of the trigger 102; diagrams 275 and 276 - to the signals at the output of the trigger 104 and at the output of the element And 110; diagrams 277 and 278 - to signals in the register 64 and at the output of the element Exclusive OR 65; diagrams 279, 280, and 281 show signals at the data input, synchronization input, and trigger 88 output; diagrams 282 and 283 - to signals at the input of data and the output of trigger 107; diagrams 284 and 285 - to signals at points 84 and 82; diagrams 286 and 287 - to signals at points 83 and 81.

The following is a brief description of the operation of known devices [1, 2].

Scramblers and descramblers typically contain pseudo-random bit sequence generators or fragments of such generators. An example of constructing a generator of a pseudo-random sequence of bits is shown in figure 1 (see the book. P. Horowitz, W. Hill. "The Art of Circuit Engineering": In three volumes - M .: Mir, 1993. - 2 tons). The generator 1 is made on the basis of the shift register 2 with the exclusive element OR (XOR) 3 in the feedback circuit.

In the initial state, any non-zero code is present in register 2 (the initial setup circuit of the register is not shown). Under the influence of the positive edges of the clock signal CLK at input 5, this code circulates in the generator and simultaneously modifies. In each clock cycle (CLK signal period), the code advances in register 2 in the direction indicated by arrow 6, while a bit of data from output 4 is entered into the freed register bit. As an output from the generator, you can use the output of the exclusive OR 3 element or the output of any bit of the register.

In the general case, when using the M-bit register 2, the feedback circuit is connected to the digits with the numbers M and N (M> N). In order for a pseudo-random sequence of bits with a repetition period equal to 2 ^M -1 to be formed at the output of the generator, it is necessary to select the connection points of the feedback circuit in accordance with table 7 (Fig. 1, b), which describes a number of generators of different lengths. When the generator is operating in register 2, all possible M-bit codes are generated, with the exception of zero. (Note that in all the devices described below it is possible to use advanced generators that do not have forbidden states, see, for example, Prince B. Shevkoplyas "Microprocessor Structures. Engineering Solutions": Reference Book. - Supplement One. - M: Radio and Communication, 1993. - 256 p.)

A pseudo-random sequence of bits with a repetition period equal to 2 ^M -1 has the following properties.

1. In the full cycle (2 ^M -1 cycles) the number of logs. 1, formed at the output 4 of generator 1, is one more than the number of logs. 0. Additional log. 1 appears due to the exclusion of a state in which a zero code would be present in register 2. This can be interpreted so that the probability of occurrence of the log. 0 and the log. 1 at the output 4 of the generator 1 are almost the same.

2. In a full cycle (2 ^m - 1 ticks) half of the series from consecutive logs. 1 has a length of 1, one fourth of a series is a length of 2, one eighth of a length of 3, etc. Series from a log have the same properties. 0 taking into account the missed log. 0. This suggests that the probabilities of the appearance of "eagles" and "tails" do not depend on the outcome of previous "tosses." Therefore, the probability that a series of consecutive logs. 1 or log. 0 will end on the next toss, equal to 1/2.

3. If the sequence of the full cycle (2 ^M -1 cycles) is compared with the same sequence, but cyclically shifted by any number of cycles W (W is not zero or a multiple of 2 ^m - 1), then the number of mismatches will be one more, than the number of matches.

The most common are two main schemes of devices for data transmission (devices of the "scrambler-descrambler" type): with non-isolated and isolated (from the communication line) generators of pseudo-random bit sequences.

In the device 8 (FIG. 2 [1]), the scrambler 10 and the descrambler 11 are made using fragments of the pseudorandom sequences of bits considered earlier 1 (see FIG. 1). An additional Exclusive OR 12 element is introduced into the feedback loop of the generator based on the shift register 15. A similar generator based on the shift register 19 with an open feedback loop is used in the descrambler.

All processes taking place in the device 8 are synchronized from a clock located in an external data source 26 (it can also be placed in block 10). The clock generates a signal CLK - a continuous sequence of clock pulses with a duty cycle equal to two. In each clock cycle, the next bit of the transmitted DATA data is fed to input 17 of the scrambler 10, and in the shift register 15, the accumulated code moves one bit to the right (arrow 25).

Assuming that data source 26 sends a long log sequence to scrambler 10. 0 (DATA = 0), the Exclusive OR 12 element can be considered as a repeater of the Y1 signal from the output of the Exclusive OR 13 element. In this situation, register 15 is actually closed in the ring and generates exactly the same pseudorandom sequence of bits as in the generator circuit considered earlier 1 (FIG. 1). If an arbitrary bit sequence is received from data source 26, then it interacts with the bit sequence from the output of the Exclusive OR 13. As a result, a new (scrambled) sequence of SCRD data bits is generated, which is close in structure to random. This sequence, in turn, advances in register 15, forms the bit stream Y1 at the output of the exclusive OR 13 element, etc.

A scrambled SCRD bit sequence passes through an amplifier 14, is transmitted over a communication line 9 (for example, over a twisted pair of wires of a multicore cable of an urban telephone network) and enters a descrambler 11, where it passes through an amplifier 22. Using a generator 18 with phase-locked loop frequency from the input signal SCRD * (from the output of amplifier 22) a clock signal CLK * is allocated, which is transmitted to the clock input C of register 19 and to the output 23 of device 8.

The generator 18 with phase-locked loop frequency can be performed according to one of the known schemes (see, for example, US Pat. No. 6,215.835 B1). It is designed to generate a highly stable CLK * clock based on continuous tracking of the SCRD * input signal. In this case, the negative edge of the signal CLK * is tied to the moments of change of the signal SCRD * (0 → 1 or 1 → 0), so that the positive edge of the signal CLK * is formed in the middle of the bit interval of the signal SCRD *, which corresponds to its steady-state value. Data shift in register 19 and reception of the next SCRD * bit to the freed bit occur at the positive edge of the CLK * signal. The descrambled DATA * data arrives at the data receiver 27 and is captured therein along the positive edges of the CLK * signal.

Due to the sufficient inertia of the generator 18, the CLK * signal is practically insensitive to the "jitter" of the SCRD * signal and its other short-term distortions caused by interference in the communication line 9. (Such use of a standard generator with phase-locked loop in telecommunication systems is generally accepted and will not be described further. )

DATA and DATA * data streams are accurate to the transmission delay. Indeed, in the steady state, the same codes are present in the shift registers 15 and 19, since the same data SCRD = SCRD * (taking into account the transmission delay) is supplied to the D inputs of these registers, and the clock frequency is the same. Therefore, Y2 = Y1, and, taking this into account,

DATA * -SCRD * ⊕Y2 = SCRD⊕Y2 = (DATA⊕Y1) ⊕Y2 = DATA⊕Y1⊕Y1 = DATA⊕0 = DATA.

The considered method of scrambling-descrambling data does not require the use of any special initial synchronization procedure (as in the device [2]). After filling in the shift register 19, as was shown, the pseudorandom bit sequence generators based on registers 15 and 19 work synchronously (their states are always the same) and generate the same signals Y1 and Y2. When a single error occurs in the communication line 9, the code synchronization (the identity of the contents of registers 15 and 19) is temporarily violated, but then automatically restored as soon as the correct data is again filled in the register 19. However, during the progress of the erroneous bit in the shift register 19, namely during periods first it hits one and then to the other input of the Exclusive OR 20 element, the Y2 signal takes an incorrect value twice. This leads to the propagation of a single error - it first appears in the DATA * signal at the moment it arrives from the line and then occurs two more times with a subsequent twofold distortion of the Y signal.

In the device 28 (Fig. 3 [2]), pseudo-random bit sequence generators isolated from the communication line 29 are used. Their initial code synchronization is performed using descrambler hardware and software source 49 and data receiver 50.

The hardware includes a multiplexer 45 (MUX) and a program-controlled output 46 of the data receiver 50, on which the control signal F is generated. During normal operation of the scrambler-descrambler system, the data receiver 50 constantly supports the output signal F = 0. The signal Z2 from the output of the Exclusive OR 41 element is transmitted to the output of the multiplexer 45, the pseudo-random bit sequence generator based on register 40 is isolated from external influences.

Assume that in the initial state the descrambler is not synchronized with the scrambler. Such a situation may arise, for example, after turning on the supply voltage of the receiving side equipment, after an error in the operation of the descrambler generator 39 due to the influence of interference on the communication line or for other reasons. In the absence of code synchronization between the scrambler and descrambler, the contents of registers 35 and 40 do not match, the received DATA * data stream is erroneous and does not coincide with the transmitted DATA data stream.

Upon detection of a stable chaotic data stream DATA * (in which there is no separation of information frames caused by the protocol of exchange, etc.), the receiver generates a signal F = 1. As a result, the multiplexer 45 begins to transmit to the input D of the register 40 a signal of scrambled data SCRD *, as in the previously discussed device [1] (see figure 2).

The exchange protocol provides for the transfer of data in the form of a sequence of frames. Groups of regular frames are interspersed with overhead frames. For example, after a group of 1000 ordinary frames, one official follows. It, in particular, contains a synchronization sequence of a certain number (for example, 256) of zero bits. When these bits (DATA = 0) are output to the scrambler, the Exclusive OR 33 element acts as a repeater of the Z1 signal from the output of the Exclusive OR 36 element. Therefore, in this case, the scrambled SCRD signal is a fragment of a “true” pseudo-random bit sequence, in the sense that it not mixed with a stream of arbitrary DATA data and generated only by the 32 scrambler generator.

This sequence is automatically loaded into register 40 and passes through it, since F = 1. After the contents of the registers 35 and 40 are the same, the signal Z2 begins to repeat the signal Z1. Code synchronization is achieved. At the input of the data receiver 50 is fed a continuous sequence of logs. 0, because DATA * = DATA = 0. After confident detection of a sufficiently long (for example, containing 180 bits) sequence of logs. 0, the receiver 50 generates a signal F = 0 and thereby returns the generator of the pseudo-random descrambler bit sequence to the isolated operation mode. Now, code synchronization has not only been achieved, but also “saved” due to the logical isolation of register 40 from communication line 29. After the transmission of the service (synchronizing) frame is completed, the data source 49 proceeds with the transfer of a group of 1000 ordinary frames according to the exchange protocol adopted in the system.

Thus, in the device [2] to maintain synchronous operation of the shift registers of the scrambler and descrambler (in case of a violation of the synchronization of the device or when the receiver is initially turned on), it is necessary to periodically interrupt the transmission of useful data and transmit service information frames containing sufficiently long chains over the communication line sync bits (DATA = 0). As a result, the effective data transfer rate on the line decreases, and the exchange protocol is complicated. In addition, with an increase in the intervals between overhead frames (which is desirable for a more efficient transmission of useful data), the time it waits for the descrambler in the event of loss of code synchronization. During this time, the transfer of useful data is not possible.

Unlike the device [2], the proposed device (Fig. 4) implements two improvements to improve the data transfer rate.

The first improvement is that the restoration of code synchronization between the scrambler and the descrambler in the event of its loss occurs without the transmission of any service synchronizing code sequences over the communication line. Therefore, the flow of useful data is not interrupted, the synchronization recovery time is reduced.

The second improvement is that the information on the position of the boundaries between bits belonging to different channels is not explicitly transmitted along the line; The carriers of this information are random events that are recorded simultaneously by data transmission and reception units.

In general terms, the idea of the first improvement is as follows. The scrambler and descrambler contain pseudo-random sequence of bits isolated from the communication line with the same feedback structure. The scrambled bit stream is constantly analyzed by the scrambler and descrambler in order to find certain codes in it. The detection of each such code by the scrambler and descrambler leads to the simultaneous installation of both generators of the pseudo-random sequence of bits in a certain state corresponding to this code. Thus, the generators at random moments are simultaneously set to the same state as the transfer of useful data. These events occur relatively rarely, i.e. most of the time, the generators operate in the mode of "natural" sequential transition from the previous state to the next, as was shown in the description of the generator 1 (figure 1). If the code synchronization has not been broken, then the moments of installation of the generators only confirms it. If the code synchronization was previously lost, then it is restored upon the first detection of one of the given codes in the stream of scrambled data. Thus, synchronization overhead bits are not transmitted over the communication line.

The second improvement is also based on the fact that data transmission and reception units simultaneously (up to transmission delay) detect predetermined codes in a scrambled data stream. The moments of detection of such codes are random events. They are used to synchronize the operation of demultiplexing and data multiplexing units. If these blocks previously worked in antiphase (when data from the first channel was transferred to the second channel and vice versa), then after the detection of the first of the mentioned random events, correct synchronization is restored.

The following describes the operation of the components of the proposed device.

The shift registers 74 and 85 (FIG. 4) are intended for temporary storage of fragments of SDATA and SDATA * streams of scrambled data. In the steady state, these fragments are the same (coincide up to a transmission delay). Reception of the next bit in the register 74 (85) occurs on the positive edge of the signal at the clock input C of this register. Simultaneously with the reception of the next bit from input D, previously stored data is shifted to one bit to the right (arrow 93). In this example of the construction of the device, the width of the register 74 (85) is chosen to be eight, although it can be greater or less. The dynamics of the operation of the register 74 can be traced by the table 116 of its states (Fig.7, c).

The scrambler 54 pseudorandom bit sequence generator 55 contains a shift register 58 and an exclusive OR element 59. A similar descrambler pseudo random bit sequence generator 55 contains a shift register 64 and an exclusive OR element 65.

Shift registers 58 and 64 are intended for temporary storage of pseudo-random codes SRND and SRND *. In steady state, these codes are the same (coincide with an accuracy of transmission delay). The next bit in register 58 (64) is received from input D along the positive edge of the signal at synchronizing input C, provided that its control input P / S (P / S *), which sets the mode of parallel or serial data reception, has a log signal . 0. Simultaneously with the reception of the next bit from input D, the previously stored code is shifted by one bit to the right (along arrow 93). If at the control input P / S (P / S *) register 58 (64) there is a log signal. 1, then a parallel code from the group of inputs 79 (92) is received on the positive edge of the signal at the synchronizing input C into the register. In this example of the construction of the device, the width of the register 58 (64) is chosen equal to five, although it can be greater or less. In this case, the connection points of the XOR element 59 (65) to the register 58 (64) are selected in accordance with the table presented in figure 1, b.

The initial state of the register 58 may be any, including zero. The exit from the zero state occurs when a parallel code is written to the register from inputs 79. The scrambler initialization program provides for the output of some code CODE ₁ to its input 61, which is recognized by the decoder 75. If the code zero was initially present in register 58, the code CODE ₁ passes without change through the XOR element 56 and is sequentially loaded into the register 74. The decoder 75 responds to it by transferring the register 58 to the parallel loading mode (P / S = 1) and generating a non-zero code LOAD ₁ which is then received in p register 58 from inputs 79. Thus, the generator 55 leaves the forbidden state 000 ... 0. If the initial state of register 58 was nonzero, then issuing CODE ₁ to input 61 is useless, but does not lead to any undesirable consequences. It is also possible to set register 58 to a nonzero state (the corresponding input of register 58 to this state is not shown).

The initial state of the register 64 may also be any, including zero. This state is updated (becomes obviously non-zero) when one of the predefined codes (CODE ₁ and, possibly, others) is detected by the decoder 86 in the scrambled data stream.

The element Exclusive OR 56 (59, 65, 66) generates a log signal at the output. 1 only if the input signals have opposite logical values (log. 0 and log. 1). The exclusive OR elements 59 and 65 form the output signals RND and RND * of the pseudo-random bit sequence generators of the scrambler 54 and the descrambler 62. The exclusive OR elements 56 and 66 form the scrambled SCRD and descrambled DIN data signals.

D-type flip-flops 76, 87 and 88 receive data bits from input D along the positive edge of the signal at synchronization input C. Triggers 76 and 88 generate DLINE and DATA * output signals, in which the signal can change only once at the boundaries between bit intervals, while the input signals SCRD and DIN of these triggers at the boundaries between bit intervals can change many times due to the non-simultaneous occurrence of transients ("racing" signals) in circuits 58-59-56; 61-56 and 64-65-66; 87-66. Flip-flop 87 eliminates input jitter to a large extent (edge-jitter at the boundaries between bit intervals) due to the fact that a bit is received in this trigger at the center of the bit interval when the transients of the DLINE * signal have already ended. The residual jitter of the SDIN signal at the output of the trigger 87 is determined by the imperfect CLK * signal at the output of the generator 63. The initial states of the triggers 76, 87, and 88 are arbitrary.

Inverter 77 (89) converts the input signal to a log. 0 to the output signal log. 1, and vice versa - the input signal is a log. 1 to the output signal log. 0.

Generator 63 with phase-locked loop can be performed according to one of the known schemes (see, for example, US Pat. No. 6,215.835 B1). It is designed to generate a highly stable CLK * clock based on continuous tracking of the DLINE * input signal. The positive edge of the CLK * signal is tied to the moment the DLINE * signal changes (0 → 1 or 1 → 0), so that the negative edge of the CLK * signal is formed in the middle of the bit interval of the DLINE * signal, which corresponds to its steady-state value.

Due to the sufficient inertia of the generator 63, the CLK * signal is practically insensitive to the jitter of the DLINE * signal and its other short-term distortions caused by interference in the communication line 51. (Such use of a standard phase-locked oscillator in telecommunication systems is generally accepted and will not be described further.)

The decoder 75 (86) is designed to highlight in the stream of scrambled data passing through the shift register 74 (85), certain codes CODE ₁ , CODE ₂ , ..., СООЕ _к . When the decoder 75 (86) detects the indicated codes, the corresponding G-bit code LOAD ₁ , LOAD ₂ , ..., LOAD _k is generated at its outputs 79 (92) for subsequent parallel loading of the shift register 58 (64). In this example, the construction of the device K = 4, G = 5. If any code CODE ₁ , CODE ₂ , ..., CODE _{k is} detected, _the decoder 75 (86) also generates a single signal at the input P / S (P / S *) of the operating mode of the register 58 (64), preparing it for parallel reception data on the positive edge of the next sync pulse at input C.

The amplifier 57 (67) is designed to transmit (receive) a scrambled data signal to the line (from the line) 51. The parameters of the amplifiers 57 and 67 are determined by the type of communication line 51, which in the simplest version can be made in the form of a twisted pair of wires, coaxial or fiber cable. The communication line may contain sequentially connected repeaters, in which blocks of buffer memory can be used. Therefore, the signal transmission delay between the transmission unit 52 and the data receiving unit 53 may be significant and not known in advance (but constant).

The clock generator 94, located in the block 69 data multiplexing (figure 5), sets the pace of the entire device. At the output 60 of the generator 94, a continuous pulse train is formed with a duty cycle equal to two. Flip-flop 98 divides the input frequency by two, while the phase of the output signal ST is corrected, if necessary, by the RESET pulse from the output of the And 96 element. Trigger 100 acts as a repeater of the ST signal and "cleans" this signal from short-term false pulses at the moments when the RESET signal is generated at the output element And 96 (see diagrams 166 and 167 in Fig.12). The signals TxC1 and TxC2 from the outputs of the trigger 100 set the rate of receipt of data TxD1 and TxD2 on the first and second channels.

The next bit of data TxD1 (TxD2) comes from an external source (not shown) to the input of the device in response to the positive edge of the signal TxC1 (TxC2). The data bit TxD1 (TxD2) may come from an external source with some delay, which is not taken into account in the time diagrams (Fig.10-Fig.12) to increase their visibility. This delay (indicated by the T * symbol in the interval T8-T10 in diagram 144, Fig. 10) can approach two periods of the CLK clock, provided that the trigger 99 has enough DAT signal preset time at its input D. The DAT signal preset time represents is the interval between the end of the period T * and the nearest positive edge of the signal CLK (moment T10).

Data TxD1 and TxD2 of the first and second channels are "mixed" into a single DAT data stream using multiplexer 101. As shown in Fig. 5, when TxC2 = 1, multiplexer 101 transmits TxDl data of the first channel to the output, and when TxC2 = 0, TxD2 data second channel. Trigger 99 binds the boundaries of the bit intervals of the DATA signal to the positive edges of the CLK clock. The trigger 97 and the element And 96 form a pulse RESET zeroing of the trigger 98 upon receipt of a correction pulse J at the input 78 of the block 69 (diagrams 150-152 and 163-165 in FIG. 11 and FIG. 12).

In block 80 demultiplexing data (6), the input bit stream DATA * is divided into two streams - RxD1 (data of the first channel) and RxD2 (data of the second channel). The separation is performed by triggers 105 and 106, which are synchronized by the signals RxC1 and RxC2 from the outputs of the trigger 108. These signals are used by external data receivers of the first and second channels (receivers not shown) for synchronous reception of the RxD1 and RxD2 bits.

At input 68 of block 80, there is a continuous pulse train CLK * (copy of CLK signal from generator 94, see FIG. 5) with a duty cycle of two. Flip-flop 103 divides the input frequency by two, while the phase of the output signal CT *, if necessary, is corrected by the RESET * pulse from the output of the And 110 element. Flip-flop 107 performs the function of the signal repeater CT * and "cleans" this signal from short-term false pulses at the moments of signal formation RESET * at the output of AND element 110 (see diagrams 244 and 245 in FIG. 16, diagrams 263 and 264 in FIG. 17). The trigger 108 binds the output signals of block 80 to the negative edges of the signal CLK *. The triggers 102, 104 and the element And 110 form the pulse RESET * zeroing of the trigger 103 upon receipt of the correction pulse J * at the input 90 of the block 80 (diagrams 216-219, 235-238, 254-257 and 273-276).

The following is a description of the operation of a larger fragment of the proposed device. This fragment includes a scrambler 54, a communication line 51 and a descrambler 62.

The DATA input data and the accompanying synchronization signal CLK go to the inputs 61 and 60 of the scrambler 54. The positive edges of the CLK signal (moments T0, T1, ..., T18 in Fig. 8) correspond to the boundaries between the bit intervals of the DATA data signal, as shown in diagrams 117 and 118. On the positive edges of the signal CLK, the contents of the register 74 are changed (diagram 121), the generator 55 goes into new states (diagram 123). At the same time, for each positive edge of the CLK signal, the next pseudo-random RND bit is formed (diagram 119), which is added modulo two with the DATA data bit and converted into a scrambled SCRD data bit (diagram 120). At the end of the transient processes, at the moment of formation of the negative edge of the CLK signal, the SCRD bit is received in the trigger 76 (DLINE signal diagram 124) and transmitted through the amplifier 57 to the communication line 51.

In the time interval T8-T9 (Fig. 8), the decoder 75 generates a signal J = 1 at the input P / S of the operation mode control of the register 58 (diagram 122), preparing it for receiving parallel data at the time T9.

In the absence of parallel loading, the generator 55 of the pseudo-random sequence of bits sequentially, cyclically passes through a series of states S1, S2, S3, ..., S31, S1, S2, etc., as shown in Fig. 7, a, b (table 111 Diagram 112). In state S1 (see the first row of table 111, as well as pointer 113 in diagram 112), a five-digit binary code 11111 ₂ = 1F ₁₆ is stored in register 58, and a log signal is generated at the output of RND generator 55. 0. In the next step, the pointer 113 moves clockwise and is fixed at an adjacent position, the generator 55 switches to state S2, in which SRND: 01111 ₂ = 0F ₁₆ , RND = 0, etc. This process is cyclically repeated, the pointer 113 rotates in a circle, sequentially passing through all possible states S _i .

Parallel loading of the register 58 in an arbitrary cycle leads to the forced installation of the generator 55 in one of the specified states, in this example, in the states S3, S11, S19 or S27. These states are preferably selected so that in diagram 112 the arcs S3-S11, S11-S19, S19-S27 and S27-S3 have approximately equal lengths (see indicators 114 and 115, which divide the circle into four approximately equal parts). In the process of operation of the scrambler, the generator 55 is relatively rare, with equal probability is set to these states, and in the intervals between such settings, the pointer 113 continues to uniformly (stepwise) clockwise rotation.

The choice of several (and not one) given states to which the generator 55 goes at the moments of its parallel loading is advisable in those cases when the number of states of the generator is large enough, and during a full turn of the pointer 113, the probability of parallel loading of the register 58 is close to unity. Therefore, if the pointer 113 periodically “breaks” from uniform rotation and falls into the same predetermined state, then the likelihood that it has time to complete at least one full revolution becomes low. In other words, some states of the generator 55 will be used less frequently than others, and then the properties of the “canonical” pseudo-random sequence of bits noted earlier (when describing the generator 1, see FIG. 1) will be lost to some extent, which is undesirable. The presence of several fixed installation points, evenly distributed over the diagram 112, evens out the probabilities of using all possible states of the generator 55.

As shown in diagrams 121 and 122 (Fig. 8), one of the codes causing the generator 55 to be forced to a fixed state is the SDATA = CODE ₁ = 62 ₁₆ = 01100010 ₂ code. This code is present in register 74 in the time interval T8-T9, and, as already noted, the decoder 75 responds to it by preparing register 58 to receive the parallel LOAD ₁ code from inputs 79. This code in this example is OE ₁₆ = 01110 ₂ and corresponds to state S11 of the generator 55 (see tab. 111 in Fig. 7, a). Thus, at time T9, the chain of successive transitions ... S16, S17, ..., S23, S24 is broken, and instead of switching to the next state S25, the generator 55 “jumps” to the state S11. After this, a new chain of successive transitions is formed: S11, S12, ..., S18, S19, ... - until the next situation arises in which this circuit breaks, and then the next chain is formed with one of the initial states S3, S11, S19 or S27 etc.

The scrambled DLINE * data received from line 51 synchronizes the generator 63 with phase-locked loop (Fig. 4), as a result, the signal CLK * is generated at its output, and its inverse value is generated at the output of the inverter 89 (diagrams 125, 133, 126 in FIG. 9). The SDIN signal (diagram 127) at the output of trigger 87 repeats the DLINE * signal with a delay of half the clock period, while the SDIN signal, as already noted, practically does not contain phase distortion (jitter). The scrambled SDIN data passes sequentially through the register 85. After filling it, the SDATA * data (diagram 128), up to the transmission delay, coincides with the SDATA data in the scrambler register 74 (diagram 121).

This follows from the fact that, firstly, the data source for both registers is common - the output of the Exclusive OR 56 element, and, secondly, nothing prevents the simultaneous (up to a transmission delay) filling of both registers with the same data. Since the decoders 75 and 86 are identical, and the data at their inputs are the same, the signals at the outputs of these decoders are also the same (up to a transmission delay). From this it follows that the previously considered process of setting the generator 55 to a certain state also proceeds in descrambler 62, namely, in the time interval T8-T9 (Fig. 9), the signal J * = 1 is formed at the input P / S * of register 64 (diagram 129), at time T9, a parallel code OE ₁₆ corresponding to state S11 is received in register 64.

Regardless of the history of the generator of the pseudo-random bit sequence of the descrambler 62, starting from the moment T9 (Fig. 9), this generator is synchronized with the generator 55 of the scrambler 54 in the sense that the bit sequences generated by both generators coincide. Uncertain states and signals in the initial period when there was no code synchronization between the generators are marked with “X” in the diagrams 130, 131, 132, and 134.

Starting from moment T9, the scrambling RND (diagram 119 in Fig. 8) and the descrambling RND * (diagram 131 in Fig. 9) the bit sequences coincide, therefore, the DIN signal (diagram 132) of the descrambled data coincides with the DATA signal (diagram 118) at the input 61 scrambler accurate to transmission delay. The output DATA * signal (diagram 134) of the data, "cleared" of possible multiple switching at the boundaries between bit intervals, is output to the descrambler 91 and is accompanied by a signal CLK *. Thus, the input signals DATA and CLK are converted into coincident (up to a transmission delay) output signals DATA * and CLK *.

The frequency of repetition of the moments of synchronous installation of registers 58 and 64 in the same state (moments of code synchronization) depends on the data transfer rate, as well as on the bit depth and the number K of codes CODE ₁ , CODE ₂ , ..., CODE _k recognized by the decoders 75 and 86.

With K = 1 and a register width of 74 (85) equal to 8, in the scrambled data stream, on average, in each 256-bit chain, one sought code will be found, equal to CODE ₁ . With a data transfer rate of 10 Mbit / s, the average repetition rate of the synchronization moments is 10,000,000 / 256 = 39,062.5 Hz. At K = 4, the frequency of the synchronization moments increases four times and amounts to 156250 Hz.

To reduce the probability of false recognition of CODE ₁ , CODE ₂ , ..., CODE _k codes by the descrambler decoder 86, due to the receipt of 85 error bits from the communication line into the register, the bit capacity of this register (as well as register 74) can be increased, for example, to 20 bits .

Below is the operation of the proposed device as a whole.

As already noted, the device synchronously receives data from two input channels, multiplexes them, scrambles them, and transfers them over the communication line. On the remote side, data is received from the line, the clock signal is extracted, the data is descrambled and demultiplexed, after which they enter the corresponding output channels. The task is to ensure the coordinated operation of data transmission and reception units. When solving it, “stochastic” synchronization was used, which does not require the introduction of service information into the data stream.

With this synchronization, random events associated with the "spontaneous" occurrence of some specified codes in the stream of scrambled data are simultaneously recorded at the receiving and transmitting sides. These points, if necessary, are used to correct the state of the overall system synchronization device. The foregoing is illustrated by the options considered below for the device to function under different conditions, depending on the history and on the moments of detection of the mentioned random events.

When the device is operating, six code situations are listed in Table 1.

Table 1. Possible code situations when transferring data through the device The presence of the correction impulse J and the reaction to it from the side of the data transmission unit 52 The state of the data receiving unit 53 Code situation number Previously Installed Sync Data at the outputs RxD1 and RxD2 of the device Impulse J correction is absent (figure 10) Right The data is correct, the rate of delivery is constant. The correction pulse J * is absent (Fig. 13) 1 Wrong, cannot be restored The data is incorrect. Impulse J * 2 no correction (Fig. 14) The correction pulse J is generated by the synchronization bit from channel 2. The pulse J is ignored (Fig. 10.11) Right The data is correct, the rate of delivery is constant. The correction pulse J * is ignored (Figs. 13, 15) 3 Wrong, then restored by his pulse J * The data is initially incorrect. They become correct and are issued at a constant pace after receiving the correction impulse J * (Figs. 14, 16) 4 The correction pulse J is generated by the synchronization bit from channel 1. The next bit from channel 1 is duplicated (Fig. 10,12) Right The data is correct, the rate of their output is slowed down once by one clock cycle in connection with the receipt of the correction impulse J * (Figs. 13, 17) 5 Wrong, then restored by his pulse J * The data is initially incorrect. They become correct and are issued at a constant pace after receiving the correction impulse J * (Figs. 14, 18) 6

Code situation No. 1 (figures 10, 13)

In this situation, in the history, the correct synchronization is established between the transmission unit 52 and the data receiving unit 53. The data multiplexing unit 69 periodically requests data of the first and second channels and multiplexes the received bits in response, after which the scrambled DLINE data is output to line 51, as shown in diagrams 135-147. 10 and the subsequent drawings, the numbers 1 and 2 indicate the bits belonging to the first and second channels. The numbering of time points in diagrams describing the operation of data transmission unit 54 (FIG. 10-FIG. 12) is not related to the numbering of time points in diagrams describing the operation of data reception unit 53 (FIG. 13-FIG. 18). (Recall that the delay in transmitting signals on line 51 is not known in advance, so the time frames in blocks 54 and 53 are different.)

The descrambler 62 receives the scrambled data and restores them (see diagrams 174-186 in FIG. 13). Block 80 distributes the multiplexed DATA * data between the first and second channels (see diagrams 187-192 in FIG. 13).

Code situation No. 2 (figure 10, 14)

In this situation, as in the previous one, the data multiplexing unit 69 periodically requests the data of the first and second channels and multiplexes the received bits in response, after which the scrambled DLINE data is output to line 51 (see diagrams 135-147 in Fig. 10). The data receiving unit 53 is not synchronized with the transmission unit. This, in turn, means that at least one of the blocks 62 or 80 is not working properly.

If only the descrambler does not work correctly (there is no code synchronization with the scrambler), then the DATA * data and, therefore, the RxD1 and RxD2 signals are incorrect regardless of whether they are distributed correctly or incorrectly between the output channels. It was previously shown that the synchronization of the descrambler with the scrambler is established every time the pulses J and J * are formed. With this in mind, the operation of the scrambler-descrambler system is not further considered.

If only the data demultiplexing unit 80 does not work correctly, then the correct DATA * data is not correctly distributed on the output channels, namely, the RxD1 data is output to the second channel, and the RxD2 data to the first (see Fig. 14, diagrams 193-211). This is due to the fact that the frequency divider on the trigger 103 (Fig.6) is operating in the wrong phase, but there is no pulse J * that could correct the phase.

Code situation No. 3 (figures 10, 11, 13, 15)

In the background, correct synchronization is achieved; the operation of the device corresponds to the time diagrams shown in FIGS. 10, 13. As shown in FIG. 11, during the transmission of previously unknown data, it happened that a DATA data bit was generated in the T20-T21 clock, which subsequently generates the formation of pulses J and J *. This bit is marked with a dot in diagram 159 and is referred to as the synchronization bit for brevity. It should be remembered that this bit is not overhead — it belongs to the stream of user or other “useful” data, in this case transmitted over the second channel.

The synchronization bit in the same clock cycle (T20-T21, FIG. 11) is scrambled by the exclusive OR element 56, and in the next clock cycle (T21-T22) it is loaded into the leftmost bit of the shift register 74, while the remaining bits are moved one position to the right. Obtained in tact T21-T22, the SDATA code is analyzed by the decoder 75, as a result, the signal J is generated at its output. A RESET pulse is generated from this signal, which is fed to the zero setting input of trigger 98. However, this trigger is already in the zero state, therefore, the RESET pulse is not has an effect on him. In fact, this means that impulse J in block 69 is ignored.

Similar processes occur in the block 53 receiving data (see Fig.15). The synchronization bit belonging to the second channel causes the formation of a RESET * pulse, which also does not affect the trigger 103, since this trigger works in the correct phase (see diagrams 212-230). Thus, in this situation, the impulse J * in block 80 is ignored.

Code situation No. 4 (figures 10, 11, 14, 16)

In the background, synchronization is incorrect; the operation of the device corresponds to the time diagrams shown in FIGS. 10, 14. As follows from the diagrams 148-160 shown in FIG. 11, the synchronization bit received on the second channel does not violate the rhythm of the data transmission unit. The same bit goes to the data receiving unit 53 and causes the formation of a RESET * pulse, which corrects (changes by 180 degrees) the phase of the signal ST * at the output of the trigger 103 (see diagrams 231-249 in Fig. 16), as a result, the correct synchronization is restored . From the moment T21 ', the output becomes correct.

Code situation No. 5 (figures 10, 12, 13, 17)

In the background, synchronization is correct; the operation of the device corresponds to the timing diagrams shown in FIGS. 10, 13. In clock cycle T19-T20 (FIG. 12), a synchronization bit belonging to the first channel is detected in the DATA data stream (marked with a dot in diagram 172). In the next clock cycle (T20-T21), this bit after scrambling is written to register 74, which generates a pulse J. At the beginning of the second half of the clock cycle, a RESET pulse is generated (chart 165), which sets the trigger 98 to zero, which at that moment had just settled down per unit. As a result, a short-term positive impulse is formed at the trigger output (see diagram 166). This pulse is eliminated by overwriting the signal from the trigger 98 to the trigger 100. The impact of the RESET pulse on the trigger 98 leads to the violation of the periodicity of the signals TxC1 and TxC2 (diagrams 167, 169). In this case, the bit from the first channel following the synchronization bit is duplicated when it is issued to the line (diagram 173). The duplicated bit in the diagrams is indicated by the 1 * symbol.

Similar processes occur in block 53 receiving data (see Fig.17). The rate of data output is once slowed down by one cycle in connection with the receipt of the correction impulse J *. Data is transmitted correctly.

Code situation No. 6 (figures 10, 12, 14, 18)

In the background, synchronization is incorrect; the operation of the device corresponds to the timing diagrams shown in FIGS. 10, 14. In clock cycle T19-T20 (FIG. 12), a synchronization bit belonging to the first channel is detected in the DATA data stream (marked with a dot in diagram 172). In the next clock cycle (T20-T21), this bit after scrambling is written to register 74, which generates a pulse J. As a result, as in situation No. 5, the bit from the first channel following the synchronization bit is duplicated when it is sent to the line (diagram 173).

In a block 53 for receiving data, a RESET * pulse is generated, which does not affect the incorrect phase of the CT * signal (see diagrams 269-287 in Fig. 18). But the impact in this case is not required, since there is an "extra" 1 * bit in the stream of received data, which violates the order of the alternation of channels, so that previously the wrong phase of the CT * signal becomes correct. Starting from the moment T19 ', the correct data arrives at the device outputs.

Thus, in any possible code situations, upon detection of the conditions for the formation of correcting pulses J and J *, the restoration of correct synchronization is guaranteed if it was broken. If the initial synchronization was not broken, then the pulses J and J * only confirm it.

The use of the proposed device can increase the data transfer rate due to two factors. The first factor is the exclusion from the data stream of a relatively large amount of overhead information designed to synchronize the operation of the descrambler with the scrambler, as well as the exclusion from the communication protocols of the corresponding software. The second factor is the exclusion from the data stream of overhead information indicating that the data belongs to the first or second channel.

Sources of information

1. US patent No. 5.530.959 (Fig. 1).

2. US patent No. 5.530.959 (Fig.5) (prototype).

Claims (3)

1. A device for transmitting data, comprising a data transmission unit and a data receiving unit connected to opposite sides of a communication line, a data transmission unit comprising a scrambler comprising a pseudo-random sequence of bits, a first exclusive OR element and a first amplifier, a pseudo-random sequence of bits contains a first shift register and the second exclusive-OR element, the inputs of which are connected to the outputs of the first shift register, and the output to the first input of the first exclusive-OR element and to the serial data input of the first shift register, the synchronization input of which is the scrambler synchronization input, the second input of the first exclusive-OR element is the scrambler data input, the output of the first amplifier is connected to the communication line, the data reception unit contains a descrambler containing a phase-locked oscillator, the second shift register, the third and fourth elements Exclusive OR and the second amplifier, the input of which is connected to the communication line, and the output to the input of the generator with phase-locked loop frequency, the output of which is the descrambler synchronization output, the outputs of the second shift register are connected to the inputs of the third exclusive-OR element, the output of which is connected to the first input of the fourth exclusive-OR element, characterized in that the data transmission unit further comprises a data multiplexing unit, a first data input and the first synchronization output of which is the data input and the first synchronization output of the first channel, the second data input and the second synchronization output of the multiplexer unit The data are the data input and the first synchronization output of the second channel, the scrambler further comprises a third shift register, a first decoder, a first trigger and a first inverter, the output of which is connected to the synchronization input of the first trigger, the input of the first inverter is connected to the synchronization inputs of the first and third shift registers, and also with the third synchronization output of the data multiplexing unit, the control input of the first shift register is connected to the output of the first decoder and to the input of the block correction for data multiplexing, the output of the multiplexed data of which is connected to the data input of the scrambler, the input of serial data of the third shift register is connected to the output of the first XOR element and to the data input of the first trigger, the output of which is connected to the input of the first amplifier, the remaining outputs of the first decoder are connected to the inputs of parallel data of the first shift register, the inputs of the first decoder are connected to the outputs of the third shift register, the data receiving unit further comprises a demultiplexing data lock, the first data output and the first synchronization output of which are the data output and the second synchronization output of the first channel, the second data output and the second synchronization output of the data demultiplexing unit are the data output and the second synchronization output of the second channel, the descrambler further comprises a fourth shift register, the second a decoder, second and third triggers and a second inverter, the output of which is connected to the synchronization input of the second trigger and to the synchronization inputs w In the fourth and fourth shift registers, the control input of the second shift register is connected to the output of the second decoder and to the correction input of the data demultiplexing unit, the data input of which is connected to the output of the third trigger, and the synchronization input is connected to the descrambler synchronization output, the input of the fourth shift register data is connected to the second input of the fourth XOR element and with the output of the second trigger, the data input of which is connected to the output of the second amplifier, parallel data inputs the second shift register is connected to the remaining outputs of the second decoder, the inputs of which are connected to the outputs of the fourth shift register, the input of the serial data of the second shift register is connected to the first input of the fourth exclusive-OR element, the output of which is connected to the data input of the third trigger, the synchronization input of which is connected to the synchronization output descrambler and with the input of the second inverter. 2. The device for transmitting data according to claim 1, characterized in that the data multiplexing unit comprises a pulse generator, an inverter, an AND element, the first and fourth triggers and a multiplexer, the data inputs of which are the first and second data inputs of the multiplexing unit, and the control input is connected with the zero output of the fourth trigger and is the second synchronization output of the multiplexing unit, the first synchronization output of the multiplexing unit is connected to the output of the fourth trigger, the synchronization input of which is connected nen with the synchronization input of the third trigger, with the output of the pulse generator and with the input of the inverter and is the third synchronization output of the multiplexing unit, the output of the third trigger is the output of the multiplexed data of the multiplexing unit, the data input of the first trigger is connected to the first input of the And element and is the correction input of the multiplexing unit, the second input of the And element is connected to the output of the first trigger, the synchronization input of which is connected to the synchronization input of the second trigger and to the torus, the zero output of the second flip-flop is connected with its data input, and its zero-setting input - with the output of the AND, the multiplexer output is connected to the input of the third data latch, the second latch output is connected to the trigger input of the fourth data. 3. The data transmission device according to claim 1, characterized in that the data demultiplexing unit comprises first to seventh triggers, an inverter and an I element, the inverter input is connected to the synchronization inputs of the third and sixth triggers and is a synchronization input of the demultiplexing unit, the inverter output is connected to the synchronization inputs of the first, second and seventh triggers, the data inputs of the fourth and fifth triggers are connected and are the data input of the demultiplexing unit, the data input of the first trigger is the correction input and the demultiplexing unit, the outputs of the fourth and fifth triggers are the first and second outputs of the data of the demultiplexing unit, respectively, the synchronization input of the fourth trigger is connected to the zero output of the seventh trigger and is the first synchronization output of the demultiplexing unit, the synchronization input of the fifth trigger is connected to the output of the seventh trigger and is the second synchronization of the demultiplexing unit, the zero output of the first trigger is connected to the first input of the And element, the second input of which the second is connected to the output of the third trigger, the data input of which is connected to the output of the first trigger, the data input of the seventh trigger is connected to the output of the sixth trigger, the data input of which is connected to the output of the second trigger, the data input of which is connected to its zero output, and the zero-setting input is connected to output element I.

Images