JPH037440A - Multiplexing transmission system - Google Patents

Abstract

PURPOSE:To prevent the deviation of synchronization between signals by multiplexing a horizontal synchronizing signal, a vertical synchronizing signal and a display signal. CONSTITUTION:A multiplex section 5 multiplexes a horizontal synchronizing signal HSC, a vertical synchronizing signal VSC and a display signal DIP and a reproduction signal output section 11 demultiplexes and reproduces the multiplex signal based on a multiplex signal VHSI, a horizontal synchronization enable signal HSEN and a vertical synchronization enable signal VSEN. Thus, an optical interface is constituted of a couple of optical module and optical fiber, since the horizontal synchronizing signal, the vertical synchronizing signal and the display signal are sent and received by one and the same optical module (having same switching characteristic), the deviation of synchronization among the signals is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a monochrome CRT display interface, and more particularly to a multiplexing device and a reproducing device for vertical synchronizing signals, horizontal synchronizing signals, and display signals using optical modules.

[Prior art and problems to be solved by the invention] The conventional monochrome CRT display interface is
In the case of the L interface, the CRT display control section and the CRT display body may be installed at a distance of more than 10 meters or more. In this case, even if an element with high drive ability is provided in the CRT display control section, the distortion of the electrical waveform is large and display defects such as dots and the like may occur.

Further, when the TTL interface is changed to an optical interface using an optical module, it is necessary to use OE elements having the same switching characteristics for the horizontal synchronization signal, vertical synchronization signal, and display signal to prevent synchronization deviation. In this case, the horizontal synchronization signal and vertical synchronization signal are slow, but the single display signal is fast, so it is necessary to use OE elements with high-speed switching characteristics for each signal transmission, which is 10% more expensive. .

[Means for Solving the Problems] A monochrome CRT display interface according to the present invention processes a horizontal synchronization signal on the transmitting side to generate a first signal representing a level change of the horizontal synchronization signal and a horizontal synchronization enable signal. a first processing circuit that processes the vertical synchronization signal and outputs a second signal representing a level change of the vertical synchronization signal and a vertical synchronization enable signal;
a processing circuit; and the first processing circuit. a conversion circuit that performs Manchester conversion on the second signal and outputs a synchronization flag signal;

a circuit that multiplexes the horizontal synchronization signal, horizontal synchronization enable signal, vertical synchronization signal, vertical synchronization enable signal, synchronization flag signal, and display signal and outputs a multiplexed signal;
It has an optical module that converts the multiplexed signal into an optical signal and transmits it, and on the receiving side, it has an optical module that converts the transmitted optical signal into a multiplexed electrical signal and starts from the multiplexed electrical signal. means for detecting a bit, means for detecting a synchronization flag from a multiplexed electrical signal based on the detected start bit, means for performing Manchester encoding based on the detected synchronization flag, and said Manchester encoding. means for reproducing a horizontal synchronization enable signal, a vertical synchronization enable signal 1 display enable signal from a multiplexed electrical signal based on the output of the reproducing means, and a horizontal synchronization signal and a vertical synchronization signal from the multiplexed electrical signal based on the output of the reproducing means. and means for reproducing the display signal.

[Embodiment] FIG. 1 is a functional block diagram of the transmitting side (multiplexing side) of the present invention, and FIG. 2 is a functional block diagram of the receiving side (multiple reproduction side).

Multiplexing of the horizontal synchronizing signal H3C and the vertical synchronizing signal VSC1 display signal DIP will be explained with reference to FIGS. 1, 4, 5, and 6 to 10.

When the enable signal ENA becomes active, the horizontal synchronization counter 1 starts counting the width of the high level period (active period) and low level period (inactive period) of the horizontal synchronization signal HSC using the basic clock signal DTC.

As shown in FIG. 6, the width of the high level period is:

A count value is output as the high period width HWI.

As for the width of the low level period, a count value is output as a low period width HW2. High period width HWI and low period width HW
2, after the count ends, the count value is held and output.

The high period width HWI and the low period width HW2 are input to the horizontal synchronization signal control section 2.

As shown in FIG. 7, the high period width HWI and the low period width H
The horizontal synchronization enable signal H8EN becomes high after (HW2)-8 clocks of the basic clock signal DTC have elapsed from the trailing edge of the primary horizontal synchronization signal H3C after the count of W2 is completed. , the high period is repeatedly outputted with a width of (HW1)+16 clocks of the basic clock DTC, and the low period is repeatedly outputted with a width of (HW2)-16 clocks.

As shown in FIG. 8, the vertical synchronization signal vSC input to the vertical synchronization counter 3 also counts the width of the high level period and the low level period using the horizontal synchronization signal H8C as a clock. The width of the high level period is the high period width VWI,
The width of the low level period is output from the vertical synchronization counter 3 as a low period width VW2. Based on the high period width VWI and the low period width VW2, the vertical synchronization signal control unit 4 generates a vertical synchronization enable signal VSEN.

As shown in FIG. 9, the high period width vwi and the low period width V
The vertical synchronization enable signal VSEN becomes high after (vW2)-1 width of the horizontal synchronization signal HSC has elapsed from the trailing edge of the primary vertical synchronization signal vSC after the count of W2 is completed. From now on, the vertical synchronization enable signal VS EN is the horizontal synchronization signal H5C.
With one cycle as the basic width, it repeatedly outputs high for the width of (VWI) and low for the width of (VW2). Furthermore, the synchronization flag signal 5YFL is output during the high period of the vertical synchronization enable signal VSEN.

The data structure of the synchronization flag signal 5YFL is shown in FIG. This signal has a 56-bit configuration, but each bit is Manchester converted (IB2B converted).
It is output from the Manchester conversion unit 6 (FIG. 1). 7
E is a synchronization flag. The high period width HW1 of the horizontal synchronization signal H3C is 5 btt, and the low period width HW2 is 16 bi.
Each is Manchester-transformed at t and output. Also.

The high period width vW1 of the vertical synchronization signal vSC is 8 bits.

The row period width VW2 is Manchester-transformed by 16b[t and output. That is, as a count value, the high period width HWI and VWI are up to FF.

Low period width HW2. VW2 can express up to FFFF. Note that the width of 1 bit after Manchester conversion is the width of 5 clocks of the basic clock signal DTC. (See FIG. 5) FIG. 5 shows the actual output timing of the synchronization flag 5YFL. Additional bit for synchronization (basic clock signal DTC
A synchronization flag 5YFL is output after adding a 5-clock width low).

FIG. 10 shows the output of the multiplexed signal VHS I.

During the period when the horizontal synchronization enable signal H8EN is high, the horizontal synchronization signal H3C is output, and during the period when the horizontal synchronization enable signal H8EN is low, the display signal DIP is output. Further, when the vertical synchronization enable signal VSEN becomes high, the synchronization flag signal 5YFL is output. The multiplexed signal VHSI is output from the multiplexer 5.

Next, multiplexed reproduction will be explained with reference to FIG. 2 and FIGS. 11 to 14.

The multiplexed signal VH3I is input to the start bit detection section 7, and when the additional bit for synchronization (see FIG. 5) is detected, the reception start signal 5TEN is activated.

When the synchronization flag detection unit 8 detects the synchronization flag (Manchester-converted 7E) from the synchronization signal 5VHSI synchronized by the basic clock RDTC while the reception start signal 5TEN is active, it activates the flag detection signal FLEN. Make it. When the flag detection signal FLEN becomes active, the data part Manchester encoder 9 sequentially Manchester encodes the next data part using the synchronization signal 5VHSI.

High period width HWI of the horizontal synchronization signal counted on the transmitting side
is output as a high period width reception signal RHWI, and a low period width HW2 is outputted as a low period width reception signal RHW2 from the data section Manchester encoder 9, respectively. Also, if the high period width VWI of the vertical synchronization signal counted on the transmitting side is the high period width reception signal RVW1. The row period width VW2 is output as the row period width reception signal RVW2.

Horizontal synchronization enable signal HS EN is synchronization flag 5Y
After receiving the FL, after a width of (RHW2)-8 of the basic clock RDTC has elapsed from the falling edge of the primary multiplexed signal VH3I, it becomes high, and thereafter.

High period by (RHWI)+16 width, (RHW2)-1
The state of the low period is repeatedly output for 6 widths.

Vertical synchronization enable signal VS EN is synchronization flag 5
After receiving YFL, it becomes high from the rising edge of the primary multiplexed signal VH3I, and becomes low when another rising edge is detected the number of times (RVWI). The horizontal synchronization enable signal H3EN and the vertical synchronization enable signal VSEN are output from the enable signal control section 10.

The reproduction signal output section 11 outputs a multiplexed signal VH3I, a horizontal synchronization enable signal H8EN, and a vertical synchronization enable signal VSE.
The multiplexed signal is separated and reproduced based on each of the N signals.

The reproduced horizontal synchronization signal RH9C is the output of the AND of the multiplexed signal VH3l and the horizontal synchronization enable signal H3EN. The reproduced vertical synchronization signal RVSC is the vertical synchronization enable signal VSEN output as is. The reproduction display signal RDIP is.

The period when the horizontal synchronization enable signal H6EN is low is 1.
The multiplexed signal VH3I is output while the display enable signal DIEN is high.

FIG. 3 shows an example of the configuration of the present invention. The transmitter 12 is.

It has the same functions as the block diagram shown in FIG. The receiving section 15 has the same functions as the block diagram shown in FIG. The multiplexed signal VH3I is EO converted by the optical module 13 and propagated within the optical fiber. The optical module 14 performs OE conversion on the received multiplexed signal.

[Effects of the Invention] As explained above, the present invention has a monochrome CRT display interface that is configured with three pairs of optical modules and optical fibers by multiplexing horizontal synchronization signals, vertical synchronization signals, and display signals. The optical interface can be composed of a pair of optical modules and an optical fiber.

In this case, since the horizontal synchronization signal, vertical synchronization signal, and display signal are transmitted and received by the same optical module (same switching characteristics), no synchronization deviation occurs between the signals. Also, compared to a configuration without multiplexing, it is approximately 1/3
The effect is that an optical interface can be realized at a price of .

[Brief explanation of drawings]

FIG. 1 is a block diagram of the transmitting side device of the present invention, FIG. 2 is a block diagram of the receiving side device of the present invention, and FIG. 3 is a block diagram of the transmitting side device of the present invention.
A schematic configuration diagram when the transmitting device and the receiving device shown in the figure are connected by an optical transmission line, Figure 4 is a diagram showing a configuration example of the synchronization flag signal used in the present invention, and Figure 5 A diagram showing signal waveforms for explaining the output timing of a synchronization flag signal. FIGS. 6 to 10 are signal waveform diagrams for explaining the operation of each part in the transmitting device shown in FIG. 1
1 to 14 are signal waveform diagrams for explaining the operation of each part in the receiving device shown in FIG. 2, respectively. In the figure, VSC is a vertical synchronization signal, HSC is a horizontal synchronization signal,
ENA is an enable signal, DTC is a basic clock signal,
DIP is a display signal, VH3I is a multiplex signal, and H3EN is a horizontal synchronization enable signal. VSEN is a vertical synchronization enable signal, and 5YFL is a synchronization flag signal.

Claims (1)

[Claims] 1) In a monochrome CRT display interface, on the transmission side, a first processing circuit that processes a horizontal synchronization signal and outputs a first signal representing a level change of the horizontal synchronization signal and a horizontal synchronization enable signal; a second processing circuit that processes the synchronization signal and outputs a second signal representing a level change of the vertical synchronization signal and a vertical synchronization enable signal; and a synchronization flag that performs Manchester conversion on the first and second signals. a conversion circuit that outputs a signal, the horizontal synchronization signal, the horizontal synchronization enable signal, the vertical synchronization signal,
It has a circuit that multiplexes a vertical synchronization enable signal, a synchronization flag signal, and a display signal and outputs a multiplexed signal, and an optical module that converts the multiplexed signal into an optical signal and transmits it, and on the receiving side, An optical module that converts a transmitted optical signal into a multiplexed electrical signal, a means for detecting a start bit from the multiplexed electrical signal, and a synchronization flag from the multiplexed electrical signal based on the detected start bit. means for detecting, and means for performing Manchester encoding based on the detected synchronization flag;
means for reproducing a horizontal synchronization enable signal, a vertical synchronization enable signal, and a display enable signal from the multiplexed electrical signal based on the output of the Manchester encoding means;
A multiplex transmission system comprising: means for reproducing a horizontal synchronizing signal, a vertical synchronizing signal, and a display signal from a multiplexed electrical signal based on the output of the reproducing means.