JPS59230343A - Parallel data transmitting method - Google Patents

Abstract

PURPOSE:To suppress surely generation of consecutive 0s by adding 1 bit to an input signal and using this bit as a complementary code and a frame synchronism bit of a preceding bit to simplify a timing circuit. CONSTITUTION:A parallel data input (a) is subjected to scrambling with a PN series being an output of a PN (pseudo random) pattern generating section 22 at an exclusive OR circuit 22 and converted into a random code. The least significant bit among N parallel outputs (c), and a frame synchronizing signal (f) are inputted to an exclusive OR circuit 23, where a code of the same sign is formed when the frame synchronizing bit is detected and an inverted code is formed when not, and signals g,c are outputted as a serial signal by a parallel-serial converting section 24. Thus a timing control circuit 25 has only to form a clock (e) for serial data being an integral number of multiple of (N+1) times the word clock (d) and the frame synchronizing signal (f) and further, since a 1-bit complementary code is inserted, the number of consecutive 0s is specified surely.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention converts data that can be handled in word units, such as digitized analog signals such as images and audio, or parallel data, into serial data, and transmits the converted data at the receiving end. The present invention relates to a parallel data transmission method used in digital transmission in which a clock is extracted from the data string and data is reproduced.

Conventional configuration and its problems When transmitting parallel data serially, a synchronization bit is inserted to indicate the separation between two pages of data, and a clock can be extracted at the receiving end no matter what data string is received. 0
``It becomes necessary to suppress continuity.

FIG. 1 shows a conventional parallel data transmission circuit.

The configuration of this conventional example will be explained below with reference to FIG. 1. In FIG. 1, numeral 11 denotes a parallel-to-serial converter that converts N parallel data inputs, indicated by ■, into a serial data string, and its output is indicated by ■. 12 is a PN pattern generation section that generates a PN (pseudorandom) pattern, and its output signal is denoted by . 13 is an exclusive OR circuit for scrambling the signal f with the signal ■; 14 is a speed conversion section; 15 is a synchronous bit insertion section for inserting a synchronous bit into a transmission data string;
Reference numeral 6 denotes a timing control section that generates timing signals for operating these sections.

Next, the operation of the first half conventional example will be explained. It is assumed that the parallel data input signal {circle around (2)} is input in N-bit parallel form and has a transmission speed of Ao word tiles. Timing control section 16
A clock (2) of NXAoCHz] is created, and the parallel/serial converter 11 is operated for three pages using this clock (2), thereby obtaining a serially converted signal (3). At the same time, the PN pattern generating section 12 is operated with the clock ■ to obtain a PN pattern signal ■ having the same speed as the signal ■. The signals and ■ are exclusive ORed in the exclusive OR circuit 13, and the input signal is scrambled to stochastically suppress the occurrence of continuous "O".The speed converter 14 is synchronized with the input data string. It works to slightly increase the speed on the output side in order to add a bit for the M word.Now, if one bit of synchronization bit is added to the M word, it will be necessary on the read side of the speed converter 14, and the speed of lock 2 will be: Therefore, it is necessary to create such a lock by the timing control section 16.The synchronization bit insertion section 15 inserts a synchronization bit into the speed-converted data string and creates a frame structure for transmission.

The timing signal (2) for inserting the synchronization bit is generated by the timing control section 16, and at the same time, the PN pattern generation section 12 is brought into an initial state using this signal (2), thereby synchronizing the PN pattern series and the frame. However, in the conventional example described above, the parallel data transmission speed and the serial data transmission speed are generally not an integral multiple due to synchronization bit insertion, and the disadvantage is that the timing generation circuit for controlling each part becomes complicated. In addition, since the suppression of "ol+ continuity is performed only by scrambling," there is a problem that there remains a possibility that "all continuity" will occur.

OBJECTS OF THE INVENTION The present invention is intended to eliminate the drawbacks of the first half of the prior art, and aims to simplify the timing control circuit and reliably suppress the occurrence of consecutive "0"s.

Structure of the Invention In order to achieve the above object, the present invention adds a bit to one word (N bits) of an input signal, uses this bit as a concomitant code of the previous bit, and synchronizes the scrambling and descrambling by adding It is possible to detect 5 pages by violating the coding rule that a bit is a concomitant bit of the previous bit, and the transmission rate is (N+1) times the input word data rate, and the timing control circuit This has the effect of simplifying the process and at the same time ensuring that the number of consecutive "0" pits is kept below a certain level.

DESCRIPTION OF EMBODIMENTS The configuration of an embodiment of the present invention will be described below with reference to the drawings. In Figure 2, N parallel data human power ■ is N
Exclusive OR circuits 21 are inputted to the exclusive OR circuits 21. Further, the PN series generated by the PN pattern generating section 22 is parallelized and taken out as a signal ■, which is also input to the exclusive OR circuit 21. The output signal {circle around (2)} of the exclusive OR circuit 21 is input to the parallel input terminal of the parallel-to-serial converter 24 . The lowest bit of these N signals ■ is sent to another exclusive OR circuit 2.
3, and the frame synchronization bit signal generated by the timing control section 25 is input to the other input. This output signal ■ is also input to the (N+1)th bit of the parallel input terminal of the parallel-to-serial converter 24.

The timing controller 25 generates a serial data clock (N+1.) from the word clock (2) synchronized with the parallel data (2) and distributes it to the parallel/serial converter (24) and the PN pattern generator (22). The signal (2) is a signal converted into a serial signal by the parallel-to-serial converter 24, and this signal (2) becomes the signal that is transmitted as is. Figure 3 shows the structure of the serially converted data string (■), in which the bit added by 1 bit to 1 word (N bits) is a concomitant of the previous code, and the added bits for each M word are of the same sign. Use for frame synchronization.

Next, the operation of the above embodiment will be explained. In FIG. 2, the parallel data input (■) is in parallel with the PN series that is the output of the PN pattern generator 22 and the exclusive OR circuit 22.
The data is scrambled and the data string is randomized. The least significant bit of these N parallel outputs is
It is inputted to the frame synchronization signal (■) and the exclusive OR circuit 23, and when it is a frame synchronization bit, the same sign is generated, and when it is not, an inverted sign is generated. The (N+1) 7th page signals of the signals ■ and ■ are converted into serial signals as shown in FIG. 3 by the parallel-to-serial converter 24 and output.

In this embodiment, the timing control section 25 controls the word clock (N) synchronized with the parallel data input signal.
+1. It is sufficient to generate only the frame synchronization signal necessary to synchronize the serial data clock (2), which is an integral multiple of ) times the PN pattern generation section 22, and it can be realized with a simple configuration. Furthermore, regarding the suppression of consecutive 0's, not only is scrambling performed, but also a 1-bit complementary code is inserted into N bits, so there is an advantage that the +1011 consecutive number can be reliably defined.

Effects of the Invention The present invention has the above configuration, and according to the present invention, the following effects can be obtained.

(a) The clocks that operate each part are all integral multiples, and can be realized with a simple configuration.

(b) By inserting a 1-bit precode concomitant code into N bits, the number of consecutive "0"s can be reliably suppressed to a certain value or less.

(C) Frame synchronization does not require special additional bits because it can be detected by violation of the coding rule in (1) above.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a circuit implementing a conventional parallel data transmission method, FIG. 2 is a block diagram of a circuit implementing a parallel data transmission method according to an embodiment of the present invention, and FIG. 3 is a block diagram of a circuit implementing a parallel data transmission method according to an embodiment of the present invention. FIG. 3 is a diagram showing an example of a signal format. 21.23... Exclusive OR circuit, 22... PN pattern generation section, 24... Parallel-serial conversion section, 25... Timing control section. Name of agent: Patent attorney Toshio Nakao and one other person
Yo】Yu~ Pulse

Claims (1)

[Claims] One additional bit is provided in the parallel data, and this additional bit has a complementary code to the previous bit. When used as a frame synchronization bit at the same time, the additional bit is used with the same sign as the previous bit, and this parallel data is A parallel data transmission method characterized by converting and transmitting serial data.