JPS60150346A - Time division multiplex transmitter - Google Patents

Abstract

PURPOSE:To attain multiplexing and separation of signals with very simple constitution by adding one-bit of a mark pulse at fixing when time division multiplexing is executed to eliminate the need for a code conversion/decoding circuit for preventing consecutive zeros in a signal after multiplexing requiring high speed operation and use the added one-bit as a frame pulse representing the order of arrangement of multiplex. CONSTITUTION:An input signal applied to input terminals 20-23 is processed at each section and inputted to a multiplexer 16. Even if the signal supplied to the input terminals 20-23 is ''all mark'', since scrambling is applied by scramble circuits 11-14, a time slot where an output signal 38 goes always to ''1'' in the output signals 38 of the multiplexer 16 is caused only at the position at which a high level of an X3 terminal of the multiplexer 16 is outputted.

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention is directed to converting a 1' city report into a binary digital signal.
A device a1 that combines many signals on the main line b'N, that is, transmitting (in 1ii1, the number of signals is multiplexed and sent as one signal, ij L, receiving ij f+''
In f, the clock 1 which extracted the 1.4 shi 1, 1.
' The reproduction part is high by Gll, and the belief of the original plate →
1-1 to the understanding transmission device f. [Prior art] Binary digital with information embedded in one helix (r4"'7
Time division multiplexing and transmission are often used to carry large numbers of signals. Then, if you invest 1 time-sharing Shingetsu, Ukei. (The clock information present in the data number 1d is extracted and transmitted (the clock information presented in the data number 1d is reproduced. An example of the apparatus is shown for the case where the multiplicity is n = 4.The multiplex conversion circuit 1 converts the input No. 414 into two time-division tables and inserts a frame pulse indicating the order of arrangement. , 9';Don't vomit, 4B3T,
Chll, )'ST, 136ZS Light Sign 4''
With a conversion circuit! +') made L1 multi'+ii' IC
The T-note bow is converted into a ':x L /C-note-bow and supplied to the transmission ν153. The transmission line 3 is equipped with a transmitter, a repeater, and a receiver that are driven by this converted binary digital signal. In addition, transmitting fi-g4:, receiving (receiving) 11+ with electric light converter, photoelectric converter, etc.
'j may be formed. The inverse color changing circuit 4 returns the transmitted sign moon to the original multiplexed signal and supplies it to the dividing circuit 5. A splitting circuit 5 identifies the frame pulse and separates the blood-rich signal into a plurality of original input signals and outputs them. However, in the case of sending fr, the above-mentioned 111
j: H, input signal - 5. In order to prevent clock information from being lost even when - is consecutive, an inverse code conversion circuit is required on the transmitting side, 4 code conversion circuits on the transmitting side, and an inverse code conversion circuit on the receiving side. Since it must function at the multiplexed speed of the variable J cold circuit/inverse conversion circuit, it has the disadvantage of requiring high-speed operation proportional to the degree of multiplexing of the bit rate of the input signal. Figure 2 (r
l. An example of a frame configuration in this transmission device is shown below. In a counter circuit that inserts and detects a frame pulse F indicating an arrangement 11irl order of multi-11L signals, iJ: ,
Usually, to avoid confusing frame pulses and data,

[A frequency dividing circuit that is thicker than n is used, and the frame pulse detection circuit on the receiving side is also significantly reduced.
It had the disadvantage of having a +'In configuration. [Summary of the Invention] The present invention has the advantage that when time division multiplexing is performed, one pitted IJJ11 pulse of a mark (high level) is passed through when fixed. j4
2. By eliminating the need for a screw conversion/reverse code conversion circuit to prevent v consecutive uA, and still using this added 1 bit as a frame pulse 7 indicating the multiplexing array j (14 order). Very simple 11/I composition with many similarities〕1
1- conversion and minute 1'j+L become +IJ function II, lI
Min::u-N'i fby L'i device Lc ”4
．． - Provided. That is, the n,7-divider 1. of the present invention. il'transmission i-
Can 1.・No. 1, on the transmitting side, bit multiplexing is performed after inputting n numbers of inputs and eliminating all mark-like patterns by randomizing them using the j-type simple circuit bllS, but at that time 1 ] After fixedly adding 1 bit to the bit as a frame pattern, time-division multiplication] is converted into 1 bit and transmitted. By detecting the time slot that is always 1'' in the A1□ code, the (n+1) bit sequence is detected and decoded by a self-synchronous scrambling circuit. [Embodiment of the present invention] Now, one aspect of the present invention will be explained with reference to the drawings. In addition, common -QJ elements are given the same reference numerals throughout the drawings. Fig. 3 shows an embodiment of the present invention. A circuit diagram of the sending r4 side showing an example,
FIG. 4 is a waveform diagram of the 6B U output in this circuit diagram. Note that in this embodiment, the degree of multiplicity n =
4. In Fig. 3, 11 to 14 are input low-order/
! '1. A self-synchronous scrambling circuit randomizes the signal; 15 is a flip 70 retiming the scrambled input signal; 1eiJ is a theta selector multiplexer that multiplies this output; 17 is a multiplexer 1G; Transmission 1. ′,
Sending out to i,; circuit, 18 is low order! 1r clock's (n+1) I: r's i''1, j-th 11: Generate clock 'I=': i-th t; P clock, 1 raw circuit, i9+a and knock f ('n-1 -1:) Dividing the frequency by 3. -:): 7'C, 20~2
3 is the input box 1 where the human power (i) ``'l-) is input to (J, 24 is the clock 1 child where the human power (i) 'l-1 is supplied, 25 is the clock until 11.; the output is supplied. 26 to 38 indicate the operation signals of each part.In this practical example, the transmitting circuit 17 is described as a unipolar/bipolar conversion circuit, but '
The electric light conversion cycle may also be 5', ・j,. In FIG. 4, (Δ) to (rl) iJ, the operating waveforms indicating the output deviations 26 to 29 of the IE scramble circuits 11 to 14, ('.:) are the clocks i'l:li A signal waveform showing the input clock of the child 24, (F) an operation waveform showing data 30 to 33 retimed by the flip-flop 15, and 0) a signal waveform showing the clock 34 generated by the clock generation circuit 18-C3G'. , (lI) ~ (, ■) are divided by 1/i by the counter 19 and rLIC clock output 35 ~
37 indicating) k type, (l illusion (-1, 111 chi 1 of multiplexer 16, month' 3 II f indicating operation waveform, (f-)tr, L output M: f1i child 25'/
) J2k i(. This is a bipolar pulse train that shows the output. Now, at the input end "1; children 20 to 23, flu iL'F
h), - The human power signal is processed in each section and input to the multiplexer 16. The multiplexer 16 is supplied with the clock outputs 35 to 37 of the counter 19, and the addresses A, B, and C are expressed as (0,
0,0) outputs the XO separate terminal data 31 to the OUT terminal, and in the same way, when (1,0,0), X1ψ1
1. Data 32 of the 1st child, (1, 1, 0), Heil Bell of the X3 terminal, (0, 0, 1), x4☆; Output the data 30 of the M child in sequence, and continue this operation from now on. Get back on track. Therefore, 4 bits or more of 1g will not be continuous,
A mark rate of 115 is guaranteed. It's good, input ψ11A child 2
Even if the signal supplied to 0-23 is all marks,
Since scrambling is performed by the scrambling circuits 11 to 14, the time slot that is always 'A' in 38 in terms of the output of the multiplexer 16 is
The output level of the X3 terminal is only iu. Therefore, when receiving signals multiplexed in this way,
-1 side, it can be easily separated by detecting this time slot which is always °゛1''. Uke (u)
'ltl'l times 1. ! :S diagram and FIG. 6 are operation waveform diagrams of each F;i in this circuit diagram. In Figure 5,
41 is a bipolar-unipolar conversion circuit that converts the received bipolar signal into a unipolar signal; 42td is a 5-bit shift register that receives this conversion data as input; 43;
are retiming flip-flops, 44 to 47ij, self-synchronous scrambling circuit, 48.49V, l: inverter gate, 50 is an AND gate, 51 is a Nants gate, 52 is an output clock of the conversion circuit 41 via the AND gate 50. 53 is a flip-flop, 54 is a bipolar 1, inputs to which β and 114 are supplied, and 55 to 58 are ? Output terminal for taking out the converted signal, 59 is the output terminal of the counter, 1 child, 60
-69 indicate operation signals of each part. In addition, a dividing circuit for separating the signals received by the shift register 42 and the retiming flip-flop 43, antgelt 50, a nandt gate 51, a counter 52, and a 7-lip 70 tube 53.
A word synchronization circuit is constructed. In Figure 6, (
8) is the signal waveform of the reception signal No. 1 supplied to the input terminal 54, (I3) is the waveform representing the conversion data 60 of the bipolar/unipolar conversion circuit 41, and (C) is the signal waveform of this conversion circuit 4.
1 output clock 61, υ) l (E
) + (F) is the output of counter 52 F'3' QA
y Q o (59), the operation waveform showing QC (67), item) is the operation waveform showing the output signal 68 of the solid tube 70 tube 53, (10 is the operation waveform showing the output signal 69 of the Nant gate 51, (■ ) to 伽■) This is a waveform showing the output/signals 62 to 66 of the timing flip-flop 43. Now, the received signal supplied to the input terminal 54 is subjected to signal processing in each section and is input to the retiming 71 block flop 43. Normally, when word synchronization is established, the output 6G of the QE terminal of this flip-flop 43 is always °'i"
(high level), so inverter gate 4
The iH signal inverted at 9 passes through the Nant gate 51, and the output signal 69 is always at a high level. Therefore, the AND gate 50 opens and the counter 52 operates continuously, and the phase is such that the all mark pattern that arrives every 5 bits is always the output fg'66 of the QE appendix of the retiming flip-flop 43. . However, as shown in FIG. 6(B), normally, "1" should arrive next to the h time slot of the variable-1 data 60 of the all-1 spring circuit 41. If 0'' is received LJ, retiming flip-flop 4
Ql of 3.]☆; 1. The output signal 66 of the first child ends up being zero. At this time, in the time slot in which the output 1d 83 of the flip-flop 53 goes to the no-y level, the output tu''i 80 of the tuned gate 51 goes to the low level, closing the AND gate 50 for one clock. In this way, the gates 50, 51 and the counter 5
2. The synchronization circuit consisting of the flip-flop 53 limps the output of the QE terminal of the timing flip-flop -866 only once in 5 frequency divisions, and if it is not a mark (high level)/in this case, it is 1 clock. Since it operates to stop the counter, if you shift it up to 4 times, it will always detect the mark 111+ (L), which is fixedly finely divided in the pulse train of the received pulse train, and the timing of that time slot. Since the flip knob 430 operates so that the output of the QE terminal becomes
This means that the time-division multiplexed signals can be separated in the correct order on the transmitting side. Furthermore, since the input signal is scrambled on the transmitting side, there is always only one time slot that serves as a mark, and the synchronization circuit of the receiver 11.1 allows correct word cycles to be obtained. According to the operation waveform shown in FIG. 6 (El), after 2 bits of IIO# are added next to the h time slot, an example of a cross string in which a pulse 1'' is regularly inserted every 5 bits is shown. As shown in the figure, it can be seen that correct word synchronization is established with only one synchronization.Thus, the output signals 62 to 65 of the QA terminal to QD terminal of the retiming flip-flop 43 are self-synchronized. ] type scramble circuits 44 to 47
By supplying the input signal to the input signal, the randomized signal can be decoded on the transmitting side, and the same signal as the input signal can be outputted to the output pulls 1) 11 55 to 58 on the transmitting side. In this way, time division multiplex transmission can be performed using a multiplexed word arrangement in which one mark is fixedly added to every n bits. [Effects of the Invention] According to the present invention, when n signals are time-division multiplexed, marks are fixedly added, thereby reducing the mark rate 1/(
n+1), it is possible to eliminate the need for a complex code conversion/inverse conversion circuit that must operate at high speed, such as code conversion after multiplexing to suppress consecutive zeros. In addition, even if the input signal is all marks, it will be randomized by the scrambling circuit and then multi-headed, so in order to guarantee the mark rate, the (n+1)th bit mark should be used as the word synchronization code. Since frame pulses and the like are unstable, the counter can be a very simple one that divides the frequency by (n+1), and the word synchronization circuit on the receiving side can also be realized with a very simple configuration, so it can be used at very high speeds. Division multiplex transmission becomes possible. Furthermore, the synchronization detection time can be shifted up to n times, so
It is also possible to synchronize in a very short time. and,
When inserting a frame pulse once every several to several tens of words, a smooth ink circuit is required to fill in the gap that occurs when the frame pulse is removed on the receiving side, but this can also be made unnecessary. . Normally, this smooth ink circuit uses a variable oscillator such as ■CXO, but this requires complicated adjustment and is expensive; however, in the present invention, a counter is used, so no adjustment is required.
It has the advantage of being low cost and not changing over time.
It is also easy to integrate into an integrated circuit.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing a conventional transmission device, FIG. 2 is a frame configuration diagram in this transmission device, and FIGS. 3 and 4 are a circuit diagram and operation waveform diagram of a transmitting side showing an embodiment of the present invention. ,
FIG. 5 FIG. 6 is a circuit diagram and an operation waveform diagram on the receiving side showing an embodiment of the present invention. 1... Multiple conversion circuit, 2... Code conversion circuit, 3
・・・Transmission line, 4・φ・・Inverse conversion circuit, 5・・・・Separation circuit, 11~14.44~47＠龜・O Self-synchronous scrambling circuit 1t7t, 15, 43, 53...・Flip-flop circuit, 16...Multiplexer, 17
...e transmission circuit, 18φ...high-order group clock generation circuit, 19.52---e counter, 41 exposure◆e11 bipolar/unipolar conversion circuit, 42...shift register, 48~51- ・ ・ fist Gate. j (1・+! 1% "l'T...: Inside 1〒t dirt゛-11' Figure 1 Figure 2 1 234 F 12B4 + 23 Figure 3

Claims (1)

[Claims] In a device rt that transmits n digital binary signals with a phase interval JυJ by time division multiplexing, on the transmission side d, the n input signals are subjected to self-synchronous scrambling and pit multiplexed, and n-bit fixedly 11 for
A circuit is installed that encodes 9.1 so that 1 pit of 111 is added and outputs a transmission code, and the receiving side detects this added "'1" and performs word synchronization of (n+1) bits frj. and divide the received code into n pieces by 1jE, and
15, which is characterized by having a circuit that encodes a signal using self-synchronous scrambling and sends out an output signal.
11 multiplex transmission equipment.