JPH0382225A - Signal conversion circuit - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution and to make the scale of the circuit constitution by implementing the insertion of an auxiliary code and the auxiliary code rule violation processing simultaneously. CONSTITUTION:The circuit is provided with a parallel input serial output type shift register 1 having at least (n+1)-bit of input terminals and an exclusive OR circuit 4. Then an n-bit parallel signal is inputted to n-set of consecutive input terminals among input terminals of the shift register 1, and one-bit of the n-bit parallel signal is subject to logical processing with a sub signal AUX via an exclusive OR circuit 4, and the result is supplied to the remaining input terminals to control simultaneously the insertion of the auxiliary code Do and the insertion of the auxiliary code rule violation, then the (n+1)-bit serial signal SD subject to parallel/serial signal conversion is obtained simply. Thus, the signal conversion circuit with simple constitution and small circuit scale is obtained.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention converts an n-bit parallel signal such as a video signal into an (n+1)-bit serial signal in which the same sign is continuously suppressed and outputs the signal. This invention relates to a signal conversion circuit.

(Prior art) NRZ codes and AMI codes, which are widely used as transmission codes, have the risk of continuous "0" or "1m" over a long period of time, which can cause various problems in establishing code timing. Therefore, conventionally, “0” or “1”
For example, in baseband transmission, a continuous same code suppression coding method is used to prevent consecutive occurrences of the same code.

This type of same-code continuous suppression encoding method is realized, for example, by converting NRZ data into a CMI code. Specifically, for example, n-bit parallel data is converted into (n+1)-bit serial data, and the complementary code of a specific bit in the previous Kr2 n-bit parallel data is inserted into the extra bit generated by this. It is realized as follows. According to such a signal conversion circuit, for example, a low-speed sub-signal independent of the n-bit parallel data can be multiplexed by utilizing the code rule violation of the complementary code, without changing the transmission speed on the serial side. This brings about effects such as making it possible to transmit data.

Figure 3 shows the configuration of a signal conversion circuit that uses this method to multiplex and transmit sub-signals.The number of input terminals is one bit greater than the number of parallel data bits (5 bits in this example). It is composed of a parallel input serial output type shift register t having P0 to P, a timing generation circuit 2 that drives the shift register 1 at a predetermined transmission speed, and a complementary sign rule violation insertion circuit 3.

5-bit parallel data D. ~D4 are input in parallel to the input terminals P1~P of shift register i, respectively, and one bit (data D) of them is inputted to shift register l as complementary code Do whose sign is inverted via inverter la. Manual power is applied to terminal P0.

Therefore, the timing generation circuit 2 receives the parallel data D. - The clock CLKO corresponding to the period of D4 is set to the transmission speed of the serial data SD (parallel data D0 to D4).
The data is latched into the D-flip-flop 2a in synchronization with the shift clock CLKI corresponding to 6 times the period of
Generating OAD.

This load signal LOAD is applied to the shift register 1, which is then applied to the input terminal P described above. -P, data is taken in parallel. These data are serially read out from the shift register 1 as serial data SDI in response to the serial output shift clock CLKI.

As a result, parallel data D. - When D4 arrives, the fourth
As shown in the figure, the above parallel data D is synchronized with clocks CLKO and CLKI. -D4 and its complementary code Do are converted and output as a 6-bit serial data series.

Therefore, the complementary sign rule violation insertion circuit 3 receives the parallel data D. - manually inputting a sub-signal AUX independent of D4 and logically processing it with the load signal LOAD at an AND gate 8a;
This signal is latched by the D-flip-flop 3b in synchronization with the shift clock CLKI to generate a signal CRY for performing complementary sign rule violation processing. In this example, when the sub signal ^Ux is "1", the complementary sign rule is violated.

Exclusive OR circuit (E
X-OR) 3c performs exclusive OR processing on the signal CRY generated by the AND gate 3a and the D-flip-flop 3b and the data SDI serially output from the shift register 1, and uses this as the shift clock CLK.
By latching it in the D-flip-flop 3d in synchronization with I, the serial data SD containing the complement sign rule violation and multiplexed with the sub-signal ^Ux is output as shown in FIG. There is.

The reception and reproduction of the sub-signal AUX multiplexed in this manner is performed by detecting a violation of the complementary code rule.

(Problem to be Solved by the Invention) However, in the signal conversion circuit configured as described above, after converting parallel data into serial data with a complementary code inserted, processing for violating the complementary code rule is performed on this data. Since the circuit is configured as follows, the problem is that the circuit configuration becomes complicated. Furthermore, problems such as the need to synchronize timing each time using flip-flops are raised.

The present invention has been made in consideration of these circumstances, and its purpose is to easily and efficiently perform the insertion of complementary codes and the multiplexing of sub-signals due to violations of the complementary code rules. Moreover, it is an object of the present invention to provide a highly practical signal conversion circuit having a small circuit configuration scale.

[Structure of the Invention (Means for Solving the Problem) The present invention relates to a signal conversion circuit that converts an n (rrl, 2,...) bit parallel signal into an (n+1) bit serial signal, The n-bit parallel signal is input to the remaining input terminal of a parallel input serial output type shift register which inputs the n-bit parallel signal to consecutive n input terminals among the n input terminals. The present invention is characterized in that an exclusive OR circuit is provided for providing an exclusive OR signal of any one bit of the n-bit parallel signal and a sub-signal other than the n-bit parallel signal.

(Function) According to the present invention configured as described above, it is possible to simultaneously convert a parallel signal into a serial signal in the shift register and insert a complementary code. ”, it is possible to perform complementary code rule violation processing on the complementary code, so the complementary code violation intrusion circuit shown in FIG. Since it is only necessary to create the load signal for loading the parallel signal into the shift register, the circuit configuration can be significantly simplified and the circuit configuration can be made smaller and more compact. .

(Embodiment) Hereinafter, a signal conversion circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of a signal conversion circuit according to one embodiment. In this embodiment, as in the case of FIG. 3 described above, 5-bit parallel data D0 to D4 will be input and this will be explained as being converted into 6-bit serial data. Further, the same parts as those of the circuit elements shown in FIG. 3 will be described with the same reference numerals.

The signal conversion circuit of this embodiment is parallel data D.

- Input terminal P for 6 bits, which is 1 bit more than the bit number of D4. -P, and the above parallel data D. -D4
A parallel manual serial output type shift register 1 which inputs the signals in parallel to five consecutive input terminals P, ~P, and D-
A timing circuit 2 consisting of a flip-flop 2a and a NOR gate 2b, and the parallel data D0 to D4
1 bit (data D.) and the sub-signal AUX are subjected to exclusive OR processing, and the remaining 1-bit input terminal P of the shift register I is obtained. Exclusive OR circuit (EX-OR
)4.

The timing circuit 2, like the timing circuit in the circuit shown in FIG. Parallel data D. - D the clock CLKO corresponding to the period of D4.
- The load signal LOA for loading the parallel data is latched into the flip-flop 2a, and the latched data and the clock CLKO are logically processed by the NOR gate 2b.
D is generated and given to shift register 1.

According to the embodiment circuit configured in this way, parallel data D is generated at a predetermined period. -D4 arrives, the parallel data D0 to D4 are transferred to the input terminal P of the shift register l-,
~ P5 is introduced as is, and the above parallel data D
. - 1 bit D of D4. is given to EX-OR4. However, at this time, if the sub signal AUX input to the other terminal of EX-OR4 is '1'', then
The 1-bit data D0 is a complementary code whose logic is inverted by exclusive OR processing with the sub-signal AUX. and the input terminal P of the shift register 1. will be given to

On the other hand, if the sub signal AUX inputted to the other terminal of EX-OR4 is "0", then the EX-OR4
operates in positive logic, so the 1-bit data D. is the input terminal P of the shift register 1 as it is.

will be given to

As a result, as shown in the operation timing diagram in FIG. 2, the parallel data D0 to D4 arriving at a predetermined period are
Its complementary code is generated in synchronization with the load signal LOAD, which is synchronized with the arrival timing of the load signal LOAD. Or data D that violates the complementary sign rule for the sub signal ^Ux. and are read into shift register 1 in parallel. And these parallel data D. ~D
4 and complementary code Do (or data D that violates the complementary code rule).

) is a complementary code as shown in FIG. 2 in synchronization with the shift clock CLKl. (Or data D that violates the complement sign rule.

) at the beginning of the parallel data paste. p Dl + D
2 rD, , D4 are serially read out in this order and output as serial data SD. That is, shift register l
From then on, parallel/serial conversion is performed, and at the same time, complementary encoding is performed. is inserted, and the serial data SD processed to violate the complement sign rule is output.

Therefore, in this embodiment, the complement rule violation insertion circuit provided at the output stage of the shift register 1 can be substantially unnecessary, and the exclusive OR circuit provided at the input stage of the shift register 1 ( EX-OR) Complement code using only 4. It becomes possible to effectively perform the insertion of the sub-signal AUX and the multiplexing process of the sub-signal AUX by the complementary sign rule violation process. As a result,
The circuit configuration can be simplified and the size can be reduced.

In addition, since the timing circuit 2 only needs to generate the load signal LOAD, it is much better than the conventional circuit, which needed to generate an insertion timing signal, a special shift clock that caused missing teeth, etc. in addition to the load signal. , the circuit configuration can be greatly simplified, and this also allows the overall circuit configuration to be made simple and compact.

Furthermore, in this embodiment, for example, 4-bit parallel data D. -D3, the input terminal P of the shift register 1 can be converted by simply changing the ratio between the clock CLKO and the clock CLKI. The use of -P4 has the advantage that parallel/serial signal conversion can be performed as is without changing the circuit.

Note that the present invention is not limited to the above embodiments. For example, in the above embodiment, the case where the parallel data is 5 bits has been explained, but even if it is 3 bits, 4 bits, or 6 bits or more, a shift register is used that sets the input terminal of these bit numbers plus 1 bit to H. It can be implemented similarly by Further, in the above embodiment, parallel data D is used. Although we have explained the case where a shift register having the number of input terminals equal to the number of bits of ~D and I + 1 bit is used, a shift register having the number of input terminals equal to the maximum number of bits of parallel data + 1 bit is provided in advance, and this shift register is used. Parallel data having less than the above maximum number of bits may be converted.

It also performs negative OR as an exclusive OR circuit (EX-
By using NOR), it is possible to configure the circuit so that a violation of the complementary code rule is inserted when the sub signal AIIX is "1".In addition, the number of bits of the complementary code and the insertion position of the complementary code can be changed. , parallel data D to shift register.-D
Regarding the load timing etc. in No. 4, various modifications can be made without departing from the gist of the present invention.

[Effects of the Invention] As detailed above, according to the present invention, at least (n+
1) Using a parallel input serial output type shift register having input terminals for bits and an exclusive OR circuit,
The upper fc! By manually inputting the n-bit parallel signal and logically processing and applying one bit of the n-bit parallel signal to the remaining input terminal with the sub-f3 signal through the exclusive OR circuit, a complementary code is generated. Since the insertion of the signal and the insertion of the violation of the complementary sign rule are simultaneously controlled, it is possible to obtain an (n+1)-bit signal that has been converted into a parallel/serial signal very easily, and the signal conversion circuit has a simple configuration and a small circuit size. can be expressed.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of a signal conversion circuit according to an embodiment of the present invention, FIG. 2 is a timing diagram used to explain the operation of the circuit, and FIG. 3 is a circuit configuration diagram of a conventional four-way signal conversion circuit. FIG. 4 is a timing diagram used to explain the operation of the circuit. l...Shift register, 2...Timing circuit, 2
a...D flip-flop, 2b...Noah gate,
4...Exclusive OR circuit, Do-D4...Parallel data, D...Complementary code, AUX...Sub signal, C
I, KO: Clock according to RJJA of parallel data, C1, KI: Clock according to the speed of serial data, LOAD: Load signal, SD: Serial data.

Claims (1)

[Claims] Parallel signals of n (n=1, 2,...) bits are
)-bit serial signal, a parallel input serial output type shift register that inputs the n-bit parallel signal to consecutive n input terminals among (n+1) input terminals; An exclusive OR circuit that provides an exclusive OR signal of any one bit of the n-bit parallel signal and a sub-signal other than the n-bit parallel signal to the remaining input terminal of this shift register. and a timing circuit that drives the shift register and serially outputs an (n+1)-bit parallel input signal at a predetermined speed.