JPH02179032A - Signal conversion circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit scale with simple constitution by providing a parallel input serial output shift register having an input terminal, an inverting circuit and a timing circuit and applying the parallel serial conversion and the insertion of a complementary code simultaneously. CONSTITUTION:Parallel data D0-D4 are led to input terminals P1-P5 of a shift register 10 as they are. Moreover, after the one bit D0 is inverted logically at an inverter 30, it is led to the input terminal P0 of the register 10 as the complementary code. Then the data D0-D4 and the complementary code are loaded to the register 10 synchronously with the arrival timing of the data D0-D4 from a timing circuit 20, e.g. synchronously with a load signal LOAD. Then the data are read synchronously with a clock CLK 1 and outputted as serial data SD in the order of the data D0, D1, D2, D3, D4 while taking the complementary code as the head.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention relates to a signal used for converting a parallel signal into a serial signal in which the same code is continuously suppressed, for example in a video signal transmission device. Regarding conversion circuits.

(Prior art) Both the NRZ code and the AMI code, which are often used as transmission codes, are “0” or “1” for a long period of time depending on the case.
'' may occur consecutively, which may cause problems in timing extraction.Therefore, various means have been devised to prevent consecutive ``0''s or 1''s.For example, in baseband transmission, A same code continuous suppression code is used. This method using the same code continuous suppression code has N
There are many methods to convert RZ data to CMI code, but one of them is to convert n-bit parallel data to n+1-bit serial data, and use the remaining 1 bit to convert a specific bit of the above n bits. Some data are transmitted by inserting a complementary code.

FIG. 3 shows the configuration of a signal conversion circuit to which this method is applied, and has the same number of input terminals P as the number of bits of parallel data (5 bits in this example). -P4], a timing generation circuit 2, and a complementary code insertion circuit 3. In the figure, when parallel data Do-D4 arrives, the timing generation circuit 2 generates a load signal LOAD for parallel data loading and a shift clock CLKS for serial output, as shown in FIG. Therefore, the above parallel data D. ~D4 is load signal LO
The data is loaded into the shift register 1 in synchronization with AD, and then sequentially read out as serial data SDI in synchronization with the shift clock CLKS. At this time, the shift clock CLKS is obtained by deleting one bit every five bits from the clock CLKI whose speed is set to six times the speed of the parallel data D and %D4, as shown in FIG. Therefore, the serial data SDI read from the shift register 1 is parallel data D as shown in FIG. -D4 is converted into serial data and one extra bit is added.

When the serial data SDI including the remainder bits is outputted from the shift register 1, this pig SDI is inputted to the complementary code insertion circuit 3. This complementary code insertion circuit includes, for example, a flip-flop 3 for pig inversion as shown in FIG.
1, a logic circuit 32 for inserting complementary codes, and a flip-flop 33 for output. For this reason, -to-,
When serial data SD1 including a surplus bit is supplied from the conversion shift register 1, the sign of this data SD1 is first inverted in a flip-flop 31 as shown in FIG. Logic processing is performed in synchronization with the insertion timing signal CLOAD, whereby the complementary code D4 is inserted into the remainder bit. The serial data SD' into which the complementary code D4 has been inserted is output after its timing is readjusted by the flip-flop 33 in synchronization with the clock CLKI.

Thus, 5-bit parallel data D. Serial data SD is obtained by converting ~D4 into 6 bits including a complementary code. If such data SD is transmitted, even if "0" is consecutive in parallel data, the "0"
``Continuity can be limited to a maximum of 5 bits, which makes it possible to reliably perform timing recovery on the relay side or the receiving side.

(Problem to be Solved by the Invention) However, the conventional signal conversion circuit described above is configured to convert parallel data into serial data including surplus bits and then insert a complementary code into the surplus bits. . For this reason, a shift register 1 for parallel/serial conversion and a complementary code insertion circuit 3 are required, and in addition, the timing generation circuit 2 also requires not only the load signal LOAD but also the insertion timing signal CLOAD and a special code that causes missing teeth. A shift clock CLKS must be created. For this reason, there was a problem that the circuit configuration was complicated and cumbersome.

Therefore, the present invention has focused on the above-mentioned circumstances, and aims to provide a signal conversion circuit having a simple configuration and a small circuit scale.

[Structure of the Invention] (Means for Solving the Problem) The present invention converts an n (n-1, 2, . . .) bit parallel signal into an n+k (k-1, 2, . . .) bit serial signal. A signal conversion circuit for converting into a signal and outputting the signal is provided with a parallel input serial output type shift register having input terminals for at least n+k bits, an inverting circuit, and a timing circuit, and among the input terminals of the shift register, The n-bit parallel signal is input to consecutive n input terminals, and one bit of the n-bit parallel signal is inverted by the inverting circuit and input to the remaining input terminals of the shift register. The n+k bit parallel signal input to the shift register is serially outputted at a predetermined speed by the timing circuit, thereby obtaining a signal-converted n+k bit serial signal.

(Function) As a result, according to the present invention, conversion from a parallel signal to a serial signal and insertion of a complementary code are performed simultaneously in the shift register, thereby making it possible to eliminate the need for a complementary code insertion circuit. In addition, in the timing circuit, only the signal for loading the parallel signal into the shift register needs to be created, and as a result, the complementary code insertion circuit described above can be eliminated, and the circuit configuration can be simplified and miniaturized. can.

(Embodiment) FIG. 1 shows the configuration of a signal conversion circuit in an embodiment of the present invention. In this embodiment as well, 5-bit parallel data D is used as in the case of FIG. -D4 to 6-bit serial data will be explained as an example.

The signal conversion circuit of this embodiment has parallel data Do-D4.
Input terminal p for 6 bits, which is 1 bit more than the number of bits of
a parallel input serial output type shift register 10 having an OP, a timing circuit 20, and an inverter 3.
It consists of 0. The timing circuit 20 is composed of a D flip-flop 21 and a NOR gate 22. And parallel data D. - The clock CLKO corresponding to the period of D4 is changed to the clock CLKI corresponding to the speed of the serial data SD (six times the parallel data Do to D4).
The Q output of this D flip-flop 21 and the clock CL are latched in synchronization with the D flip-flop 21.
A load signal LOAD is obtained by logically processing KO and KO by an OR gate 22, and this load signal LOAD is supplied to the load terminal LD of the shift register 10. On the other hand, the inverter 30 receives parallel data Do-D4. Bit D after this logical inversion
o is supplied to the input terminal Po of the shift register 1o. Further, the clock CLKI is supplied as is to the shift clock input terminal CK of the shift register 10.

With such a configuration, parallel data Do-D4
When the parallel data Do-D4 arrives, this parallel data Do-D4 is input to the input terminal P of the shift register 1o.

~ P5 is introduced as is, and the above parallel data D
. 1 bit Do of -D4 is logically inverted by the inverter 30 and then sent to the input terminal P of the shift register 10 as a complementary code 4. will be introduced in

In this state, when the timing circuit 2o generates a load signal LOAD as shown in FIG. 2 in synchronization with the arrival timing of the parallel data Do-D4, the parallel data Do-D4 is generated in synchronization with the load signal LOAD.
D4 and complement code 4 are each loaded into shift register 10.

And these parallel data D. .about.D4 and the complementary code Do are synchronized with the clock CLKI, and as shown in FIG. 2, parallel data is pasted starting with the complementary code 5. +Dl
+ D2 + D3 + D4 are serially read out in the order and output as serial data SD. That is, the shift register 10 outputs data SD which has been subjected to parallel/serial conversion and has a complementary code inserted at the same time.

Therefore, in this embodiment, the complementary code insertion circuit can be made unnecessary, and the circuit configuration can therefore be easily miniaturized. In addition, since the timing circuit 20 only needs to generate the load signal LOAD, compared to conventional circuits that needed to generate an insertion timing signal, a special shift clock that caused missing teeth, etc. in addition to the load signal. This greatly simplifies the circuit configuration.
This also makes it possible to easily downsize the entire circuit configuration. Furthermore, in this embodiment, for example, 4-bit parallel data D. -D3, the input terminal P of the shift register 10 can be converted by simply changing the ratio between the clock CLKO and the clock CLKI. -P4 has the advantage that it can be implemented as is without any circuit changes.

Note that the present invention is not limited to the above embodiments. For example, in the above embodiment, the case where the parallel data is 5 bits has been explained, but even if the parallel data is 3 bits, 4 bits, or 6 bits or more, it is possible to use a shift register having an input terminal for these bits + 1 bit. It can be implemented similarly.

Further, in the above embodiment, a case was explained in which a shift register having the number of input terminals equal to the maximum number of bits of parallel data Do-D4 + 1 bit was used, but it is possible to use a shift register having the number of input terminals equal to the maximum number of bits of parallel data + 1 bit in advance. The shift register may be provided to convert parallel data having less than -1- maximum number of bits. For example, when converting a video signal into a digital signal and transmitting it, 10 bits is sufficient as the number of parallel data bits, so in this case, a shift register with input terminal r- for 10+1 bits is provided in advance, This shift register may be used to convert parallel data in other cases (for example, in the case of 8 bits). In this way, the conversion circuit can be used as it is without changing its configuration, and a circuit with a wide range of application and rich versatility can be provided. Further, since it becomes easy to integrate the circuit, the circuit scale can be further reduced. In addition, the number of bits of the complementary code, the insertion position of the complementary code, the timing of loading parallel data Do to D4 into the shift register, etc. can be modified in various ways without departing from the gist of the present invention.

[Effects of the Invention] As detailed above, according to the present invention, at least n+k
A parallel manual serial output type shift register having input terminals for bits, an inverting circuit, and a timing circuit are provided, and n consecutive input terminals of each input terminal of the shift register are provided with input terminals for n bits. In addition to inputting a parallel signal, bits of the n-bit parallel signal are inverted by the inverting circuit and input to the remaining input terminals of the shift register, and the n+k bits input to this shift register are input. By outputting the parallel signals serially at a predetermined speed using the timing circuit, a signal-converted n+k-bit serial signal is obtained, thereby providing a signal conversion circuit with a simple configuration and small circuit scale. can.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a signal conversion circuit according to an embodiment of the present invention, FIG. 2 is a timing diagram used to explain the operation of the circuit, FIG. 3 is a circuit configuration diagram of a conventional signal conversion circuit, and FIG.
The figure is a circuit diagram showing an example of the complementary code insertion circuit of the same circuit.
6 are timing diagrams used to explain the operation of the circuits shown in FIGS. 3 and 4. FIG. 10... Shift register, 20... Timing circuit, 21... D flip-flop, 22... NOR gate, 30... Inverter, D O-D 4... Parallel data, Do... Compensation code, CLKO...Clock according to the cycle of parallel data, CLKI...Clock according to the speed of serial controller, LOA, D...
・Load signal, SD...serial data. Applicant's agent Patent attorney Takehiko Suzue Figure 1 1゜゜゜3゜4゜

Claims (1)

[Claims] Parallel signal of n (n=1, 2,...) bits to n+
In a signal conversion circuit that converts into a k (k=1, 2,...) bit serial signal and outputs it, at least n+k
a parallel input serial output type shift register having input terminals for bits, of which n consecutive input terminals receive the n-bit parallel signal; and k bits of the n-bit parallel signal. and a timing circuit that serially outputs the n+k bit parallel signal input to the shift register at a predetermined speed. Characteristic signal conversion circuit.