KR930004309B1 - Signal converting circuit - Google Patents

Abstract

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Description

Signal conversion circuit

1 is a circuit diagram of a signal conversion circuit in an embodiment of the present invention.

2 is a timing chart used for explaining the circuit operation of FIG.

3 is a circuit diagram of a signal conversion circuit in another embodiment of the present invention.

4 and 5 are main circuit diagrams of the circuit of FIG.

6 and 7 are timing charts used to explain the operation of the circuit shown in FIGS. 4 and 5;

8 is a circuit diagram of a scramble processing circuit of a signal conversion circuit according to another embodiment of the present invention.

The present invention relates, for example, to a signal conversion circuit used in a video signal transmission device for converting a parallel signal into a serial signal suppressing the continuation of the eastern arc (0 or 1).

Both the NRZ (non-zero return) code and the AMI (alternative mark conversion) code, which are frequently used as transmission codes, sometimes have closed loops in which "0" or "1" are continuous over a long period of time, causing problems in timing extraction. There is a case. Various means have been considered here to prevent the continuation of " 0 " or " 1 " heretofore. For example, in the baseband transmission, an eastern continuous uplink code is used. There are several types of eastern continuous suppression codes, such as converting NRZ data into CMI (Code Mark Conversion) codes. Among them, n + 1 bits are serialized one bit more than n bits of parallel data. There is an mBIC method that converts data and inserts an auxiliary code into the remaining one bit to transmit data.

According to this method, when a parallel input serial output shift register having a number of bits of parallel data (e.g. 5 bits) and an equal number of input terminals is provided and the parallel data is input to the shift register, the load signal from the timing generating circuit LOAD and shift clock CLKS are output to the shift register. For this reason, the parallel data is loaded into the shift register in synchronization with the load signal LOAD, and then sequentially read from the shift register as serial data SDI in synchronization with the shift clock CLKS. At this time, the shift clock is in the form of a pulse in which one bit is deleted at five-bit intervals from the clock CLK1 set at a frequency six times parallel data. Therefore, the serial data SD1 read out from the shift register is data formed by adding the remaining bits of one bit to the data obtained by converting the parallel data into serial data.

In other words, serial data SD1 including the remaining bits is output from the shift register. When this data SD1 is input to the auxiliary code inserting circuit, after this data code is inverted, the data is logically processed in synchronization with the insertion timing signal CLOAD to insert the auxiliary code into the remaining bits. The serial data SD 'having this auxiliary code inserted therein is output in synchronization with the clock CLK1.

As described above, serial data SD can be obtained by converting 5-bit parallel data into 6-bit data including an auxiliary code. Thus, in order to transmit the data SD, even in the case of parallel data, for example, even if "0" is continuous, the continuous "0" can be suppressed to the longest 5 bits, so that data can be reliably transmitted from the relay side or the reception side. It is renewable.

However, since the signal conversion circuit is configured to convert parallel data into serial data including the remaining bits, and then insert an auxiliary code into the remaining bits, the shift register and the auxiliary code insertion circuit for parallel / serial conversion are respectively provided. In addition, in the timing generating circuit, the load signal LOAD must create an insert timing signal CLOAD or a special shift clock that causes the shift from the beginning. Due to this, there is a problem that the circuit configuration is complicated and the scale becomes large. An object of the present invention is to provide a signal conversion circuit having a simple configuration and a small circuit size.

According to this invention, n + k (k = 1,2,…) bits, which are more than (k = 1, 2,…) bits than n (n = 1, 2,…) bits, are converted into serial signals. In the output signal conversion circuit, a parallel input serial output shift register having at least n + k bits of input terminals, an inverting circuit, and a timing circuit are provided so as to be continuous to each input terminal of the shift register. The n-bit parallel signal is input to the n input terminals, and k bits of the n-bit parallel signals are inverted by the inversion circuit and input to k input terminals that are the remainder of the shift register. As the parallel signal of n + k bits input to the register is serially output at a predetermined speed by the timing circuit, a serial signal of n + k bits which is signal converted is generated.

According to the present invention as described above, the conversion from the parallel signal to the serial signal in the shift register and the insertion of the auxiliary code are performed at the same time. Accordingly, there is no need to separately install a circuit for inserting the auxiliary code. In the timing circuit, only a signal for loading the parallel signal into the shift register needs to be prepared. As a result, the circuit configuration can be simplified and downsized, as well as not requiring an auxiliary code insertion circuit.

Further, according to the present invention, an auxiliary code insertion for converting the initial data of n (n = 1, 2 ...) bits into data of n + k (k = 1, 2, ...) bits and inserting an auxiliary code into the k bits. A circuit and a scramble processing circuit, generating a pseudo random code for holding a sub code among data output from the sub code inserting circuit by the scramble processing circuit, and outputting from the sub code inserting circuit according to the pseudo random code. A signal conversion circuit for scrambled the data is provided.

According to this signal conversion circuit, the transmission data is transmitted with the auxiliary code side held, whereby the position of the auxiliary code can be detected simply and reliably at the relay apparatus or the receiving side on the transmission path. Therefore, predetermined processing such as unscrambled processing can be reliably performed on the transmission data. In addition, since the scramble processing can be performed after the insertion of the auxiliary code, the additional operation of the remaining bits and the operation of adding the auxiliary code to the remaining bits do not need to be independently performed by another circuit, thereby simplifying the circuit configuration. It can be done.

A signal conversion circuit according to an embodiment of the present invention will be described with reference to FIG.

In the present embodiment, for example, a case of converting 5-bit parallel data D0 to D4 into serial data will be described as an example.

The signal conversion circuit according to the present embodiment includes a parallel input serial output shift register 10 and a timing circuit 20 having input terminals P0 to P5 corresponding to 6 bits, which are one bit more than the number of bits of the parallel data D0 to D4. And an inverter 30. The timing circuit 20 is composed of a D flip-flop 21 receiving the clocks CLK0 and CLK1, and a NOR gate 22 receiving the output Q of the flip-flop 21 and the clock CLK0.

In the signal conversion circuit, the clock CLK0 corresponding to the period of the parallel data D0 to D4 is synchronized with the clock CLK 1 having a frequency corresponding to the transmission speed of the serial data SD (six times the speed of the parallel data D0 to D4). The flip flop 21 is caught. As the output Q of this D flip-flop 21 and the clock CLK0 are logically processed by the NOR gate 22, the load signal LOAD is output from the NOR gate 22. This load signal LOAD is supplied to the load terminal LD of the shift register 10.

On the other hand, the inverter 30 is provided to logically invert the data DO in the parallel data D0 to D4, and supplies the bit D0 to the input terminal P0 of the shift register 10 after the logic inversion. The clock CLK1 is supplied as it is to the shift clock input terminal CK of the shift register 10.

로써 시프트레지스터(10)의 입력단자 P0에 도입된다. 이러한 상태로 타이밍회로(20)로부터 병렬데이타 D0∼D4의 도착타이밍에 동기하여 예를들면, 제 2 도에 나타난 것같이 로드신호 LOAD가 발생되면, 이 로드신호 LOAD에 동기하여 병렬데이타 D0∼D4 및 보조부호

는 시프트레지스터(10)에 각각 로드된다. 이들 병렬데이타 D0~D4 및 보조부호

는 클록 CLK1에 동기하여 제 2 도에 나타난 것같이 보조부호

를 선두로하여 병렬데이타인 D0, D1, D2, D3, D4의 순서로 직렬로 읽어내어져 직렬데이타 SD로 출력된다. 즉, 시프트레지스터(10)에서는 병렬/직렬 교환되어져, 동시에 보조부호가 삽입된 데이터 SD가 출력된다.Since the parallel data D0 to D4 arrive as described above, the parallel data D0 to D4 are introduced into the input terminals P1 to P4 of the shift register 10 as they are, and one bit D0 of the parallel data D0 to D4 is converted to the inverter. After the logic is reversed by 30, the auxiliary code

As a result, it is introduced to the input terminal P0 of the shift register 10. In this state, when the load signal LOAD is generated from the timing circuit 20 in synchronization with the arrival timings of the parallel data D0 to D4, for example, as shown in FIG. 2, the parallel data D0 to D4 in synchronization with the load signal LOAD. And auxiliary symbols

Are loaded into the shift registers 10, respectively. These parallel data D0 ~ D4 and auxiliary code

Is an auxiliary code as shown in Fig. 2 in synchronization with the clock CLK1.

The data is read serially in the order of parallel data D0, D1, D2, D3, and D4, and output as serial data SD. That is, in the shift register 10, data SD which is exchanged in parallel / serial and at which the auxiliary code is inserted at the same time is output.

According to the embodiment described above, it is not necessary to separately install a circuit for inserting an auxiliary code, which makes it possible to simplify the circuit configuration. In addition, since the timing circuit 20 only needs to generate the load signal LOAD, the circuit configuration of the timing circuit 20 can be greatly simplified, and thereby the overall circuit configuration can be simplified and miniaturized. In the present embodiment, for example, even when 4-bit parallel data D0 to D3 are converted into serial data, the ratio between the clock CLK0 and the clock CLK1 is merely changed, and the input terminals P0 to S1 of the shift register 10 are changed. The use of P4 has the advantage that it can be carried out without changing the circuit.

In the above embodiment, the parallel data is composed of 5 bits. However, even if the data is composed of 3 bits, 4 bits, or 6 bits or more, by using a shift register having an input terminal corresponding to the number of bits + 1 bit, This invention can be realized. In the above embodiment, a case has been described in which a shift register having an input terminal corresponding to the number of bits +1 bit of the parallel data D0 to D4 is used, but the number corresponding to the maximum number of bits +1 bit of the parallel data is described. A shift register having an input terminal may be provided in advance so that parallel data of less than the maximum number of bits may be converted into serial data by the shift register. For example, when converting and transmitting a video signal to a digital signal, 10 bits are sufficient for the number of bits of parallel data, and in this case, a shift register having an input terminal corresponding to 10 + 1 bits is provided in advance. By using this shift register, parallel data in other cases (for example, 8 bits) may be converted into serial data. This makes it possible to use the conversion circuit without changing its configuration, and to provide a wide range of applications, thereby providing a signal converter circuit rich in versatility. In addition, since the circuit can be easily formed, the circuit size can be further miniaturized. In addition, the number of bits of the auxiliary code, the insertion position of the auxiliary code, and the load timing of the parallel data D0 to D4 to the shift register can be modified in various ways.

As described in detail above, according to the present invention, a parallel input serial output shift register having an input terminal corresponding to at least n + k bits, an inverting circuit, a timing circuit, and the like are provided so that each input of the shift register is provided. N bits of parallel signals are input to the n input terminals connected to the terminal, and k bits of the n bits of parallel signals are inverted by the inversion circuit and input to the remaining k input terminals of the shift register. The parallel signal of n + k bits input to this shift register is converted into a serial signal at a predetermined speed by a timing circuit, and the converted n + k bit serial signal is output. As a result, a signal conversion circuit having a simple configuration and a small circuit size can be provided.

Next, another embodiment of the present invention will be described with reference to FIG.

This embodiment provides a signal conversion circuit that adds a scramble function to the features of the above embodiment, and this signal conversion circuit is composed of an auxiliary code insertion circuit 101 and a scramble processing circuit 102.

If the auxiliary code inserting circuit 101 is temporarily inputting the 5-bit parallel data D0 to D4 as initial data, as shown in Fig. 4, the auxiliary code insertion circuit 101 corresponds to 6 bits, which is one bit more than the number of bits of the parallel data D0 to D4. A parallel input serial output shift register 111, a timing circuit 112, and an inverter 113 having a number of input terminals P0 to P5. The timing circuit 112 is composed of a D flip-flop 114 that receives clocks CLK0 and CLK1 and a NOR gate 115 that receives the output Q and clock CLK0 of the flip-flop 114. The clock CLK0 corresponding to the frequency of the parallel data D0 to D4 is caught by the D flip-flop 114 in synchronization with the clock CLK1 corresponding to the transmission speed of the serial data SD (six times the parallel data D0 to D4). The output Q of the flop 114 and the clock CLK0 are logically processed by the NOR gate 115 so that the load signal LOAD is output to the load terminal LD of the shift register 111. The inverter 113 is provided to logically invert the data D4 in the parallel data D0 to D4, and after this logic inversion, the bit D4 is supplied to the input terminal P5 on the MBS side of the shift register 111. The clock CLK1 is provided to the shift clock input terminal CK of the shift register 111 as it is.

On the other hand, the scramble processing circuit 102 includes an M-series generator 121 for generating a pseudo random pulse sequence MP, a control circuit 122 for controlling the operation of the M-series generator 121, and an auxiliary code insertion circuit 101. It consists of an exclusive logic circuit 123 that scrambles the serial data SD by exclusively processing the pseudo-random pulse sequence MP generated by the serial data SD and the M-series generator 121 outputted from the. The control circuit 122 consists of a D flip-flop 124 and an end gate 125, for example, as shown in FIG. The load signal LOAD generated by the timing circuit 112 of the auxiliary code insertion circuit 101 is delayed by only one bit in synchronization with the clock CLK 1 by the D flip-flop 124 and is inverted. The AND gate 125 is gated by the 1-bit delayed inverted signal LOAD ', so that the control clock CS is generated from the AND gate 125.

로써, 시프트레지스터(111)의 입력단자 P5에 도입된다. 이 상태로 타이밍회로(112)로부터 병렬데이타 D0∼D4의 도착 타이밍에 동기하여 예를들면, 제 6 도에 나타난 것같이 로드신호 LOAD가발생되면, 이 로드신호 LOAD에 동기하여 병렬데이타 D0∼D4 및 보조부호

는 시프트레지스터(111)에 각각 로드된다. 이들 병렬데이타 D0∼D4 및 보조부호

는 클록 CLK1에 동기하여 제 6 도에 나타난 것같이 병렬데이타 D0를 선두로 하여 D1, D2, D3, D4 보조부호

순으로 직렬로 시프트레지스터(111)에서 읽어내어, 직렬데이타 SD로써 출력된다. 즉, 시프트레지스터(111)에서는 병렬/직렬변환에 따른 나머지 비트의 부가와, 이 나머지 비트로 보조부호의 삽입이 동시에 행하여진 데이타 SD가 출력된다.With such a configuration, when parallel data D0 to D4 are input to the auxiliary code insertion circuit 101, the parallel data D0 to D4 are introduced into the input terminals P0 to P4 of the shift register 111 as they are, and the parallel data D0 to D4. After the 1-bit D4 is logically inverted by the inverter 113, the auxiliary code

As a result, it is introduced to the input terminal P5 of the shift register 111. In this state, when the load signal LOAD is generated from the timing circuit 112 in synchronization with the arrival timings of the parallel data D0 to D4, for example, as shown in FIG. 6, the parallel data D0 to D4 is synchronized with the load signal LOAD. And auxiliary symbols

Are loaded into the shift registers 111, respectively. These parallel data D0 to D4 and auxiliary code

Synchronously with the clock CLK1, the auxiliary codes D1, D2, D3, and D4 with the parallel data D0 as shown in FIG.

The shift register 111 is read in serial order and output as serial data SD. That is, the shift register 111 outputs the data SD in which the addition of the remaining bits due to the parallel / serial conversion and the insertion of the auxiliary code into these remaining bits is performed at the same time.

에 대응하는 펄스가 삭제된 펄스신호이다. 이로 말미암아, M계열 발생기(121)에서 제어클록 CS에 동기하여 직렬데이타 SD의 보조부호측 형성위치(D4,

)에 대응하는 위치에서는 제 7 도에 나타난 것같이 부호변화가 금지된 유사 임의 펄스열 MP가 발생된다. 따라서, 지금 임시로 보조부호 삽입회로(111)로부터 제 7 도에 나타난 것같은 직렬데이타 SD가 출력되고, 또 M계열 발생기(121)로부터 제7도에 나타난 것같은 유사 임의 펄스열 MP가 발생되었다고 한다면, 배타적 논리화회로(123)의 출력은 제7도에 나타난 신호 SSD가 된다. 즉, 비트 D0∼D4는 유사 임의 펄스열 MP에 의하여 스크램블 처리되고, 또 직렬데이타 SD의 보조부호측(D4,

)이 보존된 직렬데이타 SSD가 출력된다.On the other hand, in the scramble processing circuit 102, the control clock CS is created from the load signal LOAD and the clock CLK1 supplied from the timing circuit 112 of the auxiliary code insertion circuit 101. This control clock CS is an auxiliary code of serial data SD as shown in FIG.

The pulse signal corresponding to the pulse signal is deleted. This causes the M-series generator 121 to form the auxiliary code side of the serial data SD in synchronization with the control clock CS.

At the position corresponding to), as shown in Fig. 7, a pseudo random pulse string MP is generated which is prohibited from changing the code. Therefore, if the serial data SD as shown in FIG. 7 is temporarily output from the auxiliary code insertion circuit 111 now, and the pseudo random pulse string MP as shown in FIG. 7 is generated from the M-series generator 121, The output of the exclusive logic circuit 123 becomes the signal SSD shown in FIG. That is, the bits D0 to D4 are scrambled by the pseudo random pulse string MP, and the auxiliary code side D4, of the serial data SD, is scrambled.

) Is outputted.

사이의 보조부호측은 보존되어 있기 때문에, 중계장치나 수신측에서는 전송데이타로부터 그대로 간단하고 확실하게 보조부호를 검출할 수 있고, 이것에 의하여 오류검사, 위상(位相)조정등의 신호처리나 비스크램블처리 등을 간단하고 확실하게 행할 수 있다. 또한 보조부호 삽입후의 데이터에 대하여 스크랜블 처리를 행할 수 있기 때문에, 병렬데이타 D0∼D4로부터 직렬데이타 SD로 변환, 결국 속도변환에 의해 나머지 비트의 부가와, 이 나머지 비트로 보조부호의 삽입을 시프트레지스터(111)로 일괄하여 행할 수 있도록 되고, 이 결과, 회로구성을 간단 소형화할 수 있다.Therefore, if such a serial data SSD is transmitted, D4,

Since the auxiliary code side is stored between the relay and the receiving side, the auxiliary code can be detected simply and reliably from the transmission data as it is, thereby allowing signal processing such as error checking and phase adjustment or nonscramble processing. And the like can be performed simply and reliably. In addition, since the scramble processing can be performed on the data after the insertion of the auxiliary code, conversion from the parallel data D0 to D4 to the serial data SD and finally the addition of the remaining bits by speed conversion and the insertion of the auxiliary code into the remaining bits are performed by the shift register. This operation can be performed collectively at 111. As a result, the circuit configuration can be easily downsized.

In the above embodiment, the scramble processing circuit is configured using the M series generator 121, but this is a self synchronous scramble which performs scramble processing by self synchronous instead of the M series generator 121 and the exclusive logic circuit 123. It may be configured using a circuit. 8 shows an example of a self-synchronizing scrambled circuit configuration, and is composed of five-stage shift registers 131 to 135 and exclusive logic circuits 136 and 137. FIG. According to this circuit, the output signal SD of the auxiliary code insertion circuit 101 is input to the ultra-short shift register 131 with the exclusive logic circuit 137. The output of the two-stage shift register 132 and the output of the termination shift register 135 are input to the exclusive logic circuit 136. The output of this exclusive logic bypass 136 and the signal SD are logically processed by the exclusive logic circuit 137.

In the previous embodiment, the control clock CS is generated by using the load signal LOAD and the clock CLK1 generated by the timing circuit 112 of the auxiliary code insertion circuit 101 in the control circuit 122, but the auxiliary clock from the other serial data SD. The insertion position of the code D4 may be detected, and a control clock CS may be created based on this detection result. In addition, as in the previous embodiment, a shift register having an input terminal number corresponding to the maximum number of bits + 1 bit of parallel data is provided in advance, so that the parallel register of less than the maximum number of bits is converted into this shift register. Also good. That is, when converting and transmitting a video signal to a digital signal, 10 bits are sufficient as the number of parallel data. In this case, a shift register having an input terminal corresponding to 10 + 1 bits is provided in advance, and this shift register is used. The parallel data of other cases (for example, when the 8-bit inverted output is input to the ninth bit) may be converted into serial data. This embodiment can also be implemented by installing the inverter 113 on the LBS side as in the first diagram. In this way, the scrambling process which preserve | saved the auxiliary code side can be performed, without changing the structure of a conversion circuit, and the circuit which is versatile and has a wide application range can be provided. In addition, the integrated circuit can be easily made, and the circuit size can be further miniaturized. The structure of other auxiliary code inserting means or scramble processing means, the number of bits n of input data, the number of bits k of auxiliary code or the insertion position of the auxiliary code, the load timing of parallel data D0 to D4 of the shift register, etc. Various modifications can be made without departing from the spirit of the invention.

As described in detail above, a simple circuit is generated by generating a pseudo-random code for preserving the sub-code side among the data output from the sub-code inserting means and performing a scramble process of the data output from the sub-code inserting means by the pseudo random code. Despite the configuration, it is possible to provide a signal conversion circuit capable of obtaining transmission data with the auxiliary code side securely held.

Claims (10)

A number corresponding to the second predetermined number for converting the first predetermined number n bits of the parallel signal into a serial signal by converting the second predetermined number n + k bits at least 1 bit (k) more than the first predetermined number to the serial signal. A parallel input serial output shift register means having parallel inputs of a first predetermined number (n) of input terminals continuous in these input terminals, and at least one bit (k) signal in the parallel signal; The inverting signal is loaded into the inverting circuit means for inputting the remaining input terminal of the shift register means, the parallel signal of the first predetermined number of bits inputted to the shift register means, and the inverted signal to the shift register means. A signal side constituted by timing circuit means for outputting a first timing signal and a second timing signal for reading the loaded signal at a predetermined speed to the shift register means. Circuit. The signal conversion circuit according to claim 1, wherein the shift register has an LSB input terminal corresponding to a least significant bit (LSB), and is constituted by the inverting circuit means and an inverter for inputting the inverted signal to the LSB input terminal. 2. The apparatus of claim 1, wherein the timing means receives a first clock signal having a frequency corresponding to a transmission speed of the serial data and a second clock signal having a frequency lower than that of the first clock signal, and converts the second clock signal into the first clock signal. And a logic gate means for logic processing a flip-flop means applied in synchronization with one clock signal and an output of the second clock signal and the flip-flop means to output the second timing signal. Converts the initial data of the first predetermined number (n) bits into data of the second predetermined number (n + k) bits at least one bit (k) more than the first predetermined number, and adds an auxiliary code to the first bit (k). An auxiliary code inserting means for inserting and outputting the output data, and a pseudo random code for generating the output data auxiliary code side from the auxiliary code inserting means, and generating the pseudo random code from the auxiliary code input means by the pseudo random code. And a scramble processing means configured to scramble the output data of the output signal. 5. The method according to claim 4, wherein the auxiliary code inserting means is at least a second predetermined number for converting into a second predetermined number (n + k) bit serial signal, which is k bits more than the parallel signal of the first predetermined number (n) bits. A parallel input serial output shift register means having a number of input terminals corresponding to the input signal and a parallel signal being input to a continuous first predetermined number n of input terminals in these input terminals and a signal of at least one bit in the parallel signal. Inverts the inverted circuit means for inputting the inverted signal to the remaining input terminals of the shift register means, and loads the inverted signal in parallel with the first predetermined number of bits inputted to the means of the electric shift register and the inverted signal to the shift register means. Timing circuit means for outputting to said shift register means a first timing signal for carrying out and a second timing signal for reading the loaded signal at a predetermined speed; Signal conversion circuit composed by. 5. The M scrambling apparatus according to claim 4, wherein the scramble means is generated from an M sequence generator for generating a pseudo random pulse sequence MP, a control circuit for controlling the operation of the M sequence generator, data output from the auxiliary code inserting means, and the M sequence generator. And an exclusive logic circuit configured to scramble the data by performing exclusive logic processing on the pseudo-random pulse sequence. 7. The control circuit of claim 6, wherein the control circuit delays the load signal generated by the auxiliary code insertion circuit by only one bit, inverts the gate signal, and inverts the gate signal by the inverted signal. Signal inversion circuit composed of an end gate output to a series generator. 5. The signal conversion circuit according to claim 4, wherein the scramble means is constituted by a self synchronous scramble circuit that scrambles the output data of the code insertion means by self synchronous. At least n + k in a signal conversion circuit that converts n + n bits of n (n = 1,2,…) bits to n + k bits more than n and converts them into serial signals. It has an input terminal corresponding to the number of bits, and among the parallel input serial output shift registers in which the n-bit parallel signal is input to the n consecutive input terminals, the k-bit is inverted among the n-bit parallel signals. And an inverting circuit input to the remaining k input terminals of the shift register, and a timing circuit for serially outputting a parallel signal of n + k bits input to the shift register at a predetermined speed. An auxiliary code for converting the initial data of n (n = 1,2,…) bits into n + k bits of data having k (k = 1, 2,…) bits more than n, and inserting an auxiliary code into the k bits. A scramble process for generating a pseudo random code for holding the sub code side among the data output from the sub code inserting means, and the scramble process for performing scramble processing of the data output from the sub code inserting means by the pseudo random code. A signal conversion circuit constituted by means.

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