JP2670328B2 - Signal conversion circuit - Google Patents

Description

The present invention relates to a signal conversion circuit used for reducing autocorrelation of transmission data in, for example, a video signal transmission device.

(Prior Art) NRZ code and AMI code, which are often used as transmission codes,
In some cases, “0” or “1” may continue for a long time depending on the case, which may cause a problem in timing extraction. Further, if the transmission data has a repetition of a data pattern with a short cycle, a single frequency component generated thereby may cause cross modulation or the like in the transmission path section. Therefore, conventionally, various means have been considered to prevent these, and as one of them, for example, original data is converted into a homo-code continuous suppression code by using a complementary code. On the other hand, when the original data part corresponding to the complementary sign rule periodically exists in the original data, this may be erroneously detected. In order to avoid this, it is known that the original data is scrambled using a pseudo random code sequence.

As another conventional circuit for performing the scrambling process by using the complementary code for the original data, there is, for example, one shown in FIG. That is, the surplus bit adding circuit 51 and the complementary sign adding circuit 53 are separated, the original data DT is first introduced into the surplus bit adding circuit 51, and the speed conversion is performed, for example, at a constant interval as shown in FIG. Insert extra bits. Then, the scramble circuit 52 performs scramble processing on the entire data ET after the extra bits are inserted, and then the data FT after the scramble processing is performed.
Is introduced into the complementary code adding circuit 53, where the complementary code of the code one bit before is inserted into the surplus bit position in the data FT as shown in FIG. 8 GT, and the output is sent as the transmission data GT. I am trying. With such a configuration, since the complementary code rule is transmitted while being held, the relay device or the receiving side can easily detect the complementary code and reliably perform a predetermined process such as descrambling. However, such a conventional circuit has a surplus bit adding circuit 51 and a complementary sign adding circuit.
Since 53 and 53 must be separated and provided in an independent state, there is a problem that the circuit configuration becomes complicated.

(Problems to be Solved by the Invention) As described above, the conventional signal conversion circuit has a problem that the circuit configuration becomes complicated if the complementary sign rule is held, and the present invention focuses on this point. However, it is an object of the present invention to provide a signal conversion circuit having a simple circuit configuration and capable of obtaining transmission data in which the complementary sign rule is reliably retained.

[Structure of the Invention] (Means for Solving the Problem) The present invention uses n + (n = 1, 2, ...) Bit original data as n +
Complementary code inserting means for converting into k (k = 1, 2, ...) Bit data and inserting and outputting a complementary code in the k bits, and data output from the complementary code inserting means in synchronization with the clock. Pseudo-random code generating means for generating bit-synchronized pseudo-random code, scrambling means for scrambling the data output from the complementary code inserting means by the pseudo-random code generated by the pseudo-random code generating means, and control And means. Then, the control means stops the clock input to the pseudo random code generating means at the complementary code insertion position in the data output from the complementary code inserting means to set the complementary code insertion position to 1
The code change of the pseudo-random code is prohibited from the position before the bit to the complementary code insertion position, whereby the complementary sign rule of the data output from the scramble processing means is retained.

(Operation) As a result, according to the present invention, the transmission data is transmitted in a state in which the complementary code rule is held, whereby the position of the complementary code can be easily and reliably ensured at the relay device or the receiving side on the transmission path. It becomes possible to detect. Therefore, it is possible to reliably perform a predetermined process such as a descramble process on the transmission data. Further, since the scrambling process can be performed after inserting the complementary code, it is not necessary to separately perform the operation of adding the surplus bit and the operation of adding the complementary code to the surplus bit in separate circuits as in the conventional case. This can simplify the circuit configuration.

(Embodiment) FIG. 1 shows a configuration of a signal conversion circuit according to an embodiment of the present invention. This circuit is a complementary code insertion circuit 1
And a scramble processing circuit 2.

First, the complementary code insertion circuit 1 is temporarily set to 5 as the original data.
Assuming that the parallel data D ₀ to D ₄ bits are input, the input terminals P ₀ to P ₅ of the 1-bit high 6 bits than the number of bit parallel data D ₀ to D ₄ as shown in Figure 2 A parallel input serial output type shift register 11 having,
It is composed of a timing circuit 12 and an inverter 13.
Of these, the timing circuit 12 is composed of a D flip-flop 14 and a NOR gate 15. Then, the clock CLK0 corresponding to the period of the parallel data D ₀ to D _4, in synchronization with the clock CLK1 corresponding to the speed of the serial data SD (6 times the parallel data D ₀ to D ₄₎ in the D flip-flop 14 The load signal LOAD is obtained by latching and logically processing the output of the D flip-flop 14 and the clock CLK0 by the OR gate 15, and the load signal LOAD is supplied to the load terminal LD of the shift register 11. The inverter 13 logically inverts the parallel data D _{0 to} D ₄ , and supplies the bit ▲ ▼ after the logical inversion to the input terminal P ₅ on the MSB side of the shift register 11. The clock CLK1 is directly supplied to the shift clock input terminal CK of the shift register 11.

On the other hand, the scramble processing circuit 2 includes an M-sequence generator 21 that generates a pseudo-random pulse train MP, and this M-sequence generator 21.
Control circuit 22 for controlling the operation of the above, and the complementary code insertion circuit 1
Serial data SD output from the M sequence generator 21
And a pseudo-random pulse train MP generated from the above, and an exclusive OR circuit 23 for performing an exclusive logical process to scramble the serial data SD. Of these, the control circuit 22
Is composed of, for example, a D flip-flop 24 and an AND gate 25 as shown in FIG. 3, and a load signal LOAD generated from the timing circuit 12 of the complementary code inserting circuit 1
Is delayed by 1 bit and inverted in synchronization with the clock CLK1 by the D flip-flop, and the AND gate 25 is gated by the inverted signal LOAD 'delayed by 1 bit to generate the control clock CS.

With this configuration, when the parallel data D _{0 to} D ₄ are input to the complementary code insertion circuit 1, the parallel data
D ₀ to D ₄ are as introduced into the input terminal P ₀ to P ₅ of the shift register 11, also complement code after 1 bit D ₄ of the parallel data D ₀ to D ₄ is logically inverted by the inverter 13 ▲
It is introduced to the input terminal P ₅ of the shift register 11 as ▼.
In this condition, the parallel data from the timing circuit 12
When a load signal LOAD is generated in synchronization with the arrival timing of D _{0 to} D ₄ as shown in FIG. 4, for example, this load signal LO
In parallel with AD, the parallel data D _{0 to} D ₄ and the complementary code ▲
▼ are loaded into the shift register 11, respectively. Then, these parallel data D _{0 to} D ₄ and the complementary code ▲
▼ is synchronized with the clock CLK1 and is D ₁ , D ₂ , D ₃ , D ₄ and the complementary code ▲ ▼ with D ₀ of the parallel data at the head as shown in FIG.
Are serially read in this order and output as serial data SD. That is, from the shift register 11, data in which the addition of the surplus bit by the parallel / serial conversion and the insertion of the complementary code into the surplus bit are simultaneously performed.
SD is output.

On the other hand, in the scramble processing circuit 2, the load signal LO supplied from the timing circuit 12 of the complementary code insertion circuit 1 is supplied.
The control clock CS is generated from AD and the clock CLK1. This control clock CS is obtained by deleting the pulse corresponding to the complementary code insertion position of the serial data SD as shown in FIG. Therefore, from the M-sequence generator 21, the serial data is synchronized with the control clock SC.
At a position corresponding to the complementary sign rule formation position D ₄ , ▲ ▼ of SD, a pseudo random pulse train MP in which sign change is prohibited is generated as shown in FIG. Therefore, if it is assumed that the complementary code insertion circuit 1 outputs the serial data as shown in SD of FIG. 5 and the M sequence generator 21 generates a pseudo random pulse train such as MP of FIG. The output of the OR circuit 23 is as shown in FIG. 5 SSD. That is,
Bits D _{0 to} D ₃ are scrambled by the pseudo random pulse train MP, and the serial data SD
Serial data SSD with complementary sign rule of D ₄ , ▲ ▼
Is output.

Therefore, if such serial data SSD is transmitted, the complementary code rule between D ₄ and ▲ ▼ is preserved, so the relay device or the receiving side can detect the complementary code as it is from the transmitted data. As a result, signal processing such as error checking and phase adjustment and descrambling processing can be performed easily and reliably. Further, since the scramble processing can be performed on the data after the insertion of the complementary code, the conversion from the parallel data D _{0 to} D ₄ to the serial data SD, that is, the addition of the extra bit by the speed conversion, and the addition of the complementary code to the extra bit are performed. It becomes possible to perform the insertion and the shift register 11 collectively, and as a result, the circuit configuration can be simplified and downsized.

The present invention is not limited to the above embodiment.
For example, although the scramble processing circuit is configured by using the M-sequence generator 21 in the above embodiment, it may be configured by using a self-periodic scramble circuit instead of the M-sequence generator 21 and the exclusive OR circuit 23. Good. FIG. 6 shows an example of the configuration, which is composed of shift registers 31 to 35 and exclusive OR circuits 36 and 37 having a five-stage configuration. Further, in the above embodiment, the load signal LOAD and the clock generated from the timing circuit 12 of the complementary code insertion circuit 1 in the control circuit 22
Although the control clock CS is generated using CLK1, it is also possible to detect the insertion position of the complementary code ▲ ▼ from the serial data SD and to generate the control clock CS based on the detection result. Further, in the above-described embodiment, as the complementary code insertion circuit, the shift register having the number of bits of parallel data D _{0 to} D ₄ + the number of input terminals of 1 is used, and the case of inserting the complementary code on the MSB side is described. A shift register having the maximum number of bits of data + 1 number of input terminals may be provided in advance, and the shift register may convert parallel data having less than the maximum number of bits. For example, when converting a video signal to a digital signal for transmission, the number of parallel data bits is 10
Since bits are enough, in this case, a shift register having input terminals for 10 + 1 bits is provided in advance,
In other cases using this shift register (for example, when the inverted output of the 8th bit is input to the 9th bit in 8 bits)
Parallel data may be converted. It is also possible to implement by providing the inverter 13 on the LSB side. By doing this, scrambling processing that preserves the complementary sign rule can be performed without changing the configuration of the conversion circuit.
It is possible to provide a circuit with a wide range of applications and versatility. In addition, since it is easy to form an integrated circuit, the circuit scale can be further reduced. In addition, the configuration of the complementary code inserting means and the scrambling processing means, the number n of bits of the input data, the number k of the complementary code and the insertion position of the complementary code, the load timing of the parallel data D _{0 to} D ₄ to the shift register, etc. As for the above, various modifications can be made without departing from the scope of the present invention.

[Effects of the Invention] As described in detail above, according to the present invention, n (n = 1, 2,
...) bit original data is converted into n + k (k = 1,2, ...) bit data, and a complementary code is inserted into the k bits and output, and the complementary code insertion is performed in synchronization with a clock. Means for generating a pseudo random code bit-synchronized with the data to be output, and scrambling processing of the data output from the complementary code inserting means by the pseudo random code generated by the pseudo random code generating means. And a control means for performing a scrambling process. The control means stops the clock input to the pseudo-random code generating means at the complementary code insertion position in the data output from the complementary code inserting means, and moves the position one bit before the complementary code inserting position. To prohibit the code change of the pseudo-random code from the position to the complementary code insertion position, thereby providing a signal conversion circuit with a simple circuit configuration and capable of reliably obtaining transmission data in which the complementary code rule is retained. You can

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a signal conversion circuit according to an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams showing a configuration of main parts of the circuit, and FIGS. 4 and 5 are FIG. 2 and A timing chart used for explaining the operation of the circuit shown in FIG. 3, FIG. 6 is a diagram showing a configuration of a scramble processing circuit of a signal conversion circuit in another embodiment of the present invention, and FIG. 7 is a conventional signal conversion circuit. FIG. 8 is a block diagram showing an example of the above, and FIG. 8 shows timings used for explaining the operation of the circuit. 1 ... Complementary code insertion circuit, 2 ... Scramble processing circuit,
11 …… Shift register, 12 …… Timing circuit, 13 ……
Inverter, 14 ... D flip-flop, 15 ... NOR gate, 21 ... M series generator, 22 ... Control circuit, 23 ... Exclusive OR circuit, 24 ... D flip-flop, 25 ... AND gate, 31 to 35 …… Shift register, 36,37 …… Exclusive OR circuit, D _{0 to} D ₄ …… Parallel data, ▲ ▼
…… Complementary code, CLK0 …… Clock according to parallel data cycle, CLK1 …… Clock according to serial data speed, LOAD …… Load signal, SD …… Serial data after complementary code insertion, MP …… Pseudo Random pulse train, CS …… Control clock, SSD …… Scrambled serial data.

Front page continuation (72) Inventor Masatoshi Wan, 2-2-1 Jinnan, Shibuya-ku, Tokyo Inside the Japan Broadcasting Corporation Broadcasting Center (72) Inventor Shizushi Kunishige 2-2-1, Jinnan, Shibuya-ku, Tokyo Japan Broadcasting Inside the Association Broadcasting Center (72) Inventor Taro Shibagaki 1 Kosuka Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Komukai Plant (72) Inventor Fumihiko Shimizu 1 Kosuka-Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Stock (72) Inventor Fumio Fujioka 3-1, 1-1 Asahigaoka, Hino-shi, Tokyo In-house Toshiba Hino Factory (72) Inventor Toshinori Kondo 3-1-1, Asahigaoka, Hino-shi, Tokyo Toshiba Hino Factory (56) Reference JP 62-38634 (JP, A) JP 63-146629 (JP, A)

Claims (1)

(57) [Claims] 1. The original data of n (n = 1, 2, ...) Bits is n +
Complementary code inserting means for converting into k (k = 1,2, ...) Bit data, inserting a complementary code into the k bits and outputting the data, and data output from the complementary code inserting means in synchronization with the clock. Pseudo-random code generating means for generating a pseudo-random code bit-synchronized with, and scrambling means for scrambling the data output from the complementary code inserting means by the pseudo-random code generated by the pseudo-random code generating means. , The clock input to the pseudo random code generating means is stopped at the complementary code insertion position in the data output from the complementary code inserting means, and the position from one bit before the complementary code inserting position to the complementary code inserting position is reached. A signal conversion circuit comprising: a control unit that prohibits a code change of the pseudo-random code.