JPH02179047A - Signal conversion circuit - Google Patents

Abstract

PURPOSE:To obtain a transmission data keeping surely a complementary coding rule with simple circuit constitution by generating a pseudo random code holding the complementary coding rule in a data outputted from a complementary encoding insertion means. CONSTITUTION:A complementary coding insertion circuit 1 converts an n-bit parallel original data into a data of (n+k)-bit, inserts a complementary code to the k-bit and outputs a serial data SD. On the other hand, a control circuit 22 receives a load signal LOAD and a clock CLK 1 from the insertion circuit 1 and outputs a control clock CS to an M-series generator 21. The generator 21 generates a pseudo random pulse train MP holding the complementary coding rule. An exclusive OR circuit 23 receiving the pulse train MP and the data SD scrambles the data by using the pulse train MP and a serial data SSD holding the complementary coding rule is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a signal conversion circuit used for reducing autocorrelation of transmitted data, for example in a video signal transmission device.

(Prior art) Both the NRZ code and the AMI code, which are often used as transmission codes, are “0” or “1” for a long period of time depending on the case.
may occur consecutively, which may cause problems in timing extraction. Furthermore, if the transmitted data has a repeating data pattern with a short period, the resulting single frequency component may cause cross-modulation or the like in the transmission line section. Conventionally, various means have been devised to prevent these problems, and one of them is, for example, converting the original data into a same-symbol continuous suppression code using a complementary code.

On the other hand, if original data portions corresponding to the complementary sign rule periodically exist in the original data, this may be detected incorrectly.

In order to avoid this, it is known that the original data is scrambled using a pseudo-random code string.

Another conventional circuit that uses complementary codes for original data and performs scrambling processing is, for example, the one shown in FIG. That is, the surplus bit addition circuit 51 and the complementary code addition circuit 53 are separated, and the original data DT is first introduced into the surplus bit addition circuit 51, where, for example, speed conversion is performed, so that the data is output at regular intervals as shown in FIG. Insert extra bits. Then, the scramble circuit 52 performs scrambling processing on the entire data ET after inserting the surplus bits, and then the data FT after the scramble processing is introduced into the complementary code addition circuit 53, where the surplus bits in the data FT are As shown in FIG. 8 GT, a complementary code of the previous code is inserted at the position, and the output thereof is sent out as transmission data GT. With such a configuration, since the complementary code agent is transmitted while being retained, the relay device or the receiving side can easily detect the complementary code and reliably perform predetermined processing such as descrambling. However, such a conventional circuit has the problem that the circuit configuration becomes complicated because the surplus bit addition circuit 51 and the complementary code addition circuit 53 must be provided separately and independently.

(Problem to be Solved by the Invention) As described above, the conventional signal conversion circuit has the problem that the circuit configuration becomes complicated when trying to hold the complementary code agent.The present invention focuses on this point. Another object of the present invention is to provide a signal conversion circuit that can obtain transmission data that reliably retains a complementary code agent with a simple circuit configuration.

[Structure of the Invention] (Means for Solving the Problems) The present invention converts n (n=1, 2,...) bits of original data into n+k (k=1.2...) bits of data. a pseudo-random code inserting means for inserting a complementary code into the bits of the bit, and a scrambling means, which retains the complementary code in the data output from the complementary code inserting means. A code is generated, and the pseudo-random code is used to scramble the data output from the complementary code insertion means.

(Function) As a result, according to the present invention, the transmission data is transmitted with the complementary code agent retained, so that the repeater on the transmission path or the receiving side can easily and reliably determine the position of the complementary code. It becomes possible to detect. Therefore, predetermined processing such as descrambling processing can be reliably performed on the transmitted data. In addition, since scrambling can be performed after inserting the complementary code, it is no longer necessary to perform the operation of adding surplus bits and the operation of adding complementary codes to the surplus bits independently through separate routes as in the past. , This allows the circuit configuration to be simplified.

(Embodiment) FIG. 1 shows the configuration of a signal conversion circuit in an embodiment of the present invention. This circuit is composed of a complementary code insertion circuit 1 and a scrambling processing circuit 2.

First, the complementary code insertion circuit 1 temporarily receives 5-bit parallel data D as the original data. -D4 is input, as shown in FIG.
The shift register 11 includes a parallel manual serial output type shift register 11, a timing circuit 12, and an inverter 13. Of these, the timing circuit 12 is composed of a D flip-flop 14 and a NOR gate 15. And parallel data D. - The clock CLKO corresponding to the period of D4 is set to the clock CLKO corresponding to the speed of the serial data SD (six times the parallel data Do-D4).
The load signal LOAD is latched by the D flip-flop 14 in synchronization with KI, and the Q output of the D flip-flop 14 and the clock CLKO are logically processed by the OR gate 15, and this load signal LOAD is sent to the shift register. It is supplied to load terminal LD of No. 11. The inverter 13 also receives parallel data D. -D
The bit 4 after this logic inversion is supplied to the input terminal P5 on the MSB side of the shift register 11.

Note that the clock CLKI is supplied as is to the shift clock input terminal CK of the shift register 11.

On the other hand, the scrample processing circuit 2 includes an M-sequence generator 21 that generates a pseudo-random pulse train MP, a control circuit 22 that controls the operation of this M-sequence generator 21, and serial data output from the complementary code insertion circuit 1. It is comprised of an exclusive OR circuit 23 that performs exclusive OR processing on the SD and the pseudo-random pulse train MP generated from the M-sequence generator 21 to scramble the serial data SD.

The control circuit 22 includes, for example, a D flip-flop 24 and an AND gate 25 as shown in FIG. Then, the load signal LOAD generated from the timing circuit 12 of the complementary code insertion circuit 1 is delayed and inverted by 1 bit in synchronization with the clock CLKI by the D flip-flop, and this 1-bit delayed inverted signal LOA is
D' gate-controls AND gate 25, thereby generating control clock C8.

With such a configuration, when parallel data Do-D4 is input to the complementary code insertion circuit 1, this parallel data D. -D4 is the input terminal Po-P of the shift register 11
4, and the above parallel data Do-
One bit D4 of D4 is logically inverted by the inverter 13 and then introduced to the input terminal P5 of the shift register 11 as a complementary code 4. In this state, the timing circuit 12
For example, when a load signal LOAD is generated as shown in FIG. 4 in synchronization with the arrival timing of the parallel data Do-D4, the parallel data Do-D4 and the complementary code D4 are shifted in synchronization with the load signal LOAD. are loaded into registers 11, respectively. Then, these parallel data Do-D4 and complementary code D4 are synchronized with the clock CLKI, and as shown in FIG. 4, starting with the parallel data Do, Dr r D 2 * D 3 +
The data are serially read out in the order of D 4 +complementary code D4 and output as serial data SD. That is, the shift register 11 outputs data SD in which the addition of surplus bits through parallel/serial conversion and the insertion of complementary codes into the surplus bits are performed simultaneously.

On the other hand, the scrample processing circuit 2 receives the load signal LO supplied from the timing circuit 12 of the complementary code insertion circuit 1.
Control clock C8 is created from AD and clock CLKI. This control clock C8 is obtained by omitting the pulse corresponding to the complementary code insertion circuit of the serial data SD, as shown in FIG. For this reason, M-sequence generator 2
1, in synchronization with the control clock C8, a pseudo-random pulse train MP in which sign change is prohibited is generated at the position corresponding to the complementary sign rule forming position D4*D4 of the serial data SD, as shown in FIG. be done.

Therefore, if the complementary code insertion circuit 1 to FIG.
Suppose that serial data as shown in FIG. 5 is output and a pseudo-random pulse train as shown in FIG. Become. That is, bit Do-
D3 is scrambled by the pseudo-random pulse train MP, and serial data SSD is output in which the complementary code rule of D4°D4 of the serial data SD is preserved.

Therefore, if such serial data SSD is transmitted, the complementary code rule between D4 + D4 is preserved, so the relay device or receiving side can easily and reliably detect the complementary code from the transmitted data. This allows error checking, signal processing such as phase adjustment, descrambling processing, etc. to be performed easily and reliably. In addition, since the data after complementary code insertion can be scrambled, serial data S
The shift register 11 can now perform the conversion to D, that is, the addition of surplus bits by speed conversion and the insertion of complementary codes to these surplus bits, all at once, and as a result, the circuit configuration can be easily miniaturized. be able to.

Note that the present invention is not limited to the above embodiments. For example, in the above embodiment, the scrambling processing circuit is configured using the M-sequence generator 21, but it may also be configured using a self-synchronous scrambling circuit instead of the M-sequence generator 21 and the exclusive OR circuit 23. good. FIG. 6 shows an example of the configuration, in which a five-stage shift register 31 to 3 is shown.
5 and exclusive OR circuits 36 and 37. Further, in the above embodiment, the load signal L generated from the timing circuit 12 of the complementary code insertion circuit 1 is used in the control circuit 22.
The control clock C8 is created using OAD and clock CLK1, but the serial data SD
The insertion position of the complementary code D4 may be detected from , and the control clock C8 may be created based on this detection result. Furthermore, in the above embodiment, as a complementary code insertion circuit, the parallel data Do
We have explained the case of inserting a complementary code on the MSB side using a shift register having the number of input terminals of ~D4 bit number + 1 bit, but the maximum number of bits of parallel data + 1
A shift register having the number of input terminals of bits may be provided in advance, and this shift register may convert parallel data having less than the maximum number of bits. For example, when converting a video signal into a digital signal and transmitting it, 10 bits is sufficient as the number of parallel data bits, so in this case, a shift register with input terminals for IO + 1 bit is provided in advance, and A register may be used to convert parallel data in other cases (for example, when the inverted output of the 8th bit is input to the 9th bit of 8 bits). Also, inverter 13 is set to L.
It can also be implemented by providing it on the SB side. In this way, it is possible to perform scrambling processing that preserves the complementary code agent without changing the configuration of the conversion circuit, and it is possible to provide a circuit that has a wide range of application and is rich in versatility. Further, since it becomes easy to integrate the circuit, the circuit scale can be further reduced. In addition, the configuration of the complementary code insertion means, the configuration of the scrambling processing means, the number of bits of input data n1
The number of bits of the complementary code, the insertion position of the complementary code, the loading timing of the parallel data D and -wD4 to the shift register, etc. can be modified in various ways without departing from the gist of the present invention.

[Effects of the Invention] As detailed above, according to the present invention, a pseudo-random code is generated that preserves the complementary code agent in the data output from the complementary code insertion means, and the pseudo-random code is used to insert the complementary code. By performing the scrambling process on the data output from the means, it is possible to provide a signal conversion circuit that has a simple circuit configuration and can obtain transmission data that reliably retains the complementary code agent.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a signal conversion circuit according to an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams showing the main part configuration of the circuit, and FIGS. FIG. 3 is a timing diagram used to explain the operation of the circuit shown in FIG. 6, a diagram showing the configuration of a scrambling circuit of a signal conversion circuit in another embodiment of the present invention, and FIG. 7 is a conventional signal conversion circuit. FIG. 8, a block diagram showing an example of the circuit, shows the timing used to explain the operation of the circuit. DESCRIPTION OF SYMBOLS 1... Complementary code insertion circuit, 2... Scramble processing circuit, 11... Shift register, 12... Timing circuit, 13... Inverter, 14... D flip-flop, 15... NOR gate , 21... M sequence generator, 22... Control circuit, 23... Exclusive OR circuit, 24... D flip-flop, 25... AND gate, 31-35... Shift register , 36.37・
...exclusive OR circuit, Do-D4...parallel data, Dl...complementary code, CLKO...clock according to the cycle of parallel data, CLKl...clock according to the speed of serial data, LOAD...load signal, SD...serial data after complementary code insertion, MP...
・Pseudo-random pulse train, C8... control clock, S
SD: Serial data after scramble processing. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] The original data of n (n=1, 2,...) bits is converted into n+k (
k=1, 2,...) bit data and inserts a complementary code into the k bits; and a pseudo code that maintains the complementary code rule in the data output from the complementary code inserting means. 1. A signal conversion circuit comprising: scrambling processing means for generating a random code and scrambling data output from the complementary code insertion means using the pseudo-random code.