KR950004542Y1 - Sub-code interface circuit - Google Patents

Abstract

No content.

Description

Subcode interface circuit

1 is a block diagram of a conventional subcode error correction circuit.

2 is a subcode data format explanatory diagram.

3 is a subcode interface circuit diagram of the present invention.

4 is a detailed circuit diagram of FIG. 3 and a first read clock generator.

5 is a timing diagram of each of the four sub waveforms.

6 is a detailed circuit diagram of FIG. 3 and a second read clock generator.

7 is a timing diagram of each of the six sub-waveforms.

* Explanation of symbols for main parts of the drawings

1: Compact Disk Digital Signal Processing

2: Subcode Interface 3: Error Correction

12: first read clock generator 13: second read clock generator

14: multiplexer 15: shift register

16: latch 31, 46: flip-flop

The present invention relates to an interface circuit for reading a video signal recorded in the sub (SUB) code area of a compact disc. In particular, the read clock is developed to read serial data to satisfy the first EIAJ and second EIAJ output formats. The subcode interface circuit converts and outputs the parallel data in synchronization with the output clock.

The conventional subcode error correction circuit processes a digital signal read from a compact disc, as shown in FIG. 1, and then outputs a synchronization signal SFSY, SBSY, and a subcode data signal SUB. When the synchronization signal SFSY, SBSY and the subcode data signal SUB are input from the signal disk digital signal processing section 1 and the compact disk digital signal processing section 1, the synchronization signal SCLK is inputted. And a subcode interface 2 for outputting a parallel data signal and applying a read clock RCK to the compact disc digital signal processing section 1, and a synchronization signal SCLK and a parallel data signal at the subcode interface 2; Is composed of an error correcting section 3 for correcting an error.

The operation of the conventional circuit configured as described above will be described in detail with reference to FIGS. 1 and 2.

The sub code data recorded in the sub (SUB) code area of the compact disc is recorded sequentially with 8 bits of data from P to W as one symbol as shown in FIG. Among them, P and Q are control signals used in audio signals, and the actual video signal constitutes one symbol with 6 bits from R to W. This signal is output after the compact disc digital signal processing section 1 performs EF (Eight Fourteen) demodulation.

One pack is composed of 24 symbols. After 4 packs, that is, 96 symbols, a synchronization signal for the symbol is generated. The synchronization signal generated for each symbol is referred to as SFSY. Since the 8-bit subcode data SUB is output in series through the parallel serial shift register in the compact disc digital signal processor 1, a read clock RCK is generated so that the subcode data SUB can be read externally. You have to.

The sub code interface 2 receives the synchronization signals SFSY and SBSY from the compact disc digital signal processor 1 and generates a read clock RCK capable of reading serial data, thereby generating a compact disc digital signal processor 1. After receiving the sub data SUB, the 6-bit or 8-bit parallel data and its synchronization signal SCLK are output to the error correction unit 3.

However, as described above, the subcode interface is a block in the Compact Disk Expanded Graphic IC, and there are no known circuits, and before the IC internal circuit of each manufacturer is examined in detail, the subcode interface is unknown. There was no problem.

In view of such a conventional problem, the present invention generates a read clock within itself according to the first and second EIAJ standards having different specifications, reads subcode data, and converts serial data into parallel data in synchronization. The sub-code interface circuit is designed to be described in detail with reference to the accompanying drawings as follows.

FIG. 1 is a circuit diagram of a subcode interface of the present invention. FIG. 4 is a detailed circuit diagram of a first read clock generator of FIG. 3, and FIG. 6 is a detailed circuit diagram of a second read clock generator of FIG. The first read clock generator 12 which receives the sync signal sbsy, the 1 symbol sync signal sfsy, and the clock CLK to generate a read clock RCK1 and a sync signal SCLK1 satisfying the first EIAJ standard. And a second read clock generator 13 for receiving the first symbol sync signal SFSY and the clock CLK to generate a read clock RCK2 and a sync signal SCLK2 satisfying a second EIAJ standard, and A multiplexer which receives the outputs of the first read clock generator 12 and the second read clock generator 13 and receives the control of the selection signal SEL and outputs the read clock RCK and the synchronization signal SCLK. (14) and the subcode data inputted to the terminal D by receiving the read clock RCK from the multiplexer 14 through the inverter 11; The shift register 15 for serially / parallel converting and outputting SUB and the subcode data inputted in parallel from the shift register 15 are latched and output by the synchronization signal SCLK inputted from the multiplexer 14. The latch 16 is used. The first read clock generator 12 uses the 96-symbol synchronous signal SBSY inputted to the terminal LD through the inverter 21 as a load signal, and the 1-symbol synchronous synchronizing signal inputted through the inverter 22 ( SFSY) as a clock to count the first binary counter 23, when the output of the first binary counter 23 is 97, the first clock generator 24 for outputting a low active one clock, and It receives the output of the first clock generator 24 and the output of the end gate 25 that receives the output of the inverters 21 and 22 as input signals, and receives the clock CLK through the inverter 26. A second clock generator (27) for counting; a second clock generator (28) for receiving the output of the second binary counter (27) and outputting a low active one clock at the K < th >clock; A third clock generator 29 that receives the output of the true counter 27 and outputs a low active 1 clock at the K + 8th clock; and the third clock generator 29 and the second clock generator 2 8, a flip-flop 31 receiving the output of the reset input R and the set input S, the output of the flip-flop 31 and the clock CLK as inputs, and a read clock RCK1. And an inverter 30 for outputting the synchronous signal SCLK1 by inverting the output of the end cage 25 and outputting the synchronization signal SCLK1. Binary counter 43, which receives one symbol synchronous signal SFSY as a load signal through inverter 41, receives clock CLK through inverter 42, and counts the binary counter 43. A first clock generator 44 that receives an output as an input and outputs a low active 1 clock at the Kth clock, and a low active 1 clock at the K + 8th clock as an input of the output of the binary counter 43 The second clock generator 45 and the output of the first clock generator 44 are applied to the set input S, and the output of the second clock generator 45 is reset. Consists of (R) flip-flop 46 and the flip-flop 46 is output as the clock AND gate 47 for outputting a read clock (RCK2) receiving (CLK) as an input is received by.

If described in detail with reference to the waveform diagram of Figure 5 and Figure 7 the effect of the present invention configured as described above.

In the case of the first EIAJ standard, the multiplexer 14 selects and outputs the output of the first read clock generator 12 by the external selection signal SEL, and in the case of the second EIAJ standard, the multiplexer 14 in the multiplexer 14 Select and export the output of 13). When the output read clock RCK is input to the compact disc digital signal processing (CDDSP) unit not shown in the figure, the compact disc digital signal processing unit outputs serial subcode data SUB.

When the subcode data SUB is input to the shift register 15 and the read clock RCK is inverted by the inverter 11 and input to the shift register 15, the shift register 15 is input to the input serial sub. Code data (SUB) is converted into 8-bit parallel data and output. When the parallel data is input from the shift register 15, the latch 16 outputs to the error correction unit not shown in synchronization with the one-symbol synchronization signal SCLK input to the clock.

Referring to the operation of the first read clock generation unit 12 in detail, the 96-symbol synchronous signal SBSY may be high in the 97th and 0th times, depending on the output of the compact disc digital signal processing unit (not shown). It may become high.

Even if only 0th is high, there is no subcode data SUB in the 97th 1-symbol sync signal SFSY.

Therefore, the read clock shown in FIG. 5 (c) in the 96-symbol sync signal SBSY and the 1-symbol sync signal SFSY of the first EIAJ standard shown in FIGS. 5 (a) and 5 (b), respectively, RCK1) is not generated in the 97th and 0th times of the 1 symbol synchronization signal SFSY shown in FIG. 5 (b), and only 8 clocks in the low state from the 1st to 96th remaining one symbol synchronization signal SFSY are shown. Is generated.

The first second counter 23 receives the 96 symbol synchronous signal SBSY through the inverter 21 as a load signal, and receives the 1 symbol synchronous signal SFSY as a clock through the inverter 22 to receive a binary count. When the 97th clock is reached, the first clock generator 24 generates a low-active one clock, and then gates the 96 symbol synchronization signal SBSY and the one symbol synchronization signal SFSY inverted with the clock signal. When the input operation is performed at (25) and the AND operation is performed, an inverted signal of FIG. 5 (d) is generated and becomes low from the high state of the 97th and 0th 1st symbol sync signal SFSY clock and the 1st symbol sync signal SFSY. The second binary counter 27 is prohibited from operating because a load signal having a value of zero is input.

By operating the second binary counter 27 only in the low state of the synchronization signal SCLK to operate the second clock generator 28 at the Kth clock, a low active signal is generated to set the flip-flop 31, and K By operating the third clock generator 29 at the + 8th clock, the low active signal is generated to reset the flip-flop 31, thereby generating a window for 8 clocks in the flip-flop 31. If the AND operation is performed through the clock CLK and the AND gate 32, only the eight clocks CLK pass through the clock CLK, and the read clock RCK is output as shown in FIGS. 5C and 5F.

The operation of the second read clock generator 13 will be described in detail. In the second EIAJ standard, there is no 96 symbol synchronous signal SBSY, and the one symbol synchronous signal SFSY is 97 as shown in FIG. 7 (a). And a high level in the clock period of 0, and a low state and a high state are constantly repeated in the remaining periods, that is, in the 1 to 96 clock periods.

As shown in FIGS. 7B and 7E, the read clock RCK2 generates eight clocks in the low state of the one-symbol sync signal SFSY, and thus, the compact disc digital signal processor. If input, the subcode data SUB is output.

The inverted output of the one-symbol synchronization signal SFSY is used as the clock of the third degree latch 16, that is, the synchronization signal of the parallel data, and the load signal of the binary counter 43, and the clock CLK is used. It is applied to the clock of the binary counter 43 through the inverter 42 and counted. The count value output from the binary counter 43 is supplied to the first clock generator 44 and the second clock generator 45. Enter it.

As such, when the output of the binary counter 43 is input, the first clock generator 44 outputs a low active 1 clock at the K th count value to set the flip-flop 46, and the second clock generator 45 A low active 1 clock is made at the K + 8th count value and the flip-flop 46 is reset to create a window for 8 clocks.

When the output of the flip-flop 46 and the clock CLK are ANDed through the AND gate 47, the read clock RCK2 for 8 clocks as shown in FIGS. 7B and 7E is generated.

As described in detail above, the present invention reads a subcode in accordance with the first and second EIAJ standards in a compact disc graphic or a compact disc expansion IC (IC), which is an image processing apparatus using a sub code of a compact disc, and then converts the data to correct the error. There is an effect that can be sent to the government.

Claims (1)

A first binary counter 23 that counts the inverted signals of the 96-symbol synchronous signal SBSY and the 1-symbol synchronous signal SFSY as a load signal and a clock signal, and 97 counts of the first binary counter 23; Inverter 30 by AND combining the first clock generator 24 which generates the clock by the output, the clock of the clock generator 24, and the inverted signals of the 96 symbol synchronous signal SBSY and the 1 symbol synchronous signal SFSY. A second binary counter that counts the AND gate 25 outputting the synchronization signal SCLK1 and the inverted signal of the AND gate 25 and the inverted signal CLK as load signals and clock signals. (27) Second and third clock generators 28 and 29, which generate clocks by counting the K and K + 8 counts of the second binary counter 27, and the second and third clock generators. The flip-flop 31, which is subjected to the set and reset control by the clocks (28) and (29), and the output signal of the flip-flop 31 and the clock CLK are AND-combined to the read clock RCK1. A first read clock generator 12 comprising an AND gate 32 and an inverted signal of the one symbol synchronous signal SFSY as a synchronous signal SCLK2, and output the first symbol synchronous signal SFSY and A binary counter 43 which counts the inverted signal of the clock CLK as a load signal and a clock signal, and first and second clocks generated by the K, K + 8 count outputs of the binary counter 43; Of the flip-flop 46 and the flip-flop 46 which are set and reset controlled by the clocks of the second clock generators 44 and 45 and the clocks of the first and second clock generators 44 and 45; A second read clock generation unit 13 including an AND gate 47 for outputting the output signal and the clock CLK by a weather clock RCK2, and outputting from the first read clock generation unit 12; The synchronization signal SCLK1 and the read clock RCK1 or the second read clock generator 13 output the synchronization signal SCLK2 and the read clock RCK2 according to the selection signal SEL for synchronization. A multiplexer 14 for outputting to the call SCLK and the read clock RCK, a shift register 15 for converting the subcode data SUB in parallel by an inverted signal of the read clock RCK, and the synchronization And a latch (16) for latching and outputting the output parallel data of the shift register (15) by a signal (SCLK).