JPH01212935A - Multiplex code conversion system - Google Patents

Abstract

PURPOSE:To suppress speed rise in a stage on the way of multiplexing and to attain multiplex processing utilizing a frame format of an input interface at a comparatively small speed increase by using a parallel/serial conversion section at the final stage in multiplication so as to apply C-bit insertion processing. CONSTITUTION:Control pulses A-E generated by a control signal generating circuit 15 having a 1/9 frequency division circuit are applied to an AND gate circuit 11 and an OR gate circuit 12 together with signals 1-1, 1-2, 1-3,-4-1, 4-2, 4-3 of input channels ch1-ch4 and inversion signals COM of signals 4-1, 4-2, 4-3 of the channel ch4 in a parallel/serial conversion circuit with an 8B1C code generating function, then an 8B1C code Q is outputted at an output terminal Q of a flip-flop 14. Moreover, there is a relation of m=kn (k is 1, 2,...) between the value (m) of the mB1C code to be generated and the multiplex channel number (n) and the mB1C code is obtained by adding a control pulse generated by a control signal generating circuit having a 1/(1+m) frequency divider with respect to the input channels ch1-chn and the inverted signal of the signal of the channel chn.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides BSI (Bit 5equuece
The present invention relates to a multiplex code conversion method used for the purpose of converting an image into an image (Indepandanca).

(Prior art) [1] C bit insertion method Conventionally, C bit insertion method in the multiplexing process of a multiplexing terminal relay device
As a multiplex code conversion method for obtaining multiple codes by inserting bits, there are the following methods.

FIGS. 6A and 6B, and FIGS. 7A and 7B are explanatory diagrams showing examples of the conventional C bit insertion method. This is a case where a 10-bit IC bit code (hereinafter referred to as 10BIC code) is obtained by adding one C bit to an information bit.

Note that the explanation focuses only on the information bits and C bits.

(i) Case of Serial Processing FIG. 6A shows a case where C bits are inserted by serial processing into an already multiplexed signal sequence.

In FIG. 6A, 1 is a processing section, and speed conversion section IA
, a scrambling unit IB, and a C bit insertion unit IC. fo is the frequency of the low-order group input.

fc is the frequency of only C bits.

6A and 6B, the input signal ■ consisting of the multiplexed signal P is converted into
The position for the bit is secured.

That is, the C bit position is secured every time 10 bits of the input signal ■ are input (signal ■ in FIGS. 6A and 6B), and this signal ■ is scrambled by the scrambler IB (signal ■ in FIGS. 6A and 6B). Finally, the C bit insertion unit IC converts the inverted value of the previous bit to the C bit shown in Figure 6B.
By inserting it into the bit position, a 10BIC code ■ is obtained.

(...) In the case of parallel processing FIGS. 7A and 7B show the case of the C bit insertion method in the case of parallel processing, which is a method in which processing is performed in a low-speed operating part before multiplexing.

In FIGS. 7A and 7B, each channel Ch1 to c
As in the case of serial processing, the speed conversion section IA of the processing section 1 performs speed conversion on the input signals respectively input to h4 to secure the C bit position. After that, the scrambling unit IB performs scrambling, inserts a mark "1" into the C bit position, and outputs the result (see Fig. 7A and Fig. 7).
Signal in figure B). Appropriate delays are applied to these outputs by delay elements 2 (signals ■ in Figures 7A and 7B), and parallel/serial conversion is performed by parallel/serial conversion circuit 3 to multiplexed signal P'. C bit position every 11 bits (
mark) appears (signal ■ in Figures 7A and 7B),
Finally, the C bit conversion circuit 4 converts the C pit position I! By rewriting (mark) with the inverted value of the immediately preceding bit, a 10BIC code ■ is obtained.

(Fast) When using a parallel/serial conversion circuit FIG. 8A is an explanatory diagram showing an example of a method for inserting a C bit using a parallel/serial conversion circuit.

In FIG. 8A, 3' is a parallel/serial conversion circuit, and 5 is an inverter.

As shown in FIG. 8A, this method uses a parallel/serial conversion circuit 3' for (n+1) multiplexing when performing n-channel multiplexing, and sets one channel to the inverted value of the previous channel. m81G code is obtained. however,
In this case, since m = n, the smaller the number of multiplexed channels n, the greater the speed increase.

[2] Channel selection control method (i) In the case of serial processing If a frame exists in the multiplexed signal, channel selection is performed simultaneously by synchronizing the frame of the signal. If a frame exists in the multiplexed signal, this is the same as in the case of parallel processing, which will be described later.

(5) In the case of parallel When multiplexed signals are expanded in parallel by a serial/parallel conversion circuit, the position of the output channel of the serial/parallel conversion circuit is generally undefined. This situation is shown in FIG.

As shown in Figure 9, channels chi, ch2, ch
3. When the signals multiplexed in the order of ch4 are serial/parallel converted by the serial/parallel conversion circuit 6, the output channels are in the order of chi, ch2, . Although the order of ch3 to ch4 is maintained, which channel is output to which terminal 9 is undefined. Therefore, in order to establish a channel, it is necessary to have a function of extracting channel information from parallel expanded signals and controlling the serial/parallel conversion circuit 6. In general,
The frame synchronization circuit 10 performs frame synchronization on each of the parallel developed signals, detects the channel identification bit BS in the frame, and detects the channel identification bit B.
Since the serial/parallel conversion circuit 6 is controlled by S through the channel control circuit 8A, until the correct channel is output to the correct terminal 9, (frame synchronization is established)
→ (Detection of channel identification bit B) → (Control of serial/parallel conversion circuit 6) → The following operations are repeated.

(in) When using a serial/parallel conversion circuit As in the example shown in FIG. 8A above, if the C bit is the inverted value of a certain channel on the transmitting side, on the receiving side,
As shown in FIG. 8B, it is also possible to perform channel selection control using the regularity of these two channels.

In FIG. 8B, 6 is a serial/parallel conversion circuit, 7 is a comparator, and 8 is a channel control circuit.

In the example shown in FIG. 8B, the signal of channel n and its inverted signal are connected to the output terminal n of the serial/parallel conversion circuit 6 and (n + 1
), the regularity of the two channel signals appears, so the comparator circuit 7 detects this and
Channel control can be performed through the channel control circuit 8 based on the detected value.

[Problem to be solved by the invention]

However, in the conventional multiplex code conversion system shown in FIGS. 8A and 8B, when multiplexing n channels, the parallel/serial conversion circuit 3 and the serial/parallel conversion circuit 6 for multiplexing (n+1) are used. In this case, m = n, so the smaller the number of multiplexed channels, the greater the speed increase. There was a problem.

That is, in general, in ultra-high-speed transmission systems, a parallel processing configuration (Figure 7A) is adopted due to hardware constraints, but in the above-mentioned configuration, speed conversion is performed in the lowest-stage low-speed processing section, and C Since the bit positions are inserted, the frame format of the input interface cannot be preserved. On the other hand, the configuration of FIG. 4, it becomes a 4BIC code and the speed increase rate is 1.25), so there was a problem that it was not suitable for ultra-high speed transmission systems.

Furthermore, in the conventional multiplex code conversion method shown in FIG. 9 described above, until the correct channel is output to the correct terminal 9,
Since the following operations are repeated: (establishment of frame synchronization) -> (detection of channel identification bit B) -> (control of serial/parallel conversion circuit 6) ->..., there is a problem in that channel selection control takes time.

The present invention has been made to solve the above problems.

SUMMARY OF THE INVENTION An object of the present invention is to reduce the speed increase rate when inserting C bits in the multiplexing process in a multiplexing code conversion method of a multiplexing terminal relay device.

The object of the present invention is to provide a technology that allows flexible and easy multiplex configuration.

Another object of the present invention is to provide a multiplex code conversion method for a multiplex terminal relay device, in which a serial/parallel converter on the receiving side:
It is an object of the present invention to provide a technique that performs channel selection control using inserted C bits and can facilitate multiplex configuration and shorten channel selection control time compared to conventional channel selection control.

The above and other objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the present invention provides a multiplexing code conversion method that inserts C bits in the multiplexing process of a multiplexing terminal relay device, and on the transmitting side, for an input signal of n channels,
Each time channels 1 to nti- are multiplexed, one C bit, which is the inverted value of a specific channel, is added, and the receiving side checks the regularity of the C bit inserted on the transmitting side and the specific channel. The main feature is that channel selection is performed based on the channel selection method.

[Effect]

According to the above-mentioned means, by performing C bit insertion processing in the parallel/serial converter at the final stage of multiplexing, speed increase in the middle stage of multiplexing is suppressed, and multiplex processing is performed using the frame format of the input interface. can be performed with a relatively small speed increase, making it easy to perform flexible processing.

Also, in the serial/parallel converter on the receiving side, the inserted C
Channel selection control is performed based on bits, and compared to conventional channel selection control, multiplexing configuration can be facilitated and channel selection control time can be shortened.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail based on the drawings.

In addition, in all the times for explaining the example.

Components having the same function are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiment 1] FIG. 1A is a block circuit diagram for explaining the schematic configuration of a parallel/serial conversion circuit with an 88IC code generation function, which is an embodiment of the multiplex code conversion method of the present invention. 1B
This figure is a time chart for explaining the operation of the parallel/serial conversion circuit with 88IC code generation function shown in FIG. 1A.

In FIG. 1A, 11 is an AND gate circuit, 12 is an O
An R gate circuit, 13 and 14 are flip-flops, and 15 is a control signal generation circuit having a 179 frequency dividing circuit.

As shown in FIGS. 1 and 1B, the parallel/serial conversion circuit with 8BIC code generation function of the first embodiment has an input channel c
hi to ch4 signals 1-1.1-2.1-2.1-3,
2-1.2-2.2-3゜3-1.3-2.3-3.4
-1.4-2.4-3 and channel ch4 signal 4-1
．． 4-2.4-3 inversion signal COM (signal 4-1.4
-2.4co1), AND the control pulse A-E generated by the control signal generation circuit 15 having a 179 frequency dividing circuit.
By adding using the gate circuit 11 and the OR gate circuit 12, the 88IC code Q is outputted to the output terminal Q of the flip-flop 14 as shown in the time chart shown in FIG. 1B. The clock CLK has a frequency shown in equation 1 (1).

CLK frequency = (input signal frequency) x (multiplexing number) x
(Speed increase rate due to C bit) (1) The frequencies of C and LK are, for example, phase-locked loop (
PLL: Phase Locked Loop
) created by the circuit. In this example, (the frequency of the input signal) is x4x9/8, so it is sufficient to supply a clock with a frequency 4.5 times that of the input signal.

The control signal generation circuit 15 generates the control pulse A by combining the frequency-divided outputs of a Johnson ring counter, etc.
-E can be generated.

Codes other than 8BIC can be generated using a circuit similar to the circuit shown in FIG. 1A, but there is a relationship expressed by equation (2) between the mBIC code that can be generated and the number of multiplexed channels n.

m=kn"""e(2) In Equation (2), =1.2.3....

The mB1G code is obtained by adding a control pulse generated by a control signal generation circuit having a 1/(m+1) frequency divider to the inverted signals of input channels chi-chn and channel chn.

In this way, by incorporating a means for inserting the C bit of the mBIC transmission line code into the parallel/serial conversion circuit and performing the C bit insertion process in the parallel/serial conversion section at the final stage in multiplexing, multiplexing is possible. It is possible to suppress the speed increase during the middle stages of processing and perform multiple processing using the frame format of the input interface with a relatively small speed increase, making it possible to easily perform flexible processing.

[Embodiment 2] FIG. 2A is a block circuit diagram for explaining the schematic configuration of a serial/parallel conversion circuit with a channel selection function for 88 IC code, which is an embodiment of the multiplex code conversion method of the present invention. , FIG. 2B is a time cheat for explaining the operation of the serial/parallel conversion circuit with channel selection function for 88IC code shown in FIG. 2A.

2A and 2B, 21.22 is a flip-flop, 23 is an exclusive OR circuit, 24 is a control signal generation circuit having a 179 frequency division circuit, 25 is a control signal generation circuit having a 174 frequency division circuit, 26 is a phase locked loop (PLL) circuit for determining the frequency period, and 27 is an inverter for signal inversion.

As shown in FIGS. 2A and 2B, the serial/parallel conversion circuit with a channel selection function for 88IC code of this embodiment inputs an input signal (8B I C code) through five flip-flops 2.
1 in parallel and is driven by control signals A to E generated by a control signal generation circuit 24 having a 179 frequency divider circuit.

The output terminal Q of the flip-flop 21 receives the output signal Q1~
Q5 is output.

Here, the control signal generation circuit 24 having a 179 frequency dividing circuit
is similar to the control signal generation circuit 15 shown in the first embodiment. Output signals Q4 and Q5 are output from exclusive OR circuit 2.
Exclusive OR is performed using 3 and used as the channel control signal (C bit check signal) C8. Since the value of channel control signal C8 is always "1" only when channel 4 and C bit during multiplexing are output to output signals Q4 and Q5, channel control can be performed based on this. becomes.

The output signals Q1 to Q4 are again input to the flip-flop 22 and read out using the original low-order group clock. The first clock (CLKI) of the input signal includes a speed increase by the C bit, so it is connected to a suitable phase-locked loop (
PLL) circuit 26 generates a second clock (CLK2) from which it is removed.

Frequency of CLK2 = (Frequency of CLKI) x (Reciprocal of speed increase rate) (3) In this example, the frequency of CLK2 is 879 times the frequency of CLKI. By generating control signals A' to D' from this CLK2 in a control signal generating circuit 25 having a 174 frequency dividing circuit and driving the flip-flop 22 at the subsequent stage, the low-order group signals of channels chi to channel ch4 are output. Ru. The control signal generating circuit 25 having a 1/4 frequency dividing circuit can also be realized by a circuit similar to the control signal generating circuit 24 having a 1/9 frequency dividing circuit.

Parallel/with m81G code generation function on the transmitting side that satisfies formula (2)
The serial/parallel conversion circuit with mBIC code channel selection function on the receiving side facing the serial conversion circuit is as follows.

It can be realized by a circuit similar to the circuit shown in FIG. 2A. .

By doing this, the serial/parallel converter on the receiving side performs channel selection control based on the inserted C bit, and compared to conventional channel selection control, multiplexing configuration can be easily controlled and selection control can be performed. time can be shortened.

[Embodiment 3] Figures 3A and 3B show that a parallel/serial conversion circuit with a C bit insertion function according to an embodiment of the multiplex code conversion method of the present invention is used in the final stage of multiplexing, and FIG. 3A is a block circuit diagram illustrating a schematic configuration of a multiplexing device that is capable of holding a synchronized frame format, in which FIG. 3A shows a circuit on the transmitting side, and FIG. 3B shows a circuit on the receiving side.

In FIGS. 3A and 3B, 31 and 32 are synchronous multiplex processing units, 33 are parallel/serial conversion circuits with a C bit insertion function,
34 is a transmitter, 35 is a receiver, 36 is a serial/parallel conversion circuit with a channel selection function, 3? , 38 is a synchronization separation processing unit;
f, is the frequency of the low-order group input signal.

A multiplexing device that uses the parallel/serial conversion circuit with the C bit insertion function of Example 3 in the final stage of multiplexing and can maintain the synchronization frame format in the intermediate stage is shown in Figures 3A and 3B. As shown in the figure, this is an example of multiplexing and demultiplexing using a three-stage configuration of 4x4x4, and the synchronization frame format is maintained at each stage of multiplexing in both the transmitting and receiving circuits, and the input Output interface (f,,4f
,.

16 f,) can be provided.

In addition, the speed increase in this case is (m+1)/m, where m=8
1,125 when m=12, 1.083 when m=12,
The conventional examples (1) -(ni) and (2) -(
When using method iii) (m = 4.

The speed increase is small compared to the speed increase of 1.25).

Furthermore, in the repeater, the synchronous interface of the input/output interface 16f shown in FIGS. 3A and 3B can be taken out simply by using a serial/parallel conversion circuit with a channel selection function, and the signal can be inserted into this signal. It is also possible to perform extraction (Add-Drop).

Note that Add-Drop is a function of extracting or inserting a signal of an arbitrary channel in a flowing multiplexed signal, and is possible only when the frame format is maintained.

(Embodiment 4) FIGS. 4A and 4B show a multi-stage multiplexer in which each stage uses a parallel/serial converter with a C bit insertion function according to an embodiment of the multiplex code conversion method of the present invention. FIG. 4A is a block circuit diagram for explaining a schematic configuration example of the converting device, and FIG. 4A is a circuit on the transmitting side, and FIG. 4B is a circuit on the receiving side.

In Fig. 4A and Fig. 4B, 41.41' is a module for low-order group (f, interface), 42.42'
is a module for higher order group (4f0 interface), 43,
43' is a module for higher order group (16f, interface), 44.45.46 is a parallel/serial conversion circuit with C bit insertion function, 47 is a transmitter, 48 is a receiver, 49 is a C bit detection check circuit, 50.51 .52 is a serial/parallel conversion circuit with a channel selection function, and f6 is a bit rate of a low-order group input signal.

A multistage multiplexing device using the parallel/serial conversion circuit with C bit insertion function of this embodiment 4 in each stage is shown in FIGS. 4A and 4B.
As shown in the figure, this is an example of 64 multiplexing and demultiplexing using a 4X4X4 three-stage configuration.

In this example, the C bit is inserted in the parallel/serial conversion circuits 44, 45, and 46 at each stage on the transmitting side, so the speed increase is somewhat large. /Parallel conversion circuit 50°51.52,
Since channel selection control is performed using the C bit at each stage, the channel selection control time can be significantly reduced compared to conventional methods.

In this case, the speed increase is (m+1)"/m".

When m = 8, it is 1,424, and when m = 12, it is 1.271, but in the conventional example (13-(ni) and (2)
- (in) method (m=4, speed increase 1.
953), the speed increase is extremely small.

Next, we will discuss the multiplex code conversion methods of the first to fourth embodiments of the present invention, the conventional parallel/serial conversion circuit, and the serial/serial conversion circuit.
FIG. 5 shows a comparison of the speed increase rate with a multiplex code conversion method using a parallel conversion circuit.

In FIG. 5, (a) is a speed increase rate curve in the case of the multiplex code conversion method according to the first embodiment and the second embodiment of the present invention, and (b) is the speed increase rate curve in the case of the multiplex code conversion method according to the first embodiment and the second embodiment of the present invention. It is a speed increase rate curve in the case of a multiplex code conversion method. Also, (c)
is the speed increase rate curve in the case of the conventional multiplex code conversion method shown in FIGS. 8A and 8B, and (d) is the speed increase rate curve in the case of the conventional
The multiplex code conversion method shown in Figure A and 8B is n=4X4
It is a speed increase rate curve when used in 3-stage multiplexing of ×4.

As can be seen from the above description, according to the embodiment of the present invention, the configuration is relatively simple, the speed increase rate is small, and the C
A parallel/serial conversion circuit with a bit addition function and a serial/parallel conversion circuit with a channel selection function using the C bit can be obtained.

If you use these to increase the speed by inserting C bits at the final stage of multiplexing, that is, just before sending out to the transmission path, the input frame format will be maintained while retaining the input frame format in the middle stages of multiplexing. processing becomes possible. As a result, it is possible to multiplex inputs in the high-order group synchronization frame format, which is currently being standardized in TIL, while maintaining the frame format, and to realize a multiplexing terminal device capable of accommodating inputs of each order group. becomes possible.

In addition, compatibility with the higher-order group frame format means that end-station relay equipment (input terminals) that can extract and insert signals
Many advantages can be expected, such as the feasibility of multiplex code conversion methods such as d-Drop-MUX).

On the other hand, by using the parallel/serial conversion circuit with the C-bit addition function and the serial/parallel conversion circuit with the channel selection function according to the embodiment of the present invention at each stage of multiplexing, channel selection control is improved compared to the conventional method. It is also possible to realize a configuration method that takes significantly less time. (However, in this case, the frame format cannot be maintained in the middle of the process.) Furthermore, a parallel/serial conversion circuit with a C bit insertion function.

By combining the serial/parallel conversion circuits with channel selection functions into one chip, it is expected that reliability and economical efficiency will be improved.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As described above, according to the present invention, by performing C bit insertion processing in the final stage parallel/serial converter in multiplexing, speed increase in the middle stage of multiplexing is suppressed,
Since multiple processing using the frame format of the input interface can be performed with a relatively small increase in speed, flexible processing can be easily performed.

Also, in the serial/parallel converter on the receiving side, the inserted C
Since channel selection control is performed using bits, multiplexing configuration can be made easier and selection control time can be shortened compared to conventional channel selection control.

[Brief explanation of the drawing]

FIG. 1A is a block circuit diagram for explaining the schematic configuration of a parallel/serial conversion circuit with an 88IC code generation function, which is an embodiment of the multiplex code conversion method of the present invention. FIG. 1B is a time chart for explaining the operation of the parallel/serial conversion circuit with 88IC code generation function shown in FIG. 1A. FIG. 2A is a block circuit diagram for explaining the schematic configuration of a serial/parallel conversion circuit with a channel selection function for 88 IC code, which is an embodiment of the multiplex code conversion method of the present invention. FIG. 2B is a time cheat for explaining the operation of the serial/parallel conversion circuit with channel selection function for 88IC code shown in FIG. A block circuit for explaining the schematic configuration of a multiplexing device that uses an embodiment of a parallel/serial conversion circuit with a C bit insertion function in the final stage of multiplexing and makes it possible to maintain a synchronization frame format in the intermediate stage. figure. 4A and 4B are schematic configurations of a multistage multiplexing device using a parallel/serial conversion circuit with a C bit insertion function in each stage, which is an embodiment of the multiplex code conversion method of the present invention. A block circuit diagram for explaining an example, FIG. Graph showing experimental results for comparing the speed increase rate with the multiplex code conversion method. Figure 6A, Figure 6B, Figure 7A, Figure 7B, Figure 8A,
FIGS. 8B and 9 are diagrams for explaining the problems of the conventional multiplex code conversion system. In the figure, 11...AND gate circuit, 12...OR gate circuit, 13.14...flip-flop, 15...
...Control signal generation circuit having a 1.79 frequency dividing circuit, 2
1.22...Flip chip, 23...Exclusive OR circuit, 24...Control signal generation circuit having a 179 frequency division circuit, 25...Control signal generation circuit having a 174 frequency division circuit, 26 ...Phase Locked Loop (PLL) circuit for frequency periods. 27... Inverter for signal inversion, 31. 32... Synchronous multiplexing unit, 33... Parallel/serial conversion circuit with C bit insertion function, 34... Transmitter, 35... Receiver, 36
...Direct/parallel conversion circuit with channel selection function, 3? ,
38... Synchronization separation processing unit, 41.41'... Module for low-order group (f, interface), 42.42
'...Module for higher order group (4f1 interface),
43.43'...Module for higher order group (16f. interface), 44.45.46...
・Parallel/serial conversion circuit with C bit insertion function, 47...Transmitter, 48...Receiver, 46...C bit detection circuit, 50.51.52...Series/parallel with channel selection function It is a conversion circuit.

Claims (1)

[Claims] (1) In a multiplex code conversion method that inserts redundant bits for suppressing consecutive same codes in the multiplex processing process of a multiplex terminal relay device, on the transmitting side, channels 1 to n are input to input signals of n channels. Every time multiplexing is performed k times, one redundant bit, which is the inverted value of a certain channel, is added, and the receiving side selects a channel based on the regularity of the redundant bit inserted on the transmitting side and the specific channel. A multiplex code conversion method characterized by performing the following.