KR960004708B1 - Frame synchronization detection method and its circuit of demux of data transmission system - Google Patents

Abstract

The parallel frame synchronous detection is adopted to detect the synchronous signal to reduce time necessary to detect the synchronous signal. The circuit comprises D-flipflops(DF11-DF13) for latching and shifting data transmitted through data input stage according to the clock signal, a counter(CNT) for dividing frequency of a clock signal, D-flipflops(DF14-DF16) for latching output signal of the D-flipflops(DF11-DF13) and for outputting the latched signal by 3bit units, D-flipflops(U50-U63) for shifting output signal of the D-flipflops(DF14-DF16) by 4bits, and AND gates(AN1-AN10) and NAND gates(U64-U66) for operating output signal of the D-flipflops(U50-U63).

Description

Frame Synchronization Detection Circuit of Demultiplexing of Data Transmission System

1 is a conventional circuit diagram.

2 is a circuit diagram according to the present invention.

3 is a concrete circuit diagram of the serial / parallel conversion circuit 200 of FIG.

4-6 show timing diagrams in accordance with the present invention.

The present invention relates to a frame synchronization signal detection circuit for demultiplexing a DS4 signal of a synchronous detection circuit transmission system. In particular, a frame synchronization for demultiplexing a data transmission system that can shorten a detection time by using a parallel frame synchronization signal detection method. It relates to a detection circuit.

In general, a frame signal is detected when receiving data demultiplexed by a data transmission apparatus. Furthermore, in the case of a frame detection circuit configured as shown in FIG. 1, a series of DS4 data is shifted in a shift register SR1-SR12 of 12 steps. When the output state of the output terminal Q of the 12-stage shift registers SR1-SR12 is in the state of " 111110100000 " of FAW (Frane Alignment Word), the frame synchronization signal is detected. The synchronization signal is applied to separate the three-channel subordinate signal and the maintenance signal from the input signal by making the timing signal for the demultiplexing function. The frame synchronization algorithm by detecting the frame synchronization signal is as follows. The first frame synchronization loss is determined as frame synchronization loss when receiving four consecutive wrong frame synchronization signals (FAW) at the expected position. The second frame synchronization loss is detected when frame synchronization signal is detected three times consecutively. I think that has recovered. As described above, however, the frame synchronization signal is detected as a 12-stage shift register state by shifting a series of synchronization detection circuits, so that there is a problem that time delay occurs due to the state processing.

Accordingly, an object of the present invention is to provide a circuit which can reduce the detection time and improve the efficiency by processing in parallel when detecting the frame synchronization signal from three separate data by serial / parallel conversion of the DS4 signal.

According to the present invention for performing the above object, a serial / parallel conversion means for converting and outputting transmission serial data into n parallel bits by n bits according to an input start time point, and an output unit divided into n of the serial / parallel conversion means. Shifting means for outputting a frame synchronizing signal by shifting the signal to a frame;

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a circuit diagram according to the present invention. The serial / parallel conversion circuit 200 and the serial / parallel conversion circuit 200 converting and outputting in parallel by dividing the output into three parts by four bits through the serial synchronous detection circuit input terminal D1. ), And the AND gate (AN1-AN10) and the NAND gate (U64-U66) for determining an input time point from the outputs of the output terminals of the flip-flop (U50-U63) shifted by 4 bits of It is composed of

FIG. 3 is a detailed circuit diagram of the serial / parallel conversion circuit 200 of FIG. 2, which deflects and shifts the data of the synchronous detection circuit input terminal DI1 in sequence according to the clock input of the clock terminal CK. DF13, the counter CNT divides the clock of the clock stage CK, and the outputs of the deflip-flops DF11-DF13 according to the output of the counter CNT, and classifies three bits into cycles. It is composed of output flip-flops (DF14-DF16).

4 to 6 are operational timing diagrams of FIGS. 2 to 3 according to the present invention.

Therefore, a specific embodiment of the present invention will be described in detail with reference to FIGS. 2 to 6, in which data corresponding to a DS4 signal is input to a total of 12-bit inputs to the serial / parallel conversion circuit 200 through the data input terminal DI1. According to the data entry time, it is classified into three cases. Specifically, referring to FIG. 3, when the FAW synchronous detection circuit, that is, 111111100000 is input in series to the data input terminal D1, the deflip-flop DF11-DF13 is driven by the clock of the clock terminal CK. It is shifted and the output of the output terminal Q is input to the data terminal D of the flip-flop DF14-DF16. The flip-flop DF14-DF16 latches the output of the output terminal Q of the deflip-flop DF11-DF16 according to the output of the counter CNT, and the counter CNT is a signal of the clock terminal CK. Divide by 3 to print.

When latching the state of the data input terminal D of the flip-flop DF14-DF16 according to the three-divided output of the counter CNT, the output terminal (D1) is output as follows according to the data input time input to the data input terminal D1. dt1-dt3) occur in three cases.

1) When detected in ONE

dt1 stage status 1 1 1 0

dt2 stage status 1 0 0 0

2) When detected by TWO

dt1 stage status X 1 0 0 0

dt2-stage state 1 1 1 0 X

dt3-stage status 1 1 0 0 X

3) when detected in Thr

dt1 stage status X 1 1 0 0

dt2-stage state X 1 0 0 0

dt3-stage state 1 1 1 0 X

This may be illustrated in the timing diagrams of FIGS. 4 through 6.

That is, in FIG. 4, dt1-dt3 is One, in FIG. 5, dt1-dt3 is two, and in FIG. 6, dt1-dt3 is the Thr.

The above-mentioned signals of dt1-dt3 are inputted to the buffers U41, U42, and U49 to the flip-flop U50, U51, and U52. However, in the initial state, “high” is applied to the clear stage CLR and output from the inverter U39 to the low level. At this time, all of the clear stages LDN of the flip-flop U50-U63 become low, and the state of the output terminal Q becomes low. Subsequently, when the clock of the clock stage CLK is applied to the clock stage D of the flip-flop U50-U63 and is applied to the dt1-dt3 stage as shown in FIGS. The outputs of U52, U53, and U54 are shifted to be in the state of dout1-dout5, and the outputs of the other flip-flop U55-U63 are output from the NAND gates U64-U26 through the AND gates U43-U48. A division signal for one1, two, and thr is generated, and an SPL signal is generated through the NAND gate U26.

Therefore, when detected in one, dout1-dout3 data is separated into CH1, CH2 and CH3 data, and when detected in two, dout4 and dout1 data are separated into CH1, CH2 and CH3 data, and when detected in thr, dout5, dout1, dout2 data is separated into CH1, CH2, and CH3 data.

As described above, all 12-bit frame sync signals are detected when the serial frame sync signal is detected. However, the parallel frame sync signal detection processes 4-5 bits of signals in parallel, thereby shortening the detection time of the frame sync signal and performing an efficient function. can do.

Claims (1)

In the frame synchronous detection circuit during demultiplexing of the data transmission system, a de-flip flop (DF11-DF13) which latches and shifts data of the data input terminal D1 in sequence according to the clock input of the clock terminal CK, and the clock stage. A counter CNT that divides the clock of CK into three, and a de-flip flop DF14 which latches the output of the de-flip flops DF11 to DF13 according to the output of the counter CNT, and classifies and outputs three bits. The input time is determined from the output of the flip-flop U50-U63, which shifts the output of the flip-flop DF14-DF16 by four bits, and the output of the output of the flip-flop U50-U63. And an AND gate (AN1-AN10) and a NAND gate (U64-U66).