KR100353533B1 - Delay locked loop circuit - Google Patents

Abstract

The present invention relates to a delay lock loop circuit of a semiconductor memory device, in which a unit delay stage consisting of a NAND gate and a unit delay stage consisting of a NOR gate are alternately connected in series to each other, and a first pulse signal is used as a first unit delay stage. The second pulse signal is input, and from the second unit delay stage, the output signal of the previous unit delay stage is input, and the second pulse signal and the third pulse signal in phase opposite to the second pulse signal are alternately inputted. A delay chain for generating a fourth pulse signal from the last unit delay stage, an output signal for the unit delay stage, a reset signal, and a control signal, respectively; and a signal received at the unit delay stage by the control signal, respectively; Shifter means composed of multiple flip-flops for shift output And a plurality of logic gates that alternately receive an output signal and an output bar signal output from two adjacent flip-flops among the plurality of flip-flops, and also use a clock signal as an input, the last of the plurality of logic gates As the first logic gate, logic means for receiving the output signal of the last flip-flop among the plurality of flip-flops, the clock signal and the lock control signal, and a unit delay stage consisting of a NOR gate and a unit delay stage consisting of a NAND gate are alternated with each other. The first unit delay stage receives the output signal and the clock signal of the last logic gate of the plurality of logic gates, and from the second unit delay stage, the output signal of the previous unit delay stage and the Two adjacent logics among multiple logic gates Data output signal and output bar signal are alternately received, and the last unit delay stage receives the output signal of the first logic gate of the logic gates and the output signal of the unit delay stage of the preceding stage. And a replication delay means for generating a clock signal having the same phase.

Description

Delay locked loop circuit

The present invention relates to a delay locked loop (also referred to as a "DLL") circuit of a semiconductor memory device. More specifically, the present invention relates to a unit delay composed of two input NAND gates and an inverter. By reducing the delay gate, the delay lock loop circuit can double the resolution of the DLL and accurately compensate for the clock and data, or skew between the external clock and the internal clock.

In general, a delay lock loop circuit (DLL) is a device that receives a clock signal input from the outside of the system and generates an internal clock signal necessary for the inside of the system to be synchronized with the phase of the clock signal input from the outside. In this case, the system includes all of a logic device or a semiconductor device using an external clock signal. For example, the DLL circuit may be used in various types of logic devices as well as cache memory devices that speed up data processing between the central processing unit and the DRAM of the computer, or may be applied to a synchro DRAM, a Rambus DRAM, or the like.

Next, the principle of the conventional DLL circuit will be described with reference to the external clock signal clk and the data output signal dout shown in FIG.

As shown in the figure, when data is sent out in synchronization with the clock clk, skew by td1 is generated. To compensate for this, an internal clock (dll_clk) signal that is advanced by td1 before the clock (clk) signal is used. When data is output in accordance with the internal clock dll_clk signal, an output signal dout 'coinciding with the external clock clk (a) can be obtained as shown in Fig. 1D. As described above, the internal clock dll_clk signal c is a clock that is advanced by td1 to the external clock clk, but is actually a signal produced by delaying the external clock clk by td2. That is, td2 = tck-td1, so it looks like a clock that is advanced by td1 at the rear.

FIG. 2 is a block diagram of a conventional DLL circuit, and includes an output signal matching unit 100, a control signal generator 200, and a DLL generator 300.

The output signal matching unit 100 receives an external clock signal clk to generate a clock signal clk_dout having the same timing as the output signal dout. The control signal generator 200 generates a control signal (measure, shift, shift_reset) by inputting a clock signal (clk_dout) which is an output signal of the external clock (clk) and the output signal matching unit (100). Serve These control signals (measure, shift, shift_reset) are respectively input to the DLL generator 300 together with an external clock signal (clk). At this time, the DLL generator 300 generates the 'dll_clk' signal as shown in FIG. 1C to compensate for the skew using these signals.

3 is a circuit diagram of the DLL generator 300 shown in FIG. 2, a delay chain 10 including a plurality of unit delays 12 including two input NAND gates and an inverter, and each unit delay ( Input signals by a plurality of shifter units 20 for receiving and storing the output signals of 12) and a plurality of NOR gates that respectively input output signals and clock signals clk of the two adjacent shifter units 20. A lock unit for locking a circuit and a clock output signal (clk_out) for compensating skew between a clock and data or an external clock and an internal clock by inputting an output signal of each NOR gate. The replication delay chain portion 30 is configured.

FIG. 4 shows an output signal 'ga' of the unit delay shown in FIG. 3 and an output signal 'b' of the shifter circuit unit, respectively.

The output signal of each unit delay ('A' of FIG. 4) outputs a pulse signal whose edge section is reduced by the time delayed in each unit delay. Therefore, the more the unit delay passes, the smaller the output pulse width.

On the other hand, each output signal ('b' in FIG. 4) of the shift circuit unit 20 outputs a pulse signal polled low by the polling period of the shift signal.

The digital DLL method connects dozens of unit delay elements in series, extracts the appropriate output, and synchronizes clock and data, or external and internal clocks. At this time, how accurately the DLL removes the clock skew is determined by the unit device delay.

However, in the conventional delay lock loop circuit configured as described above, there is a problem in that the unit delay of the delay chain has two gate delays of two input NAND gates and an inverter, and the resolution of the DLL is not good. (In this case, the lower the unit delay, the better the resolution. The higher the unit delay, the lower the resolution of the DLL.)

Accordingly, the present invention has been made to solve the above problems, and the present invention reduces the unit delay composed of two input NAND gates and an inverter to one delay gate, thereby doubling the resolution of the DLL. It is an object of the present invention to provide a delay lock loop circuit capable of accurately compensating clock and data or skew between an external clock and an internal clock.

1 is an operation timing diagram for explaining the operation principle of a conventional DLL circuit

2 is a block diagram of a conventional DLL circuit

3 is a circuit diagram of the DLL generator shown in FIG.

4 is an operation waveform diagram of each part of FIG.

5 is an operation timing diagram for explaining the operation principle of the DLL circuit of the present invention;

6 is a configuration diagram of the DLL circuit according to the first embodiment of the present invention.

7A and 7B are output waveform diagrams showing simulation results of the present invention.

8 is a configuration diagram of a DLL circuit according to a second embodiment of the present invention.

9 is a configuration diagram of a DLL circuit according to a third embodiment of the present invention.

10 is a configuration diagram of a DLL circuit according to a fourth embodiment of the present invention.

11 is a configuration diagram of a DLL circuit according to a fifth embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: output signal matching circuit 200: control signal generation circuit

300: DLL generating circuit 10: Delay chain part

12,14,16: Unit delay stage 20: Shift and lock circuit

22: shifter circuit stage 30: replication delay chain portion

32, 34, 36: duplicate unit delay stage 40: conversion circuit section

In order to achieve the above object, in the delay lock loop circuit of the present invention, a unit delay stage consisting of a NAND gate and a unit delay stage consisting of a NOR gate are alternately connected to each other in series, and a first pulse signal is used as a first unit delay stage. And a second pulse signal are input, and from the second unit delay stage, the output signal of the previous unit delay stage is input, and the second pulse signal and the third pulse signal in phase opposite to the second pulse signal are alternately inputted. And a delay chain generating a fourth pulse signal from the last unit delay stage, an output signal, a reset signal, and a control signal of the unit delay stage, respectively, and receiving the signal received at the unit delay stage by the control signal. A shifter means composed of a plurality of flip-flops each shifted and outputted, It consists of a plurality of logic gates that alternately receive the output signal and the output bar signal output from two adjacent flip-flops among the plurality of flip-flops, and also use a clock signal as an input, the last of the plurality of logic gates As logic gates, logic means for receiving the output signal of the last flip-flop among the plurality of flip-flops, the clock signal and the lock control signal, and a unit delay stage consisting of a NOR gate and a unit delay stage consisting of a NAND gate are alternated with each other. Receive the output signal and the clock signal of the last logic gate of the plurality of logic gates in the first unit delay stage, and the output signal of the previous unit delay stage and the plurality of unit delay stages from the second unit delay stage. Two adjacent logic gays of the two logic gates The output signal of the logic gate and the output bar signal are alternately received, and the last unit delay stage receives the output signal of the first logic gate among the logic gates and the output signal of the unit delay stage of the preceding stage. A copy delay means for generating the same clock signal is provided.

The logic means may be configured by a three input NAND gate or a three input NOR gate, and may be configured by alternately replacing the three input NOR gate and the NAND gate.

The copy delay chain means is preferably configured such that two input NOR gates and NAND gates alternate with each other.

In addition, a conversion means connected to an output terminal of the replication delay chain means and equalizing the phase of the clock signal passing through the even-numbered replication delay chain means and the clock signal passing through the odd-numbered replication delay chain means are further provided. can do. In this case, the conversion means preferably comprises a first transfer gate, an inverter connected in parallel with the first transfer gate, and a second transfer gate.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

5 shows the operation timing for explaining the operation principle of the DLL circuit of the present invention.

First, a reference waveform (c) waveform having a pulse width of td2 is generated using two waveforms of the clock signal clk (a) and the clock output signal clk_dout (b). The 'clk_dout' signal b is a delay of the clock signal clk through the same path as the output signal dout and has the same timing as the 'dout' signal. Next, the pulse width of the 'measure' waveform c is changed to the delay of the delay chain to generate the 'dll_clk' signal d. In other words, a delay-pulse-delay conversion method is used, in which a delay to be compensated is converted into a pulse and the delay is converted into a delay.

6 is a block diagram of a DLL circuit according to a first embodiment of the present invention, in which a unit delay 14 composed of one 2-input NAND gate and a unit delay 16 composed of one 2-input NOR gate are alternately configured. A plurality of shifter circuits 20 for storing the output of each unit delay chain by inputting the delay chain 10 and the output signal, the shift reset signal shift_reset, and the shift signal of each unit delay chain; The NOR gate receives the output signal of the two adjacent shifter circuits 20 and the clock signal clk, and the NOR gate allows the clock to be delayed by a delay to compensate for the clock skew, and the output signal of the NOR gate. It consists of a duplicate delay chain section 30 for outputting a pulse signal having the same delay as the delay chain.

The operation by the above configuration will be described in detail with reference to the simulation result waveform diagram shown in FIG.

First, the two-input NAND gate outputs 'high' unconditionally when one input is 'low' and the output outputs the opposite signal of the other input when one input is 'high'. The two-input NOR gate outputs 'low' unconditionally when one input is 'high' and outputs the opposite signal of the other input when one input is 'low'. Using this property, the present invention forms a unit delay chain with one gate.

When the 'measure' signal is 'low' (measureb = 'high'), the output of the NAND gate is unconditionally 'high', and the output of the NOR gate unconditionally outputs 'low'. That is, the output of the odd unit delay (NAND) has an unconditional high, and the output of the even unit delay (NOR) unconditionally outputs a low.

When the 'measure' signal becomes 'high' (measureb = 'low'), the delay chain is enabled, while at the same time the 'high' signal is transmitted alternately between 'low', 'high', 'low', and 'high'. do. At this time, before the clock skew of td2 is compensated for, the NAND gate output outputs 'low' and the NOR gate output outputs 'high'. On the other hand, after the clock skew by td2 is compensated, the output of the opposite direction, that is, the NAND gate output is 'high' and the NOR gate output is 'low'. The output of the unit delay is then stored in the shift. When the shift signal is 'high', the shifter circuit unit 20 outputs the stored value.

The first of the inputs of the three-input NOR gate 32 of the replication delay chain is a clock (clk) signal for compensating clock skew, and the second and third inputs are connected in odd and even numbers differently. The second and third inputs of the odd third input NOR gate are inputted with the stored value of the odd shifter and the stored value of the next shifter, respectively. That is, the two inputs of the odd third input NOR gate are connected to the output of the odd shifter and the output of the shifter of the next stage.

Next, the input of the even third input NOR gate is input as opposed to the input of the odd third input NOR gate. The second and third inputs are the opposite of the stored value of the even shifter and the stored value of the shifter of the next stage. The opposites are entered respectively. That is, the two inputs of the even third input NOR gate are connected to the output bar signal outb of the even shifter and the output bar signal outb of the next shifter. If any one of the inputs of the 3-input NOR gate is present, its output will be output unconditionally regardless of the other input conditions, so the remaining 3 except for the 3-input NOR gate, which is delayed to compensate for clock skew, The output of the input NOR gate will output 'low' unconditionally regardless of other inputs. As shown in the figure, only a circled three-input NOR gate passes a clock to compensate for clock skew. Since the clock entering this point passes the same number of unit delay chains as set by the pulse width of the 'measure' signal, the 'dll_clk' signal is delayed by the clock width, i.e. td2, so the clock skew is delayed. You can compensate.

The unit delay element of the conventional digital DLL circuit is composed of a two-input NAND gate and an inverter and uses two gate delays. In the DLL circuit of the present invention, a unit delay element is used alternately between the two-input NAND gate and the two-input NOR gate. The unit delay can be reduced. Therefore, by reducing the unit delay of the present invention in half, the DLL resolution can be doubled.

As an essential part of the present invention, a method of compensating clock skew using a unit delay having one gate delay can be diversified.

FIG. 8 is a configuration diagram of a DLL circuit according to a second embodiment of the present invention. The difference from FIG. 6 is that the unit delay element of the delay chain alternates between the two input NOR gate 16 and the two input NAND gate 14. To reduce unit delay.

FIG. 9 is a configuration diagram of a DLL circuit according to a third embodiment of the present invention. The difference from FIG. 6 is a clock signal delayed by a clock skew to be compensated by inputting output signals and clock signals of two adjacent shifter circuits. The output logic gate is composed of NAND gates.

FIG. 10 is a diagram illustrating the configuration of a DLL circuit according to a fourth embodiment of the present invention, in which a phase of the clock signal passing through the even-numbered replication delay chain and the clock signal passing through the odd-numbered replication delay chain are equalized. Means were further implemented at the output terminals. This is because the phase of the clock passing through the three-input NAND gate and the three-input NOR gate is reversed, so that the conversion means 40 is added at the end of the replication delay chain. That is, the compensated clock that passed through the three-input NAND gate is exported as it is, and the compensated clock that passed through the three-input NOR gate is shifted out of phase so that the phase of the compensated clock passed through the three-input NAND gate and the three-input NOR gate is the same. It was made. There are many ways to control this, but we used signals to control the replication delay chain. For example, if the clock being compensated passes through a three-input NOR gate, the outputs of all three-input NAND gates remain 'high'. Also, if the clock to be compensated passes through the three-input NAND gate, the outputs of the three-input NOR gate are all kept low. Therefore, you can control the output using these two characteristics.

FIG. 11 is a diagram illustrating the configuration of a DLL circuit according to a fourth embodiment of the present invention, wherein the order of two input NAND gates and two input NOR gates of a replication delay chain is changed in a manner different from that of FIG. 10.

As described above, according to the delay lock loop circuit of the present invention, a unit delay composed of a two-input NAND gate and an inverter is alternately used as a NAND gate and a NOR gate, thereby doubling the resolution of the DLL and increasing the clock ( It has the effect of accurately compensating the clock and data, or skew between the external clock and the internal clock.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (8)

In a delay lock loop circuit of a semiconductor memory device, The unit delay stage consisting of the NAND gate and the unit delay stage consisting of the NOR gate are alternately connected to each other in series, and the first and second pulse signals are input to the first unit delay stage. A delay chain in which an output signal of a unit delay stage is input, a second pulse signal and a third pulse signal in phase opposite to the second pulse signal are alternately inputted, and a fourth pulse signal is generated from the last unit delay stage. and, Shifter means for receiving an output signal of the unit delay stage, a reset signal and a control signal, respectively and shifting and outputting a signal received at the unit delay stage by the control signal, respectively; Comprising a plurality of logic gates that alternately receive the output signal and the output bar signal output from two adjacent flip-flops of the plurality of flip-flops, and also the clock signal as an input, the last of the plurality of logic gates Logic gates include logic means for receiving the output signal of the last flip-flop of the plurality of flip-flops, the clock signal and the lock control signal; A unit delay stage consisting of a NOR gate and a unit delay stage consisting of a NAND gate are alternately connected in series, and the first unit delay stage receives an output signal and a clock signal of the last logical gate of the plurality of logic gates. From the second unit delay stage, the output signal of the previous unit delay stage and the output signal and the output bar signal of two adjacent logic gates among the plurality of logic gates are alternately received. The last unit delay stage includes the logic gate. A delay lock loop circuit comprising: a copy delay means for receiving an output signal of a first logic gate and an output signal of a unit delay stage of the first stage and generating a clock signal having the same phase as the received clock signal. The method of claim 1, And the logic gate comprises a three input NAND gate. The method of claim 1, And the logic gate comprises a three input NOR gate. The method of claim 1, And the logic gate is configured by alternating a three-input NOR gate and a NAND gate. The method of claim 1, And said replica delay means comprises a two-input NOR gate and a NAND gate alternating with each other. The method of claim 1, And a conversion means connected to an output terminal of said replication delay means and equalizing the phase of the clock signal passing through the even-number replication delay chain means and the clock signal passing through the odd-numbered replication delay chain means. Delay lock loop circuit. The method of claim 6, And said converting means comprises a first transfer gate, an inverter connected in parallel with said first transfer gate, and a second transfer gate. delete